From 52c4ae8ac0005a96cdf79be4628c21ae41fca6ca Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 17 Dec 2020 20:29:45 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index fb98095fb..e6fddced9 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -65,6 +65,7 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest) * `RM-2P-1S1D` Twin Predication (src=1, dest=1) * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed) +* `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update ## RM-1P-3S1D @@ -122,10 +123,12 @@ Otherwise the normal SV hardware for-loop applies. The three registers each may note in [[discussion]]: TODO, evaluate if 2nd SUBVL should be added. conclusion: no. 2nd SUBVL makes no sense except for mv, and that is covered by [[mv.vec]] -## RM-2P-2S1D +## RM-2P-2S1D/1S2D The primary purpose for this encoding is for Twin Predication on LOAD and STORE operations. see [[sv/ldst]] for detailed anslysis. +RM-2P-2S1D: + | Field Name | Field bits | Description | |------------|------------|----------------------------| | MASK_KIND | `0` | Execution Mask Kind | @@ -139,6 +142,8 @@ The primary purpose for this encoding is for Twin Predication on LOAD and STORE | ELWIDTH_SRC | `17:18` | Element Width for Source | | MODE | `19:23` | see [[discussion]] | +Note that for 1S2P the EXTRA2 dest and src names are switched. + ## R\*_EXTRA2 and R\*_EXTRA3 Encoding (**TODO: 2-bit version of the table, just like in the original SVPrefix. This is important, to save bits on 4-operand instructions such as fmadd**) -- 2.30.2