From 52de0895f546da29a7da0cebb80753096dd8427d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 1 Jun 2020 03:25:39 +0100 Subject: [PATCH] minor adjustment, zero test in ALU output stage --- src/soc/fu/common_output_stage.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index 1b37a625..576f88a5 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -34,7 +34,7 @@ class CommonOutputStage(PipeModBase): comb += self.o.xer_ca.ok.eq(op.output_carry) # create condition register cr0 and sticky-overflow - is_zero = Signal(reset_less=True) + is_nzero = Signal(reset_less=True) is_positive = Signal(reset_less=True) is_negative = Signal(reset_less=True) msb_test = Signal(reset_less=True) # set equal to MSB, invert if OP=CMP @@ -50,14 +50,14 @@ class CommonOutputStage(PipeModBase): comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP) comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB) comb += msb_test.eq(target[-1] ^ is_cmp) - comb += is_zero.eq(target == 0) - comb += is_positive.eq(~is_zero & ~msb_test) - comb += is_negative.eq(~is_zero & msb_test) + comb += is_nzero.eq(target.bool()) + comb += is_positive.eq(is_nzero & ~msb_test) + comb += is_negative.eq(is_nzero & msb_test) with m.If(is_cmpeqb): comb += cr0.eq(self.i.cr0.data) with m.Else(): - comb += cr0.eq(Cat(self.so, is_zero, is_positive, is_negative)) + comb += cr0.eq(Cat(self.so, ~is_nzero, is_positive, is_negative)) # copy out [inverted] cr0, output, and context out comb += self.o.o.data.eq(o) -- 2.30.2