From 52e43496a121bca2eee5664843de69faa646c94f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 30 Nov 2021 18:29:41 +0000 Subject: [PATCH] start allocating more FUs (more ReservationStations) --- src/soc/fu/compunits/compunits.py | 4 ++-- src/soc/simple/core.py | 6 +++++- src/soc/simple/test/test_core.py | 17 +++++++++++++---- 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index be3d4e69..6c6866cf 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -179,8 +179,8 @@ class FunctionUnitBaseMulti(ReservationStations2): class ALUFunctionUnit(FunctionUnitBaseMulti): fnunit = Function.ALU - def __init__(self, idx): - super().__init__(ALUPipeSpec, ALUBasePipe, 1) + def __init__(self, num_rses): + super().__init__(ALUPipeSpec, ALUBasePipe, num_rses) #class LogicalFunctionUnit(FunctionUnitBaseSingle): diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 825c7d4d..fdc8d20b 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -137,6 +137,9 @@ class NonProductionCore(ControlBase): self.decoders = {} self.des = {} + # eep, these should be *per FU* i.e. for FunctionUnitBaseMulti + # they should be shared (put into the ALU *once*). + for funame, fu in self.fus.fus.items(): f_name = fu.fnunit.name fnunit = fu.fnunit.value @@ -145,6 +148,7 @@ class NonProductionCore(ControlBase): # TRAP decoder is the *main* decoder self.trapunit = funame continue + assert funame not in self.decoders self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name, final=True, state=self.ireg.state, @@ -226,7 +230,7 @@ class NonProductionCore(ControlBase): # connect each satellite decoder and give it the instruction. # as subset decoders this massively reduces wire fanout given # the large number of ALUs - m.submodules["dec_%s" % v.fn_name] = v + m.submodules["dec_%s" % k] = v comb += v.dec.raw_opcode_in.eq(self.ireg.raw_insn_i) comb += v.dec.bigendian.eq(self.ireg.bigendian_i) # sigh due to SVP64 RA_OR_ZERO detection connect these too diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 479299ce..ee8581e9 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -43,7 +43,8 @@ from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase from soc.fu.cr.test.test_pipe_caller import CRTestCase from soc.fu.branch.test.test_pipe_caller import BranchTestCase from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase -from openpower.test.general.overlap_hazards import HazardTestCase +from openpower.test.general.overlap_hazards import (HazardTestCase, + RandomHazardTestCase) from openpower.util import spr_to_fast_reg from openpower.consts import StateRegsEnum @@ -212,10 +213,17 @@ class TestRunner(FHDLTestCase): comb = m.d.comb instruction = Signal(32) + units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, + 'spr': 1, + 'logical': 1, + 'mul': 1, + 'div': 1, 'shiftrot': 1} + pspec = TestMemPspec(ldst_ifacetype='testpi', imem_ifacetype='', addr_wid=48, mask_wid=8, + units=units, allow_overlap=True, reg_wid=64) @@ -344,12 +352,13 @@ class TestRunner(FHDLTestCase): if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - suite.addTest(TestRunner(HazardTestCase().test_data)) + #suite.addTest(TestRunner(HazardTestCase().test_data)) + suite.addTest(TestRunner(RandomHazardTestCase().test_data)) #suite.addTest(TestRunner(LDSTTestCase().test_data)) #suite.addTest(TestRunner(CRTestCase().test_data)) #suite.addTest(TestRunner(ShiftRotTestCase().test_data)) - suite.addTest(TestRunner(LogicalTestCase().test_data)) - suite.addTest(TestRunner(ALUTestCase().test_data)) + #suite.addTest(TestRunner(LogicalTestCase().test_data)) + #suite.addTest(TestRunner(ALUTestCase().test_data)) #suite.addTest(TestRunner(BranchTestCase().test_data)) runner = unittest.TextTestRunner() -- 2.30.2