From 52f6c8cc31f553ba2005892fcf2ca9b5f10bac91 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 21 Nov 2016 12:27:47 +0100 Subject: [PATCH] etnaviv: align TS surface size to number of pixel pipes The TS surface gets cleared by a tiled RS fill. If the chip has more than 1 pixel pipe the size of the TS surface needs to be aligned so that each pipe address matches a tile start, otherwise the RS will hang. Signed-off-by: Lucas Stach Reviewed-by: Wladimir J. van der Laan --- src/gallium/drivers/etnaviv/etnaviv_resource.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c index 1f0582ce0bf..5f2b63f97c1 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_resource.c +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c @@ -52,7 +52,8 @@ etna_screen_resource_alloc_ts(struct pipe_screen *pscreen, /* TS only for level 0 -- XXX is this formula correct? */ pixels = rsc->levels[0].layer_stride / util_format_get_blocksize(rsc->base.format); - ts_layer_stride = align(pixels * screen->specs.bits_per_tile / 0x80, 0x100); + ts_layer_stride = align(pixels * screen->specs.bits_per_tile / 0x80, + 0x100 * screen->specs.pixel_pipes); rt_ts_size = ts_layer_stride * rsc->base.array_size; if (rt_ts_size == 0) return true; -- 2.30.2