From 52fceb441aabe2bd632bbeb88b8173735f7e9064 Mon Sep 17 00:00:00 2001 From: Sofiane Naci Date: Thu, 18 Jul 2013 09:16:05 +0000 Subject: [PATCH] arm.md (attribute "insn"): Delete values "mrs", "msr", "xtab" and "sat". * config/arm/arm.md (attribute "insn"): Delete values "mrs", "msr", "xtab" and "sat". Move value "clz" from here to ... (attriubte "type"): ... here. (satsi_): Delete "insn" attribute. (satsi__shift): Likewise. (arm_zero_extendqisi2addsi): Likewise. (arm_extendqisi2addsi): Likewise. (clzsi2): Update for attribute changes. (rbitsi2): Likewise. * config/arm/arm-fixed.md (arm_ssatsihi_shift): Delete "insn" attribute. (arm_usatsihi): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. From-SVN: r201025 --- gcc/ChangeLog | 15 +++++++++++++++ gcc/config/arm/arm-fixed.md | 5 ++--- gcc/config/arm/arm.md | 16 +++++++--------- gcc/config/arm/cortex-a8.md | 2 +- 4 files changed, 25 insertions(+), 13 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f77bae41c8b..5d65d181d49 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2013-07-18 Sofiane Naci + + * config/arm/arm.md (attribute "insn"): Delete values "mrs", "msr", + "xtab" and "sat". Move value "clz" from here to ... + (attriubte "type"): ... here. + (satsi_): Delete "insn" attribute. + (satsi__shift): Likewise. + (arm_zero_extendqisi2addsi): Likewise. + (arm_extendqisi2addsi): Likewise. + (clzsi2): Update for attribute changes. + (rbitsi2): Likewise. + * config/arm/arm-fixed.md (arm_ssatsihi_shift): Delete "insn" attribute. + (arm_usatsihi): Likewise. + * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. + 2013-07-18 Sofiane Naci * config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md index 82a7add9f3e..474100cdf92 100644 --- a/gcc/config/arm/arm-fixed.md +++ b/gcc/config/arm/arm-fixed.md @@ -383,7 +383,6 @@ "ssat%?\\t%0, #16, %2%S1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "insn" "sat") (set_attr "shift" "1") (set_attr "type" "arlo_shift")]) @@ -393,5 +392,5 @@ "TARGET_INT_SIMD" "usat%?\\t%0, #16, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") - (set_attr "insn" "sat")]) + (set_attr "predicable_short_it" "no")] +) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 52b61d66e9d..e7eb428e44a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -250,7 +250,7 @@ ;; scheduling information. (define_attr "insn" - "mov,mvn,clz,mrs,msr,xtab,sat,other" + "mov,mvn,other" (const_string "other")) ; TYPE attribute is used to classify instructions for use in scheduling. @@ -271,6 +271,7 @@ ; block blockage insn, this blocks all functional units. ; branch branch. ; call subroutine call. +; clz count leading zeros (CLZ). ; extend extend instruction (SXTB, SXTH, UXTB, UXTH). ; f_2_r transfer from float to core (no memory needed). ; f_cvt conversion between float and integral. @@ -412,7 +413,7 @@ block,\ branch,\ call,\ - complex,\ + clz,\ extend,\ f_2_r,\ f_cvt,\ @@ -4036,8 +4037,8 @@ else return "usat%?\t%0, %1, %3"; } - [(set_attr "predicable" "yes") - (set_attr "insn" "sat")]) + [(set_attr "predicable" "yes")] +) (define_insn "*satsi__shift" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -4062,7 +4063,6 @@ return "usat%?\t%0, %1, %4%S3"; } [(set_attr "predicable" "yes") - (set_attr "insn" "sat") (set_attr "shift" "3") (set_attr "type" "arlo_shift")]) @@ -5669,7 +5669,6 @@ "uxtab%?\\t%0, %2, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "insn" "xtab") (set_attr "type" "arlo_shift")] ) @@ -6020,7 +6019,6 @@ "TARGET_INT_SIMD" "sxtab%?\\t%0, %2, %1" [(set_attr "type" "arlo_shift") - (set_attr "insn" "xtab") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")] ) @@ -12472,7 +12470,7 @@ "TARGET_32BIT && arm_arch5" "clz%?\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "insn" "clz")]) + (set_attr "type" "clz")]) (define_insn "rbitsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -12480,7 +12478,7 @@ "TARGET_32BIT && arm_arch_thumb2" "rbit%?\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "insn" "clz")]) + (set_attr "type" "clz")]) (define_expand "ctzsi2" [(set (match_operand:SI 0 "s_register_operand" "") diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index 067ff1c8b1e..65a97500826 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -88,7 +88,7 @@ (ior (and (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg") (eq_attr "neon_type" "none")) (not (eq_attr "insn" "mov,mvn"))) - (eq_attr "insn" "clz"))) + (eq_attr "type" "clz"))) "cortex_a8_default") (define_insn_reservation "cortex_a8_alu_shift" 2 -- 2.30.2