From 5304c3d604ddca0861fe09c9423f03dd459cf099 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 29 Jul 2019 16:03:16 +0100 Subject: [PATCH] tidyup --- src/ieee754/fpdiv/pipeline.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py index 278e1804..499bd79c 100644 --- a/src/ieee754/fpdiv/pipeline.py +++ b/src/ieee754/fpdiv/pipeline.py @@ -159,15 +159,14 @@ class FPDIVMuxInOut(ReservationStations): def __init__(self, width, num_rows, op_wid=2): self.id_wid = num_bits(num_rows) self.pspec = PipelineSpec(width, self.id_wid, op_wid) + # get the standard mantissa width, store in the pspec fmt = FPFormat.standard(width) log2_radix = 3 # tested options so far: 1, 2 and 3. - n_comb_stages = 2 # 2 compute stages per pipeline stage + # extra bits needed: guard + round (sticky comes from remainer.bool()) fraction_width = fmt.fraction_width - - # extra bits needed: guard + round fraction_width += 2 # rounding width to a multiple of log2_radix is not needed, -- 2.30.2