From 532efd5651344827f13744860e271d900a6cdc75 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 28 Apr 2021 10:15:13 +0000 Subject: [PATCH] shrinking regfile sizes some more --- experiments9/non_generated/libresoc.v | 59884 ++++++++++++------------ 1 file changed, 29903 insertions(+), 29981 deletions(-) diff --git a/experiments9/non_generated/libresoc.v b/experiments9/non_generated/libresoc.v index ccb3448..9b02e13 100644 --- a/experiments9/non_generated/libresoc.v +++ b/experiments9/non_generated/libresoc.v @@ -13,7 +13,7 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec19_cr_in; reg [2:0] ALU_dec19_cr_in; (* enum_base_type = "CROutSel" *) @@ -23,17 +23,17 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec19_cr_out; reg [2:0] ALU_dec19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec19_cry_in; reg [1:0] ALU_dec19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec19_cry_out; reg ALU_dec19_cry_out; (* enum_base_type = "Function" *) @@ -51,7 +51,7 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] ALU_dec19_function_unit; reg [13:0] ALU_dec19_function_unit; (* enum_base_type = "In1Sel" *) @@ -60,7 +60,7 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec19_in1_sel; reg [2:0] ALU_dec19_in1_sel; (* enum_base_type = "In2Sel" *) @@ -78,7 +78,7 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec19_in2_sel; reg [3:0] ALU_dec19_in2_sel; (* enum_base_type = "MicrOp" *) @@ -156,16 +156,16 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec19_internal_op; reg [6:0] ALU_dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec19_inv_a; reg ALU_dec19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec19_inv_out; reg ALU_dec19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec19_is_32b; reg ALU_dec19_is_32b; (* enum_base_type = "LdstLen" *) @@ -174,29 +174,29 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec19_ldst_len; reg [3:0] ALU_dec19_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec19_rc_sel; reg [1:0] ALU_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec19_sgn; reg ALU_dec19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; always @* begin if (\initial ) begin end ALU_dec19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_function_unit = 14'h0002; endcase @@ -204,9 +204,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_inv_a = 1'h0; endcase @@ -214,9 +214,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_inv_out = 1'h0; endcase @@ -224,9 +224,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_cry_out = 1'h0; endcase @@ -234,9 +234,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_is_32b = 1'h0; endcase @@ -244,9 +244,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_sgn = 1'h0; endcase @@ -254,9 +254,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_internal_op = 7'h24; endcase @@ -264,9 +264,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_in1_sel = 3'h0; endcase @@ -274,9 +274,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_in2_sel = 4'h0; endcase @@ -284,9 +284,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_cr_in = 3'h0; endcase @@ -294,9 +294,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_cr_out = 3'h0; endcase @@ -304,9 +304,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_ldst_len = 4'h0; endcase @@ -314,9 +314,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_rc_sel = 2'h0; endcase @@ -324,9 +324,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: ALU_dec19_cry_in = 2'h0; endcase @@ -347,7 +347,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_cr_in; reg [2:0] ALU_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -357,17 +357,17 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_cr_out; reg [2:0] ALU_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_cry_in; reg [1:0] ALU_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_cry_out; reg ALU_dec31_cry_out; (* enum_base_type = "CRInSel" *) @@ -379,7 +379,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -388,15 +388,15 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -413,7 +413,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -421,7 +421,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -438,7 +438,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -515,13 +515,13 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -529,17 +529,17 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] ALU_dec31_dec_sub0_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -550,7 +550,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -559,15 +559,15 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -584,7 +584,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -592,7 +592,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -609,7 +609,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -686,13 +686,13 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -700,17 +700,17 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] ALU_dec31_dec_sub10_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -721,7 +721,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -730,15 +730,15 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -755,7 +755,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -763,7 +763,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -780,7 +780,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -857,13 +857,13 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -871,17 +871,17 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] ALU_dec31_dec_sub22_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -892,7 +892,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -901,15 +901,15 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -926,7 +926,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -934,7 +934,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -951,7 +951,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -1028,13 +1028,13 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -1042,17 +1042,17 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] ALU_dec31_dec_sub26_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -1063,7 +1063,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -1072,15 +1072,15 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -1097,7 +1097,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -1105,7 +1105,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -1122,7 +1122,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -1199,13 +1199,13 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -1213,17 +1213,17 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] ALU_dec31_dec_sub8_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -1240,7 +1240,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] ALU_dec31_function_unit; reg [13:0] ALU_dec31_function_unit; (* enum_base_type = "In1Sel" *) @@ -1249,7 +1249,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_in1_sel; reg [2:0] ALU_dec31_in1_sel; (* enum_base_type = "In2Sel" *) @@ -1267,7 +1267,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_in2_sel; reg [3:0] ALU_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -1345,16 +1345,16 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_internal_op; reg [6:0] ALU_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_inv_a; reg ALU_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_inv_out; reg ALU_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_is_32b; reg ALU_dec31_is_32b; (* enum_base_type = "LdstLen" *) @@ -1363,24 +1363,24 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_ldst_len; reg [3:0] ALU_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_rc_sel; reg [1:0] ALU_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_sgn; reg ALU_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:349" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; ALU_dec31_dec_sub0 ALU_dec31_dec_sub0 ( .ALU_dec31_dec_sub0_cr_in(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in), @@ -1470,21 +1470,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_in2_sel = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_in2_sel = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_in2_sel = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_in2_sel = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_in2_sel = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel; endcase @@ -1492,21 +1492,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_cr_in = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_cr_in = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_cr_in = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_cr_in = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_cr_in = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in; endcase @@ -1514,21 +1514,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_cr_out = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_cr_out = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_cr_out = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_cr_out = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_cr_out = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out; endcase @@ -1536,21 +1536,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_ldst_len = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_ldst_len = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_ldst_len = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_ldst_len = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_ldst_len = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len; endcase @@ -1558,21 +1558,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_rc_sel = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_rc_sel = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_rc_sel = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_rc_sel = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_rc_sel = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel; endcase @@ -1580,21 +1580,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_cry_in = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_cry_in = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_cry_in = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_cry_in = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_cry_in = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in; endcase @@ -1602,21 +1602,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_inv_a = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_inv_a = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_inv_a = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_inv_a = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_inv_a = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a; endcase @@ -1624,21 +1624,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_inv_out = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_inv_out = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_inv_out = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_inv_out = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_inv_out = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out; endcase @@ -1646,21 +1646,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_cry_out = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_cry_out = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_cry_out = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_cry_out = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_cry_out = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out; endcase @@ -1668,21 +1668,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_is_32b = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_is_32b = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_is_32b = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_is_32b = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_is_32b = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b; endcase @@ -1690,21 +1690,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_sgn = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_sgn = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_sgn = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_sgn = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_sgn = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn; endcase @@ -1712,21 +1712,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_function_unit = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_function_unit = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_function_unit = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_function_unit = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_function_unit = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit; endcase @@ -1734,21 +1734,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_internal_op = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_internal_op = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_internal_op = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_internal_op = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_internal_op = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op; endcase @@ -1756,21 +1756,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: ALU_dec31_in1_sel = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_in1_sel = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: ALU_dec31_in1_sel = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_in1_sel = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_in1_sel = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel; endcase @@ -1797,7 +1797,7 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub0_cr_in; reg [2:0] ALU_dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) @@ -1807,17 +1807,17 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub0_cr_out; reg [2:0] ALU_dec31_dec_sub0_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub0_cry_in; reg [1:0] ALU_dec31_dec_sub0_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub0_cry_out; reg ALU_dec31_dec_sub0_cry_out; (* enum_base_type = "Function" *) @@ -1835,7 +1835,7 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] ALU_dec31_dec_sub0_function_unit; reg [13:0] ALU_dec31_dec_sub0_function_unit; (* enum_base_type = "In1Sel" *) @@ -1844,7 +1844,7 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub0_in1_sel; reg [2:0] ALU_dec31_dec_sub0_in1_sel; (* enum_base_type = "In2Sel" *) @@ -1862,7 +1862,7 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub0_in2_sel; reg [3:0] ALU_dec31_dec_sub0_in2_sel; (* enum_base_type = "MicrOp" *) @@ -1940,16 +1940,16 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_dec_sub0_internal_op; reg [6:0] ALU_dec31_dec_sub0_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub0_inv_a; reg ALU_dec31_dec_sub0_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub0_inv_out; reg ALU_dec31_dec_sub0_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub0_is_32b; reg ALU_dec31_dec_sub0_is_32b; (* enum_base_type = "LdstLen" *) @@ -1958,35 +1958,35 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub0_ldst_len; reg [3:0] ALU_dec31_dec_sub0_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub0_rc_sel; reg [1:0] ALU_dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub0_sgn; reg ALU_dec31_dec_sub0_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_function_unit = 14'h0002; endcase @@ -1994,15 +1994,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_inv_a = 1'h1; endcase @@ -2010,15 +2010,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_inv_out = 1'h0; endcase @@ -2026,15 +2026,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_cry_out = 1'h0; endcase @@ -2042,15 +2042,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_is_32b = 1'h0; endcase @@ -2058,15 +2058,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_sgn = 1'h0; endcase @@ -2074,15 +2074,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_internal_op = 7'h0c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_internal_op = 7'h0a; endcase @@ -2090,15 +2090,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_in1_sel = 3'h1; endcase @@ -2106,15 +2106,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_in2_sel = 4'h1; endcase @@ -2122,15 +2122,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_cr_in = 3'h0; endcase @@ -2138,15 +2138,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_cr_out = 3'h2; endcase @@ -2154,15 +2154,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_ldst_len = 4'h0; endcase @@ -2170,15 +2170,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_rc_sel = 2'h0; endcase @@ -2186,15 +2186,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub0_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub0_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub0_cry_in = 2'h1; endcase @@ -2215,7 +2215,7 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub10_cr_in; reg [2:0] ALU_dec31_dec_sub10_cr_in; (* enum_base_type = "CROutSel" *) @@ -2225,17 +2225,17 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub10_cr_out; reg [2:0] ALU_dec31_dec_sub10_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub10_cry_in; reg [1:0] ALU_dec31_dec_sub10_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub10_cry_out; reg ALU_dec31_dec_sub10_cry_out; (* enum_base_type = "Function" *) @@ -2253,7 +2253,7 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] ALU_dec31_dec_sub10_function_unit; reg [13:0] ALU_dec31_dec_sub10_function_unit; (* enum_base_type = "In1Sel" *) @@ -2262,7 +2262,7 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub10_in1_sel; reg [2:0] ALU_dec31_dec_sub10_in1_sel; (* enum_base_type = "In2Sel" *) @@ -2280,7 +2280,7 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub10_in2_sel; reg [3:0] ALU_dec31_dec_sub10_in2_sel; (* enum_base_type = "MicrOp" *) @@ -2358,16 +2358,16 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_dec_sub10_internal_op; reg [6:0] ALU_dec31_dec_sub10_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub10_inv_a; reg ALU_dec31_dec_sub10_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub10_inv_out; reg ALU_dec31_dec_sub10_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub10_is_32b; reg ALU_dec31_dec_sub10_is_32b; (* enum_base_type = "LdstLen" *) @@ -2376,56 +2376,56 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub10_ldst_len; reg [3:0] ALU_dec31_dec_sub10_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub10_rc_sel; reg [1:0] ALU_dec31_dec_sub10_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub10_sgn; reg ALU_dec31_dec_sub10_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_function_unit = 14'h0002; endcase @@ -2433,36 +2433,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_inv_a = 1'h0; endcase @@ -2470,36 +2470,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_inv_out = 1'h0; endcase @@ -2507,36 +2507,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_cry_out = 1'h1; endcase @@ -2544,36 +2544,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_is_32b = 1'h0; endcase @@ -2581,36 +2581,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_sgn = 1'h0; endcase @@ -2618,36 +2618,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_internal_op = 7'h02; endcase @@ -2655,36 +2655,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_in1_sel = 3'h1; endcase @@ -2692,36 +2692,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_in2_sel = 4'h0; endcase @@ -2729,36 +2729,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_cr_in = 3'h0; endcase @@ -2766,36 +2766,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_cr_out = 3'h1; endcase @@ -2803,36 +2803,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_ldst_len = 4'h0; endcase @@ -2840,36 +2840,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_rc_sel = 2'h2; endcase @@ -2877,36 +2877,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: ALU_dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub10_cry_in = 2'h2; endcase @@ -2927,7 +2927,7 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub22_cr_in; reg [2:0] ALU_dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) @@ -2937,17 +2937,17 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub22_cr_out; reg [2:0] ALU_dec31_dec_sub22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub22_cry_in; reg [1:0] ALU_dec31_dec_sub22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub22_cry_out; reg ALU_dec31_dec_sub22_cry_out; (* enum_base_type = "Function" *) @@ -2965,7 +2965,7 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] ALU_dec31_dec_sub22_function_unit; reg [13:0] ALU_dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) @@ -2974,7 +2974,7 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub22_in1_sel; reg [2:0] ALU_dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) @@ -2992,7 +2992,7 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub22_in2_sel; reg [3:0] ALU_dec31_dec_sub22_in2_sel; (* enum_base_type = "MicrOp" *) @@ -3070,16 +3070,16 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_dec_sub22_internal_op; reg [6:0] ALU_dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub22_inv_a; reg ALU_dec31_dec_sub22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub22_inv_out; reg ALU_dec31_dec_sub22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub22_is_32b; reg ALU_dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) @@ -3088,47 +3088,47 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub22_ldst_len; reg [3:0] ALU_dec31_dec_sub22_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub22_rc_sel; reg [1:0] ALU_dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub22_sgn; reg ALU_dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_function_unit = 14'h0002; endcase @@ -3136,27 +3136,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_inv_a = 1'h0; endcase @@ -3164,27 +3164,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_inv_out = 1'h0; endcase @@ -3192,27 +3192,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_cry_out = 1'h0; endcase @@ -3220,27 +3220,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_is_32b = 1'h0; endcase @@ -3248,27 +3248,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_sgn = 1'h0; endcase @@ -3276,27 +3276,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_internal_op = 7'h21; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_internal_op = 7'h01; endcase @@ -3304,27 +3304,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_in1_sel = 3'h0; endcase @@ -3332,27 +3332,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_in2_sel = 4'h0; endcase @@ -3360,27 +3360,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_cr_in = 3'h0; endcase @@ -3388,27 +3388,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_cr_out = 3'h0; endcase @@ -3416,27 +3416,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_ldst_len = 4'h0; endcase @@ -3444,27 +3444,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_rc_sel = 2'h0; endcase @@ -3472,27 +3472,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: ALU_dec31_dec_sub22_cry_in = 2'h0; endcase @@ -3513,7 +3513,7 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub26_cr_in; reg [2:0] ALU_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) @@ -3523,17 +3523,17 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub26_cr_out; reg [2:0] ALU_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub26_cry_in; reg [1:0] ALU_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub26_cry_out; reg ALU_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) @@ -3551,7 +3551,7 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] ALU_dec31_dec_sub26_function_unit; reg [13:0] ALU_dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) @@ -3560,7 +3560,7 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub26_in1_sel; reg [2:0] ALU_dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) @@ -3578,7 +3578,7 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub26_in2_sel; reg [3:0] ALU_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) @@ -3656,16 +3656,16 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_dec_sub26_internal_op; reg [6:0] ALU_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub26_inv_a; reg ALU_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub26_inv_out; reg ALU_dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub26_is_32b; reg ALU_dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) @@ -3674,35 +3674,35 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub26_ldst_len; reg [3:0] ALU_dec31_dec_sub26_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub26_rc_sel; reg [1:0] ALU_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub26_sgn; reg ALU_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_function_unit = 14'h0002; endcase @@ -3710,15 +3710,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_inv_a = 1'h0; endcase @@ -3726,15 +3726,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_inv_out = 1'h0; endcase @@ -3742,15 +3742,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_cry_out = 1'h0; endcase @@ -3758,15 +3758,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_is_32b = 1'h0; endcase @@ -3774,15 +3774,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_sgn = 1'h0; endcase @@ -3790,15 +3790,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_internal_op = 7'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_internal_op = 7'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_internal_op = 7'h1f; endcase @@ -3806,15 +3806,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_in1_sel = 3'h4; endcase @@ -3822,15 +3822,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_in2_sel = 4'h0; endcase @@ -3838,15 +3838,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_cr_in = 3'h0; endcase @@ -3854,15 +3854,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_cr_out = 3'h1; endcase @@ -3870,15 +3870,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_ldst_len = 4'h4; endcase @@ -3886,15 +3886,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_rc_sel = 2'h2; endcase @@ -3902,15 +3902,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: ALU_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: ALU_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: ALU_dec31_dec_sub26_cry_in = 2'h0; endcase @@ -3931,7 +3931,7 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub8_cr_in; reg [2:0] ALU_dec31_dec_sub8_cr_in; (* enum_base_type = "CROutSel" *) @@ -3941,17 +3941,17 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub8_cr_out; reg [2:0] ALU_dec31_dec_sub8_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub8_cry_in; reg [1:0] ALU_dec31_dec_sub8_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub8_cry_out; reg ALU_dec31_dec_sub8_cry_out; (* enum_base_type = "Function" *) @@ -3969,7 +3969,7 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] ALU_dec31_dec_sub8_function_unit; reg [13:0] ALU_dec31_dec_sub8_function_unit; (* enum_base_type = "In1Sel" *) @@ -3978,7 +3978,7 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub8_in1_sel; reg [2:0] ALU_dec31_dec_sub8_in1_sel; (* enum_base_type = "In2Sel" *) @@ -3996,7 +3996,7 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub8_in2_sel; reg [3:0] ALU_dec31_dec_sub8_in2_sel; (* enum_base_type = "MicrOp" *) @@ -4074,16 +4074,16 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_dec_sub8_internal_op; reg [6:0] ALU_dec31_dec_sub8_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub8_inv_a; reg ALU_dec31_dec_sub8_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub8_inv_out; reg ALU_dec31_dec_sub8_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub8_is_32b; reg ALU_dec31_dec_sub8_is_32b; (* enum_base_type = "LdstLen" *) @@ -4092,62 +4092,62 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub8_ldst_len; reg [3:0] ALU_dec31_dec_sub8_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub8_rc_sel; reg [1:0] ALU_dec31_dec_sub8_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub8_sgn; reg ALU_dec31_dec_sub8_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_function_unit = 14'h0002; endcase @@ -4155,42 +4155,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_inv_a = 1'h1; endcase @@ -4198,42 +4198,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_inv_out = 1'h0; endcase @@ -4241,42 +4241,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_cry_out = 1'h1; endcase @@ -4284,42 +4284,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_is_32b = 1'h0; endcase @@ -4327,42 +4327,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_sgn = 1'h0; endcase @@ -4370,42 +4370,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_internal_op = 7'h02; endcase @@ -4413,42 +4413,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_in1_sel = 3'h1; endcase @@ -4456,42 +4456,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_in2_sel = 4'h0; endcase @@ -4499,42 +4499,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_cr_in = 3'h0; endcase @@ -4542,42 +4542,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_cr_out = 3'h1; endcase @@ -4585,42 +4585,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_ldst_len = 4'h0; endcase @@ -4628,42 +4628,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_rc_sel = 2'h2; endcase @@ -4671,42 +4671,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: ALU_dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: ALU_dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: ALU_dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: ALU_dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: ALU_dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: ALU_dec31_dec_sub8_cry_in = 2'h2; endcase @@ -4727,7 +4727,7 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] BRANCH_dec19_cr_in; reg [2:0] BRANCH_dec19_cr_in; (* enum_base_type = "CROutSel" *) @@ -4737,7 +4737,7 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] BRANCH_dec19_cr_out; reg [2:0] BRANCH_dec19_cr_out; (* enum_base_type = "Function" *) @@ -4755,7 +4755,7 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] BRANCH_dec19_function_unit; reg [13:0] BRANCH_dec19_function_unit; (* enum_base_type = "In2Sel" *) @@ -4773,7 +4773,7 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] BRANCH_dec19_in2_sel; reg [3:0] BRANCH_dec19_in2_sel; (* enum_base_type = "MicrOp" *) @@ -4851,38 +4851,38 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] BRANCH_dec19_internal_op; reg [6:0] BRANCH_dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output BRANCH_dec19_is_32b; reg BRANCH_dec19_is_32b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output BRANCH_dec19_lk; reg BRANCH_dec19_lk; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] BRANCH_dec19_rc_sel; reg [1:0] BRANCH_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; always @* begin if (\initial ) begin end BRANCH_dec19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: BRANCH_dec19_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: BRANCH_dec19_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: BRANCH_dec19_function_unit = 14'h0020; endcase @@ -4890,15 +4890,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: BRANCH_dec19_internal_op = 7'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: BRANCH_dec19_internal_op = 7'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: BRANCH_dec19_internal_op = 7'h08; endcase @@ -4906,15 +4906,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: BRANCH_dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: BRANCH_dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: BRANCH_dec19_in2_sel = 4'hc; endcase @@ -4922,15 +4922,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: BRANCH_dec19_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: BRANCH_dec19_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: BRANCH_dec19_cr_in = 3'h2; endcase @@ -4938,15 +4938,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: BRANCH_dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: BRANCH_dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: BRANCH_dec19_cr_out = 3'h0; endcase @@ -4954,15 +4954,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: BRANCH_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: BRANCH_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: BRANCH_dec19_rc_sel = 2'h0; endcase @@ -4970,15 +4970,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: BRANCH_dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: BRANCH_dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: BRANCH_dec19_is_32b = 1'h0; endcase @@ -4986,15 +4986,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: BRANCH_dec19_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: BRANCH_dec19_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: BRANCH_dec19_lk = 1'h1; endcase @@ -5015,7 +5015,7 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec19_cr_in; reg [2:0] CR_dec19_cr_in; (* enum_base_type = "CROutSel" *) @@ -5025,7 +5025,7 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec19_cr_out; reg [2:0] CR_dec19_cr_out; (* enum_base_type = "Function" *) @@ -5043,7 +5043,7 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] CR_dec19_function_unit; reg [13:0] CR_dec19_function_unit; (* enum_base_type = "MicrOp" *) @@ -5121,50 +5121,50 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec19_internal_op; reg [6:0] CR_dec19_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec19_rc_sel; reg [1:0] CR_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; always @* begin if (\initial ) begin end CR_dec19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: CR_dec19_function_unit = 14'h0040; endcase @@ -5172,33 +5172,33 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR always @* begin if (\initial ) begin end CR_dec19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: CR_dec19_internal_op = 7'h2a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: CR_dec19_internal_op = 7'h45; endcase @@ -5206,33 +5206,33 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR always @* begin if (\initial ) begin end CR_dec19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: CR_dec19_cr_in = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: CR_dec19_cr_in = 3'h4; endcase @@ -5240,33 +5240,33 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR always @* begin if (\initial ) begin end CR_dec19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: CR_dec19_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: CR_dec19_cr_out = 3'h3; endcase @@ -5274,33 +5274,33 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR always @* begin if (\initial ) begin end CR_dec19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: CR_dec19_rc_sel = 2'h0; endcase @@ -5321,7 +5321,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_cr_in; reg [2:0] CR_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -5331,7 +5331,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_cr_out; reg [2:0] CR_dec31_cr_out; (* enum_base_type = "CRInSel" *) @@ -5343,7 +5343,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -5352,7 +5352,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -5369,7 +5369,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -5446,15 +5446,15 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] CR_dec31_dec_sub0_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -5465,7 +5465,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -5474,7 +5474,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -5491,7 +5491,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -5568,15 +5568,15 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] CR_dec31_dec_sub15_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -5587,7 +5587,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -5596,7 +5596,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -5613,7 +5613,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -5690,15 +5690,15 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] CR_dec31_dec_sub16_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -5709,7 +5709,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -5718,7 +5718,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -5735,7 +5735,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -5812,15 +5812,15 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] CR_dec31_dec_sub19_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -5837,7 +5837,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] CR_dec31_function_unit; reg [13:0] CR_dec31_function_unit; (* enum_base_type = "MicrOp" *) @@ -5915,21 +5915,21 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec31_internal_op; reg [6:0] CR_dec31_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec31_rc_sel; reg [1:0] CR_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:349" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; CR_dec31_dec_sub0 CR_dec31_dec_sub0 ( .CR_dec31_dec_sub0_cr_in(CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in), @@ -5966,18 +5966,18 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR always @* begin if (\initial ) begin end CR_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_rc_sel = CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: CR_dec31_rc_sel = CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: CR_dec31_rc_sel = CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: CR_dec31_rc_sel = CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel; endcase @@ -5985,18 +5985,18 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR always @* begin if (\initial ) begin end CR_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_function_unit = CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: CR_dec31_function_unit = CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: CR_dec31_function_unit = CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: CR_dec31_function_unit = CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit; endcase @@ -6004,18 +6004,18 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR always @* begin if (\initial ) begin end CR_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_internal_op = CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: CR_dec31_internal_op = CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: CR_dec31_internal_op = CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: CR_dec31_internal_op = CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op; endcase @@ -6023,18 +6023,18 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR always @* begin if (\initial ) begin end CR_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_cr_in = CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: CR_dec31_cr_in = CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: CR_dec31_cr_in = CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: CR_dec31_cr_in = CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in; endcase @@ -6042,18 +6042,18 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR always @* begin if (\initial ) begin end CR_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_cr_out = CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: CR_dec31_cr_out = CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: CR_dec31_cr_out = CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: CR_dec31_cr_out = CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out; endcase @@ -6079,7 +6079,7 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub0_cr_in; reg [2:0] CR_dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) @@ -6089,7 +6089,7 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub0_cr_out; reg [2:0] CR_dec31_dec_sub0_cr_out; (* enum_base_type = "Function" *) @@ -6107,7 +6107,7 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] CR_dec31_dec_sub0_function_unit; reg [13:0] CR_dec31_dec_sub0_function_unit; (* enum_base_type = "MicrOp" *) @@ -6185,26 +6185,26 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec31_dec_sub0_internal_op; reg [6:0] CR_dec31_dec_sub0_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec31_dec_sub0_rc_sel; reg [1:0] CR_dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end CR_dec31_dec_sub0_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub0_function_unit = 14'h0040; endcase @@ -6212,9 +6212,9 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte always @* begin if (\initial ) begin end CR_dec31_dec_sub0_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub0_internal_op = 7'h3b; endcase @@ -6222,9 +6222,9 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte always @* begin if (\initial ) begin end CR_dec31_dec_sub0_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub0_cr_in = 3'h3; endcase @@ -6232,9 +6232,9 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte always @* begin if (\initial ) begin end CR_dec31_dec_sub0_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub0_cr_out = 3'h0; endcase @@ -6242,9 +6242,9 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte always @* begin if (\initial ) begin end CR_dec31_dec_sub0_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub0_rc_sel = 2'h0; endcase @@ -6265,7 +6265,7 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub15_cr_in; reg [2:0] CR_dec31_dec_sub15_cr_in; (* enum_base_type = "CROutSel" *) @@ -6275,7 +6275,7 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub15_cr_out; reg [2:0] CR_dec31_dec_sub15_cr_out; (* enum_base_type = "Function" *) @@ -6293,7 +6293,7 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] CR_dec31_dec_sub15_function_unit; reg [13:0] CR_dec31_dec_sub15_function_unit; (* enum_base_type = "MicrOp" *) @@ -6371,119 +6371,119 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec31_dec_sub15_internal_op; reg [6:0] CR_dec31_dec_sub15_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec31_dec_sub15_rc_sel; reg [1:0] CR_dec31_dec_sub15_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: CR_dec31_dec_sub15_function_unit = 14'h0040; endcase @@ -6491,102 +6491,102 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: CR_dec31_dec_sub15_internal_op = 7'h23; endcase @@ -6594,102 +6594,102 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: CR_dec31_dec_sub15_cr_in = 3'h5; endcase @@ -6697,102 +6697,102 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: CR_dec31_dec_sub15_cr_out = 3'h0; endcase @@ -6800,102 +6800,102 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: CR_dec31_dec_sub15_rc_sel = 2'h0; endcase @@ -6916,7 +6916,7 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub16_cr_in; reg [2:0] CR_dec31_dec_sub16_cr_in; (* enum_base_type = "CROutSel" *) @@ -6926,7 +6926,7 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub16_cr_out; reg [2:0] CR_dec31_dec_sub16_cr_out; (* enum_base_type = "Function" *) @@ -6944,7 +6944,7 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] CR_dec31_dec_sub16_function_unit; reg [13:0] CR_dec31_dec_sub16_function_unit; (* enum_base_type = "MicrOp" *) @@ -7022,26 +7022,26 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec31_dec_sub16_internal_op; reg [6:0] CR_dec31_dec_sub16_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec31_dec_sub16_rc_sel; reg [1:0] CR_dec31_dec_sub16_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end CR_dec31_dec_sub16_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub16_function_unit = 14'h0040; endcase @@ -7049,9 +7049,9 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i always @* begin if (\initial ) begin end CR_dec31_dec_sub16_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub16_internal_op = 7'h30; endcase @@ -7059,9 +7059,9 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i always @* begin if (\initial ) begin end CR_dec31_dec_sub16_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub16_cr_in = 3'h6; endcase @@ -7069,9 +7069,9 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i always @* begin if (\initial ) begin end CR_dec31_dec_sub16_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub16_cr_out = 3'h4; endcase @@ -7079,9 +7079,9 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i always @* begin if (\initial ) begin end CR_dec31_dec_sub16_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: CR_dec31_dec_sub16_rc_sel = 2'h0; endcase @@ -7102,7 +7102,7 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub19_cr_in; reg [2:0] CR_dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) @@ -7112,7 +7112,7 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub19_cr_out; reg [2:0] CR_dec31_dec_sub19_cr_out; (* enum_base_type = "Function" *) @@ -7130,7 +7130,7 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] CR_dec31_dec_sub19_function_unit; reg [13:0] CR_dec31_dec_sub19_function_unit; (* enum_base_type = "MicrOp" *) @@ -7208,26 +7208,26 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec31_dec_sub19_internal_op; reg [6:0] CR_dec31_dec_sub19_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec31_dec_sub19_rc_sel; reg [1:0] CR_dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end CR_dec31_dec_sub19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_dec_sub19_function_unit = 14'h0040; endcase @@ -7235,9 +7235,9 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i always @* begin if (\initial ) begin end CR_dec31_dec_sub19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_dec_sub19_internal_op = 7'h2d; endcase @@ -7245,9 +7245,9 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i always @* begin if (\initial ) begin end CR_dec31_dec_sub19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_dec_sub19_cr_in = 3'h6; endcase @@ -7255,9 +7255,9 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i always @* begin if (\initial ) begin end CR_dec31_dec_sub19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_dec_sub19_cr_out = 3'h0; endcase @@ -7265,9 +7265,9 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i always @* begin if (\initial ) begin end CR_dec31_dec_sub19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: CR_dec31_dec_sub19_rc_sel = 2'h0; endcase @@ -7288,7 +7288,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_cr_in; reg [2:0] DIV_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -7298,17 +7298,17 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_cr_out; reg [2:0] DIV_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_cry_in; reg [1:0] DIV_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_cry_out; reg DIV_dec31_cry_out; (* enum_base_type = "CRInSel" *) @@ -7320,7 +7320,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -7329,15 +7329,15 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -7354,7 +7354,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -7362,7 +7362,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -7379,7 +7379,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -7456,13 +7456,13 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -7470,17 +7470,17 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] DIV_dec31_dec_sub11_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -7491,7 +7491,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -7500,15 +7500,15 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -7525,7 +7525,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -7533,7 +7533,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -7550,7 +7550,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -7627,13 +7627,13 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -7641,17 +7641,17 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] DIV_dec31_dec_sub9_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -7668,7 +7668,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] DIV_dec31_function_unit; reg [13:0] DIV_dec31_function_unit; (* enum_base_type = "In1Sel" *) @@ -7677,7 +7677,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_in1_sel; reg [2:0] DIV_dec31_in1_sel; (* enum_base_type = "In2Sel" *) @@ -7695,7 +7695,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_in2_sel; reg [3:0] DIV_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -7773,16 +7773,16 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] DIV_dec31_internal_op; reg [6:0] DIV_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_inv_a; reg DIV_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_inv_out; reg DIV_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_is_32b; reg DIV_dec31_is_32b; (* enum_base_type = "LdstLen" *) @@ -7791,24 +7791,24 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_ldst_len; reg [3:0] DIV_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_rc_sel; reg [1:0] DIV_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_sgn; reg DIV_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:349" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; DIV_dec31_dec_sub11 DIV_dec31_dec_sub11 ( .DIV_dec31_dec_sub11_cr_in(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in), @@ -7847,12 +7847,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_ldst_len = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_ldst_len = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len; endcase @@ -7860,12 +7860,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_rc_sel = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_rc_sel = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel; endcase @@ -7873,12 +7873,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_cry_in = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_cry_in = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in; endcase @@ -7886,12 +7886,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_inv_a = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_inv_a = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a; endcase @@ -7899,12 +7899,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_inv_out = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_inv_out = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out; endcase @@ -7912,12 +7912,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_cry_out = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_cry_out = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out; endcase @@ -7925,12 +7925,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_is_32b = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_is_32b = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b; endcase @@ -7938,12 +7938,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_sgn = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_sgn = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn; endcase @@ -7951,12 +7951,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_function_unit = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_function_unit = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit; endcase @@ -7964,12 +7964,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_internal_op = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_internal_op = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op; endcase @@ -7977,12 +7977,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_in1_sel = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_in1_sel = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel; endcase @@ -7990,12 +7990,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_in2_sel = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_in2_sel = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel; endcase @@ -8003,12 +8003,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_cr_in = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_cr_in = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in; endcase @@ -8016,12 +8016,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: DIV_dec31_cr_out = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: DIV_dec31_cr_out = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out; endcase @@ -8045,7 +8045,7 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub11_cr_in; reg [2:0] DIV_dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) @@ -8055,17 +8055,17 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub11_cr_out; reg [2:0] DIV_dec31_dec_sub11_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_dec_sub11_cry_in; reg [1:0] DIV_dec31_dec_sub11_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub11_cry_out; reg DIV_dec31_dec_sub11_cry_out; (* enum_base_type = "Function" *) @@ -8083,7 +8083,7 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] DIV_dec31_dec_sub11_function_unit; reg [13:0] DIV_dec31_dec_sub11_function_unit; (* enum_base_type = "In1Sel" *) @@ -8092,7 +8092,7 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub11_in1_sel; reg [2:0] DIV_dec31_dec_sub11_in1_sel; (* enum_base_type = "In2Sel" *) @@ -8110,7 +8110,7 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_dec_sub11_in2_sel; reg [3:0] DIV_dec31_dec_sub11_in2_sel; (* enum_base_type = "MicrOp" *) @@ -8188,16 +8188,16 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] DIV_dec31_dec_sub11_internal_op; reg [6:0] DIV_dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub11_inv_a; reg DIV_dec31_dec_sub11_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub11_inv_out; reg DIV_dec31_dec_sub11_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub11_is_32b; reg DIV_dec31_dec_sub11_is_32b; (* enum_base_type = "LdstLen" *) @@ -8206,56 +8206,56 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_dec_sub11_ldst_len; reg [3:0] DIV_dec31_dec_sub11_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_dec_sub11_rc_sel; reg [1:0] DIV_dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub11_sgn; reg DIV_dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_function_unit = 14'h0200; endcase @@ -8263,36 +8263,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_inv_a = 1'h0; endcase @@ -8300,36 +8300,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_inv_out = 1'h0; endcase @@ -8337,36 +8337,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_cry_out = 1'h0; endcase @@ -8374,36 +8374,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_is_32b = 1'h1; endcase @@ -8411,36 +8411,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_sgn = 1'h1; endcase @@ -8448,36 +8448,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_internal_op = 7'h2f; endcase @@ -8485,36 +8485,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_in1_sel = 3'h1; endcase @@ -8522,36 +8522,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_in2_sel = 4'h1; endcase @@ -8559,36 +8559,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_cr_in = 3'h0; endcase @@ -8596,36 +8596,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_cr_out = 3'h0; endcase @@ -8633,36 +8633,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_ldst_len = 4'h0; endcase @@ -8670,36 +8670,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_rc_sel = 2'h0; endcase @@ -8707,36 +8707,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub11_cry_in = 2'h0; endcase @@ -8757,7 +8757,7 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub9_cr_in; reg [2:0] DIV_dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) @@ -8767,17 +8767,17 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub9_cr_out; reg [2:0] DIV_dec31_dec_sub9_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_dec_sub9_cry_in; reg [1:0] DIV_dec31_dec_sub9_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub9_cry_out; reg DIV_dec31_dec_sub9_cry_out; (* enum_base_type = "Function" *) @@ -8795,7 +8795,7 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] DIV_dec31_dec_sub9_function_unit; reg [13:0] DIV_dec31_dec_sub9_function_unit; (* enum_base_type = "In1Sel" *) @@ -8804,7 +8804,7 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub9_in1_sel; reg [2:0] DIV_dec31_dec_sub9_in1_sel; (* enum_base_type = "In2Sel" *) @@ -8822,7 +8822,7 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_dec_sub9_in2_sel; reg [3:0] DIV_dec31_dec_sub9_in2_sel; (* enum_base_type = "MicrOp" *) @@ -8900,16 +8900,16 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] DIV_dec31_dec_sub9_internal_op; reg [6:0] DIV_dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub9_inv_a; reg DIV_dec31_dec_sub9_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub9_inv_out; reg DIV_dec31_dec_sub9_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub9_is_32b; reg DIV_dec31_dec_sub9_is_32b; (* enum_base_type = "LdstLen" *) @@ -8918,56 +8918,56 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_dec_sub9_ldst_len; reg [3:0] DIV_dec31_dec_sub9_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_dec_sub9_rc_sel; reg [1:0] DIV_dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub9_sgn; reg DIV_dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_function_unit = 14'h0200; endcase @@ -8975,36 +8975,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_inv_a = 1'h0; endcase @@ -9012,36 +9012,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_inv_out = 1'h0; endcase @@ -9049,36 +9049,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_cry_out = 1'h0; endcase @@ -9086,36 +9086,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_is_32b = 1'h0; endcase @@ -9123,36 +9123,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_sgn = 1'h1; endcase @@ -9160,36 +9160,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_internal_op = 7'h2f; endcase @@ -9197,36 +9197,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_in1_sel = 3'h1; endcase @@ -9234,36 +9234,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_in2_sel = 4'h1; endcase @@ -9271,36 +9271,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_cr_in = 3'h0; endcase @@ -9308,36 +9308,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_cr_out = 3'h0; endcase @@ -9345,36 +9345,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_ldst_len = 4'h0; endcase @@ -9382,36 +9382,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_rc_sel = 2'h0; endcase @@ -9419,36 +9419,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: DIV_dec31_dec_sub9_cry_in = 2'h0; endcase @@ -9460,7 +9460,7 @@ endmodule (* generator = "nMigen" *) module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_in1_sel, LDST_dec31_in2_sel, LDST_dec31_cr_in, LDST_dec31_cr_out, LDST_dec31_ldst_len, LDST_dec31_upd, LDST_dec31_rc_sel, LDST_dec31_br, LDST_dec31_sgn_ext, LDST_dec31_is_32b, LDST_dec31_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_br; reg LDST_dec31_br; (* enum_base_type = "CRInSel" *) @@ -9472,7 +9472,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_cr_in; reg [2:0] LDST_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -9482,10 +9482,10 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_cr_out; reg [2:0] LDST_dec31_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -9496,7 +9496,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -9505,7 +9505,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -9522,7 +9522,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -9530,7 +9530,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -9547,7 +9547,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -9624,9 +9624,9 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -9634,28 +9634,28 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] LDST_dec31_dec_sub20_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -9666,7 +9666,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -9675,7 +9675,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -9692,7 +9692,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -9700,7 +9700,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -9717,7 +9717,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -9794,9 +9794,9 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -9804,28 +9804,28 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] LDST_dec31_dec_sub21_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -9836,7 +9836,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -9845,7 +9845,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -9862,7 +9862,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -9870,7 +9870,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -9887,7 +9887,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -9964,9 +9964,9 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -9974,28 +9974,28 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] LDST_dec31_dec_sub22_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -10006,7 +10006,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -10015,7 +10015,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -10032,7 +10032,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -10040,7 +10040,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -10057,7 +10057,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -10134,9 +10134,9 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -10144,26 +10144,26 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] LDST_dec31_dec_sub23_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -10180,7 +10180,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LDST_dec31_function_unit; reg [13:0] LDST_dec31_function_unit; (* enum_base_type = "In1Sel" *) @@ -10189,7 +10189,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_in1_sel; reg [2:0] LDST_dec31_in1_sel; (* enum_base_type = "In2Sel" *) @@ -10207,7 +10207,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_in2_sel; reg [3:0] LDST_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -10285,10 +10285,10 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec31_internal_op; reg [6:0] LDST_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_is_32b; reg LDST_dec31_is_32b; (* enum_base_type = "LdstLen" *) @@ -10297,20 +10297,20 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_ldst_len; reg [3:0] LDST_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_rc_sel; reg [1:0] LDST_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_sgn; reg LDST_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_sgn_ext; reg LDST_dec31_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -10318,14 +10318,14 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_upd; reg [1:0] LDST_dec31_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:349" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; LDST_dec31_dec_sub20 LDST_dec31_dec_sub20 ( .LDST_dec31_dec_sub20_br(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br), @@ -10394,18 +10394,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_cr_in = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_cr_in = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_cr_in = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_cr_in = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in; endcase @@ -10413,18 +10413,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_cr_out = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_cr_out = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_cr_out = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_cr_out = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out; endcase @@ -10432,18 +10432,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_ldst_len = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_ldst_len = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_ldst_len = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_ldst_len = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len; endcase @@ -10451,18 +10451,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_upd = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_upd = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_upd = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_upd = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd; endcase @@ -10470,18 +10470,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_rc_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_rc_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_rc_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_rc_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel; endcase @@ -10489,18 +10489,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_br = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_br = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_br = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_br = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br; endcase @@ -10508,18 +10508,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_sgn_ext = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_sgn_ext = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_sgn_ext = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_sgn_ext = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext; endcase @@ -10527,18 +10527,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_is_32b = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_is_32b = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_is_32b = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_is_32b = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b; endcase @@ -10546,18 +10546,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_sgn = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_sgn = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_sgn = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_sgn = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn; endcase @@ -10565,18 +10565,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_function_unit = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_function_unit = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_function_unit = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_function_unit = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit; endcase @@ -10584,18 +10584,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_internal_op = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_internal_op = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_internal_op = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_internal_op = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op; endcase @@ -10603,18 +10603,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_in1_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_in1_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_in1_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_in1_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel; endcase @@ -10622,18 +10622,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_in2_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_in2_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_in2_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: LDST_dec31_in2_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel; endcase @@ -10650,7 +10650,7 @@ endmodule (* generator = "nMigen" *) module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_sub20_internal_op, LDST_dec31_dec_sub20_in1_sel, LDST_dec31_dec_sub20_in2_sel, LDST_dec31_dec_sub20_cr_in, LDST_dec31_dec_sub20_cr_out, LDST_dec31_dec_sub20_ldst_len, LDST_dec31_dec_sub20_upd, LDST_dec31_dec_sub20_rc_sel, LDST_dec31_dec_sub20_br, LDST_dec31_dec_sub20_sgn_ext, LDST_dec31_dec_sub20_is_32b, LDST_dec31_dec_sub20_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub20_br; reg LDST_dec31_dec_sub20_br; (* enum_base_type = "CRInSel" *) @@ -10662,7 +10662,7 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub20_cr_in; reg [2:0] LDST_dec31_dec_sub20_cr_in; (* enum_base_type = "CROutSel" *) @@ -10672,7 +10672,7 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub20_cr_out; reg [2:0] LDST_dec31_dec_sub20_cr_out; (* enum_base_type = "Function" *) @@ -10690,7 +10690,7 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LDST_dec31_dec_sub20_function_unit; reg [13:0] LDST_dec31_dec_sub20_function_unit; (* enum_base_type = "In1Sel" *) @@ -10699,7 +10699,7 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub20_in1_sel; reg [2:0] LDST_dec31_dec_sub20_in1_sel; (* enum_base_type = "In2Sel" *) @@ -10717,7 +10717,7 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub20_in2_sel; reg [3:0] LDST_dec31_dec_sub20_in2_sel; (* enum_base_type = "MicrOp" *) @@ -10795,10 +10795,10 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec31_dec_sub20_internal_op; reg [6:0] LDST_dec31_dec_sub20_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub20_is_32b; reg LDST_dec31_dec_sub20_is_32b; (* enum_base_type = "LdstLen" *) @@ -10807,20 +10807,20 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub20_ldst_len; reg [3:0] LDST_dec31_dec_sub20_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub20_rc_sel; reg [1:0] LDST_dec31_dec_sub20_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub20_sgn; reg LDST_dec31_dec_sub20_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub20_sgn_ext; reg LDST_dec31_dec_sub20_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -10828,34 +10828,34 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub20_upd; reg [1:0] LDST_dec31_dec_sub20_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_function_unit = 14'h0004; endcase @@ -10863,24 +10863,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_br = 1'h1; endcase @@ -10888,24 +10888,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_sgn_ext = 1'h0; endcase @@ -10913,24 +10913,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_is_32b = 1'h0; endcase @@ -10938,24 +10938,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_sgn = 1'h0; endcase @@ -10963,24 +10963,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_internal_op = 7'h26; endcase @@ -10988,24 +10988,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_in1_sel = 3'h2; endcase @@ -11013,24 +11013,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_in2_sel = 4'h1; endcase @@ -11038,24 +11038,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_cr_in = 3'h0; endcase @@ -11063,24 +11063,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_cr_out = 3'h0; endcase @@ -11088,24 +11088,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_ldst_len = 4'h8; endcase @@ -11113,24 +11113,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_upd = 2'h0; endcase @@ -11138,24 +11138,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub20_rc_sel = 2'h0; endcase @@ -11167,7 +11167,7 @@ endmodule (* generator = "nMigen" *) module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_sub21_internal_op, LDST_dec31_dec_sub21_in1_sel, LDST_dec31_dec_sub21_in2_sel, LDST_dec31_dec_sub21_cr_in, LDST_dec31_dec_sub21_cr_out, LDST_dec31_dec_sub21_ldst_len, LDST_dec31_dec_sub21_upd, LDST_dec31_dec_sub21_rc_sel, LDST_dec31_dec_sub21_br, LDST_dec31_dec_sub21_sgn_ext, LDST_dec31_dec_sub21_is_32b, LDST_dec31_dec_sub21_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub21_br; reg LDST_dec31_dec_sub21_br; (* enum_base_type = "CRInSel" *) @@ -11179,7 +11179,7 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub21_cr_in; reg [2:0] LDST_dec31_dec_sub21_cr_in; (* enum_base_type = "CROutSel" *) @@ -11189,7 +11189,7 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub21_cr_out; reg [2:0] LDST_dec31_dec_sub21_cr_out; (* enum_base_type = "Function" *) @@ -11207,7 +11207,7 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LDST_dec31_dec_sub21_function_unit; reg [13:0] LDST_dec31_dec_sub21_function_unit; (* enum_base_type = "In1Sel" *) @@ -11216,7 +11216,7 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub21_in1_sel; reg [2:0] LDST_dec31_dec_sub21_in1_sel; (* enum_base_type = "In2Sel" *) @@ -11234,7 +11234,7 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub21_in2_sel; reg [3:0] LDST_dec31_dec_sub21_in2_sel; (* enum_base_type = "MicrOp" *) @@ -11312,10 +11312,10 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec31_dec_sub21_internal_op; reg [6:0] LDST_dec31_dec_sub21_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub21_is_32b; reg LDST_dec31_dec_sub21_is_32b; (* enum_base_type = "LdstLen" *) @@ -11324,20 +11324,20 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub21_ldst_len; reg [3:0] LDST_dec31_dec_sub21_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub21_rc_sel; reg [1:0] LDST_dec31_dec_sub21_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub21_sgn; reg LDST_dec31_dec_sub21_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub21_sgn_ext; reg LDST_dec31_dec_sub21_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -11345,58 +11345,58 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub21_upd; reg [1:0] LDST_dec31_dec_sub21_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_function_unit = 14'h0004; endcase @@ -11404,48 +11404,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_br = 1'h0; endcase @@ -11453,48 +11453,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_sgn_ext = 1'h0; endcase @@ -11502,48 +11502,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_is_32b = 1'h0; endcase @@ -11551,48 +11551,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_sgn = 1'h0; endcase @@ -11600,48 +11600,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_internal_op = 7'h26; endcase @@ -11649,48 +11649,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_in1_sel = 3'h2; endcase @@ -11698,48 +11698,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_in2_sel = 4'h1; endcase @@ -11747,48 +11747,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_cr_in = 3'h0; endcase @@ -11796,48 +11796,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_cr_out = 3'h0; endcase @@ -11845,48 +11845,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_ldst_len = 4'h4; endcase @@ -11894,48 +11894,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_upd = 2'h2; endcase @@ -11943,48 +11943,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub21_rc_sel = 2'h0; endcase @@ -11996,7 +11996,7 @@ endmodule (* generator = "nMigen" *) module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_sub22_internal_op, LDST_dec31_dec_sub22_in1_sel, LDST_dec31_dec_sub22_in2_sel, LDST_dec31_dec_sub22_cr_in, LDST_dec31_dec_sub22_cr_out, LDST_dec31_dec_sub22_ldst_len, LDST_dec31_dec_sub22_upd, LDST_dec31_dec_sub22_rc_sel, LDST_dec31_dec_sub22_br, LDST_dec31_dec_sub22_sgn_ext, LDST_dec31_dec_sub22_is_32b, LDST_dec31_dec_sub22_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub22_br; reg LDST_dec31_dec_sub22_br; (* enum_base_type = "CRInSel" *) @@ -12008,7 +12008,7 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub22_cr_in; reg [2:0] LDST_dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) @@ -12018,7 +12018,7 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub22_cr_out; reg [2:0] LDST_dec31_dec_sub22_cr_out; (* enum_base_type = "Function" *) @@ -12036,7 +12036,7 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LDST_dec31_dec_sub22_function_unit; reg [13:0] LDST_dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) @@ -12045,7 +12045,7 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub22_in1_sel; reg [2:0] LDST_dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) @@ -12063,7 +12063,7 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub22_in2_sel; reg [3:0] LDST_dec31_dec_sub22_in2_sel; (* enum_base_type = "MicrOp" *) @@ -12141,10 +12141,10 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec31_dec_sub22_internal_op; reg [6:0] LDST_dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub22_is_32b; reg LDST_dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) @@ -12153,20 +12153,20 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub22_ldst_len; reg [3:0] LDST_dec31_dec_sub22_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub22_rc_sel; reg [1:0] LDST_dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub22_sgn; reg LDST_dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub22_sgn_ext; reg LDST_dec31_dec_sub22_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -12174,40 +12174,40 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub22_upd; reg [1:0] LDST_dec31_dec_sub22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_function_unit = 14'h0004; endcase @@ -12215,30 +12215,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_br = 1'h0; endcase @@ -12246,30 +12246,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_sgn_ext = 1'h0; endcase @@ -12277,30 +12277,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_is_32b = 1'h0; endcase @@ -12308,30 +12308,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_sgn = 1'h0; endcase @@ -12339,30 +12339,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_internal_op = 7'h26; endcase @@ -12370,30 +12370,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_in1_sel = 3'h2; endcase @@ -12401,30 +12401,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_in2_sel = 4'h1; endcase @@ -12432,30 +12432,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_cr_in = 3'h0; endcase @@ -12463,30 +12463,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_cr_out = 3'h1; endcase @@ -12494,30 +12494,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_ldst_len = 4'h4; endcase @@ -12525,30 +12525,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_upd = 2'h0; endcase @@ -12556,30 +12556,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: LDST_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LDST_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: LDST_dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LDST_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: LDST_dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: LDST_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub22_rc_sel = 2'h1; endcase @@ -12591,7 +12591,7 @@ endmodule (* generator = "nMigen" *) module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_sub23_internal_op, LDST_dec31_dec_sub23_in1_sel, LDST_dec31_dec_sub23_in2_sel, LDST_dec31_dec_sub23_cr_in, LDST_dec31_dec_sub23_cr_out, LDST_dec31_dec_sub23_ldst_len, LDST_dec31_dec_sub23_upd, LDST_dec31_dec_sub23_rc_sel, LDST_dec31_dec_sub23_br, LDST_dec31_dec_sub23_sgn_ext, LDST_dec31_dec_sub23_is_32b, LDST_dec31_dec_sub23_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub23_br; reg LDST_dec31_dec_sub23_br; (* enum_base_type = "CRInSel" *) @@ -12603,7 +12603,7 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub23_cr_in; reg [2:0] LDST_dec31_dec_sub23_cr_in; (* enum_base_type = "CROutSel" *) @@ -12613,7 +12613,7 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub23_cr_out; reg [2:0] LDST_dec31_dec_sub23_cr_out; (* enum_base_type = "Function" *) @@ -12631,7 +12631,7 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LDST_dec31_dec_sub23_function_unit; reg [13:0] LDST_dec31_dec_sub23_function_unit; (* enum_base_type = "In1Sel" *) @@ -12640,7 +12640,7 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub23_in1_sel; reg [2:0] LDST_dec31_dec_sub23_in1_sel; (* enum_base_type = "In2Sel" *) @@ -12658,7 +12658,7 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub23_in2_sel; reg [3:0] LDST_dec31_dec_sub23_in2_sel; (* enum_base_type = "MicrOp" *) @@ -12736,10 +12736,10 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec31_dec_sub23_internal_op; reg [6:0] LDST_dec31_dec_sub23_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub23_is_32b; reg LDST_dec31_dec_sub23_is_32b; (* enum_base_type = "LdstLen" *) @@ -12748,20 +12748,20 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub23_ldst_len; reg [3:0] LDST_dec31_dec_sub23_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub23_rc_sel; reg [1:0] LDST_dec31_dec_sub23_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub23_sgn; reg LDST_dec31_dec_sub23_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub23_sgn_ext; reg LDST_dec31_dec_sub23_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -12769,58 +12769,58 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub23_upd; reg [1:0] LDST_dec31_dec_sub23_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_function_unit = 14'h0004; endcase @@ -12828,48 +12828,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_br = 1'h0; endcase @@ -12877,48 +12877,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_sgn_ext = 1'h0; endcase @@ -12926,48 +12926,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_is_32b = 1'h0; endcase @@ -12975,48 +12975,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_sgn = 1'h0; endcase @@ -13024,48 +13024,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_internal_op = 7'h26; endcase @@ -13073,48 +13073,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_in1_sel = 3'h2; endcase @@ -13122,48 +13122,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_in2_sel = 4'h1; endcase @@ -13171,48 +13171,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_cr_in = 3'h0; endcase @@ -13220,48 +13220,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_cr_out = 3'h0; endcase @@ -13269,48 +13269,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_ldst_len = 4'h4; endcase @@ -13318,48 +13318,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_upd = 2'h0; endcase @@ -13367,48 +13367,48 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LDST_dec31_dec_sub23_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LDST_dec31_dec_sub23_rc_sel = 2'h0; endcase @@ -13420,7 +13420,7 @@ endmodule (* generator = "nMigen" *) module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_in1_sel, LDST_dec58_in2_sel, LDST_dec58_cr_in, LDST_dec58_cr_out, LDST_dec58_ldst_len, LDST_dec58_upd, LDST_dec58_rc_sel, LDST_dec58_br, LDST_dec58_sgn_ext, LDST_dec58_is_32b, LDST_dec58_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec58_br; reg LDST_dec58_br; (* enum_base_type = "CRInSel" *) @@ -13432,7 +13432,7 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec58_cr_in; reg [2:0] LDST_dec58_cr_in; (* enum_base_type = "CROutSel" *) @@ -13442,7 +13442,7 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec58_cr_out; reg [2:0] LDST_dec58_cr_out; (* enum_base_type = "Function" *) @@ -13460,7 +13460,7 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LDST_dec58_function_unit; reg [13:0] LDST_dec58_function_unit; (* enum_base_type = "In1Sel" *) @@ -13469,7 +13469,7 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec58_in1_sel; reg [2:0] LDST_dec58_in1_sel; (* enum_base_type = "In2Sel" *) @@ -13487,7 +13487,7 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec58_in2_sel; reg [3:0] LDST_dec58_in2_sel; (* enum_base_type = "MicrOp" *) @@ -13565,10 +13565,10 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec58_internal_op; reg [6:0] LDST_dec58_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec58_is_32b; reg LDST_dec58_is_32b; (* enum_base_type = "LdstLen" *) @@ -13577,20 +13577,20 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec58_ldst_len; reg [3:0] LDST_dec58_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec58_rc_sel; reg [1:0] LDST_dec58_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec58_sgn; reg LDST_dec58_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec58_sgn_ext; reg LDST_dec58_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -13598,25 +13598,25 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec58_upd; reg [1:0] LDST_dec58_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [1:0] opcode_switch; always @* begin if (\initial ) begin end LDST_dec58_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_function_unit = 14'h0004; endcase @@ -13624,15 +13624,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_br = 1'h0; endcase @@ -13640,15 +13640,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_sgn_ext = 1'h1; endcase @@ -13656,15 +13656,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_is_32b = 1'h0; endcase @@ -13672,15 +13672,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_sgn = 1'h0; endcase @@ -13688,15 +13688,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_internal_op = 7'h25; endcase @@ -13704,15 +13704,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_in1_sel = 3'h2; endcase @@ -13720,15 +13720,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_in2_sel = 4'h8; endcase @@ -13736,15 +13736,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_cr_in = 3'h0; endcase @@ -13752,15 +13752,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_cr_out = 3'h0; endcase @@ -13768,15 +13768,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_ldst_len = 4'h4; endcase @@ -13784,15 +13784,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_upd = 2'h0; endcase @@ -13800,15 +13800,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec58_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec58_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: LDST_dec58_rc_sel = 2'h0; endcase @@ -13820,7 +13820,7 @@ endmodule (* generator = "nMigen" *) module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_in1_sel, LDST_dec62_in2_sel, LDST_dec62_cr_in, LDST_dec62_cr_out, LDST_dec62_ldst_len, LDST_dec62_upd, LDST_dec62_rc_sel, LDST_dec62_br, LDST_dec62_sgn_ext, LDST_dec62_is_32b, LDST_dec62_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec62_br; reg LDST_dec62_br; (* enum_base_type = "CRInSel" *) @@ -13832,7 +13832,7 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec62_cr_in; reg [2:0] LDST_dec62_cr_in; (* enum_base_type = "CROutSel" *) @@ -13842,7 +13842,7 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec62_cr_out; reg [2:0] LDST_dec62_cr_out; (* enum_base_type = "Function" *) @@ -13860,7 +13860,7 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LDST_dec62_function_unit; reg [13:0] LDST_dec62_function_unit; (* enum_base_type = "In1Sel" *) @@ -13869,7 +13869,7 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec62_in1_sel; reg [2:0] LDST_dec62_in1_sel; (* enum_base_type = "In2Sel" *) @@ -13887,7 +13887,7 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec62_in2_sel; reg [3:0] LDST_dec62_in2_sel; (* enum_base_type = "MicrOp" *) @@ -13965,10 +13965,10 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec62_internal_op; reg [6:0] LDST_dec62_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec62_is_32b; reg LDST_dec62_is_32b; (* enum_base_type = "LdstLen" *) @@ -13977,20 +13977,20 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec62_ldst_len; reg [3:0] LDST_dec62_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec62_rc_sel; reg [1:0] LDST_dec62_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec62_sgn; reg LDST_dec62_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec62_sgn_ext; reg LDST_dec62_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -13998,22 +13998,22 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec62_upd; reg [1:0] LDST_dec62_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [1:0] opcode_switch; always @* begin if (\initial ) begin end LDST_dec62_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_function_unit = 14'h0004; endcase @@ -14021,12 +14021,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_br = 1'h0; endcase @@ -14034,12 +14034,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_sgn_ext = 1'h0; endcase @@ -14047,12 +14047,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_is_32b = 1'h0; endcase @@ -14060,12 +14060,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_sgn = 1'h0; endcase @@ -14073,12 +14073,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_internal_op = 7'h26; endcase @@ -14086,12 +14086,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_in1_sel = 3'h2; endcase @@ -14099,12 +14099,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_in2_sel = 4'h8; endcase @@ -14112,12 +14112,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_cr_in = 3'h0; endcase @@ -14125,12 +14125,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_cr_out = 3'h0; endcase @@ -14138,12 +14138,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_ldst_len = 4'h8; endcase @@ -14151,12 +14151,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_upd = 2'h1; endcase @@ -14164,12 +14164,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: LDST_dec62_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: LDST_dec62_rc_sel = 2'h0; endcase @@ -14190,7 +14190,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_cr_in; reg [2:0] LOGICAL_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -14200,17 +14200,17 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_cr_out; reg [2:0] LOGICAL_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_cry_in; reg [1:0] LOGICAL_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_cry_out; reg LOGICAL_dec31_cry_out; (* enum_base_type = "CRInSel" *) @@ -14222,7 +14222,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -14231,15 +14231,15 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -14256,7 +14256,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -14264,7 +14264,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -14281,7 +14281,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -14358,13 +14358,13 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -14372,17 +14372,17 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] LOGICAL_dec31_dec_sub26_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -14393,7 +14393,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -14402,15 +14402,15 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -14427,7 +14427,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -14435,7 +14435,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -14452,7 +14452,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -14529,13 +14529,13 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -14543,17 +14543,17 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] LOGICAL_dec31_dec_sub28_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -14570,7 +14570,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LOGICAL_dec31_function_unit; reg [13:0] LOGICAL_dec31_function_unit; (* enum_base_type = "In1Sel" *) @@ -14579,7 +14579,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_in1_sel; reg [2:0] LOGICAL_dec31_in1_sel; (* enum_base_type = "In2Sel" *) @@ -14597,7 +14597,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_in2_sel; reg [3:0] LOGICAL_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -14675,16 +14675,16 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LOGICAL_dec31_internal_op; reg [6:0] LOGICAL_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_inv_a; reg LOGICAL_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_inv_out; reg LOGICAL_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_is_32b; reg LOGICAL_dec31_is_32b; (* enum_base_type = "LdstLen" *) @@ -14693,24 +14693,24 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_ldst_len; reg [3:0] LOGICAL_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_rc_sel; reg [1:0] LOGICAL_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_sgn; reg LOGICAL_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:349" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; LOGICAL_dec31_dec_sub26 LOGICAL_dec31_dec_sub26 ( .LOGICAL_dec31_dec_sub26_cr_in(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in), @@ -14749,12 +14749,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_ldst_len = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_ldst_len = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len; endcase @@ -14762,12 +14762,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_rc_sel = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_rc_sel = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel; endcase @@ -14775,12 +14775,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_cry_in = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_cry_in = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in; endcase @@ -14788,12 +14788,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_inv_a = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_inv_a = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a; endcase @@ -14801,12 +14801,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_inv_out = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_inv_out = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out; endcase @@ -14814,12 +14814,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_cry_out = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_cry_out = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out; endcase @@ -14827,12 +14827,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_is_32b = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_is_32b = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b; endcase @@ -14840,12 +14840,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_sgn = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_sgn = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn; endcase @@ -14853,12 +14853,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_function_unit = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_function_unit = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit; endcase @@ -14866,12 +14866,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_internal_op = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_internal_op = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op; endcase @@ -14879,12 +14879,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_in1_sel = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_in1_sel = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel; endcase @@ -14892,12 +14892,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_in2_sel = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_in2_sel = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel; endcase @@ -14905,12 +14905,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_cr_in = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_cr_in = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in; endcase @@ -14918,12 +14918,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: LOGICAL_dec31_cr_out = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: LOGICAL_dec31_cr_out = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out; endcase @@ -14947,7 +14947,7 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub26_cr_in; reg [2:0] LOGICAL_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) @@ -14957,17 +14957,17 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub26_cr_out; reg [2:0] LOGICAL_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_dec_sub26_cry_in; reg [1:0] LOGICAL_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub26_cry_out; reg LOGICAL_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) @@ -14985,7 +14985,7 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LOGICAL_dec31_dec_sub26_function_unit; reg [13:0] LOGICAL_dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) @@ -14994,7 +14994,7 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub26_in1_sel; reg [2:0] LOGICAL_dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) @@ -15012,7 +15012,7 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_dec_sub26_in2_sel; reg [3:0] LOGICAL_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) @@ -15090,16 +15090,16 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LOGICAL_dec31_dec_sub26_internal_op; reg [6:0] LOGICAL_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub26_inv_a; reg LOGICAL_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub26_inv_out; reg LOGICAL_dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub26_is_32b; reg LOGICAL_dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) @@ -15108,53 +15108,53 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_dec_sub26_ldst_len; reg [3:0] LOGICAL_dec31_dec_sub26_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_dec_sub26_rc_sel; reg [1:0] LOGICAL_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub26_sgn; reg LOGICAL_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; endcase @@ -15162,33 +15162,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; endcase @@ -15196,33 +15196,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; endcase @@ -15230,33 +15230,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; endcase @@ -15264,33 +15264,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; endcase @@ -15298,33 +15298,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_sgn = 1'h0; endcase @@ -15332,33 +15332,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_internal_op = 7'h37; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_internal_op = 7'h37; endcase @@ -15366,33 +15366,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; endcase @@ -15400,33 +15400,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; endcase @@ -15434,33 +15434,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; endcase @@ -15468,33 +15468,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_cr_out = 3'h0; endcase @@ -15502,33 +15502,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_ldst_len = 4'h4; endcase @@ -15536,33 +15536,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; endcase @@ -15570,33 +15570,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: LOGICAL_dec31_dec_sub26_cry_in = 2'h0; endcase @@ -15617,7 +15617,7 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub28_cr_in; reg [2:0] LOGICAL_dec31_dec_sub28_cr_in; (* enum_base_type = "CROutSel" *) @@ -15627,17 +15627,17 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub28_cr_out; reg [2:0] LOGICAL_dec31_dec_sub28_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_dec_sub28_cry_in; reg [1:0] LOGICAL_dec31_dec_sub28_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub28_cry_out; reg LOGICAL_dec31_dec_sub28_cry_out; (* enum_base_type = "Function" *) @@ -15655,7 +15655,7 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LOGICAL_dec31_dec_sub28_function_unit; reg [13:0] LOGICAL_dec31_dec_sub28_function_unit; (* enum_base_type = "In1Sel" *) @@ -15664,7 +15664,7 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub28_in1_sel; reg [2:0] LOGICAL_dec31_dec_sub28_in1_sel; (* enum_base_type = "In2Sel" *) @@ -15682,7 +15682,7 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_dec_sub28_in2_sel; reg [3:0] LOGICAL_dec31_dec_sub28_in2_sel; (* enum_base_type = "MicrOp" *) @@ -15760,16 +15760,16 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LOGICAL_dec31_dec_sub28_internal_op; reg [6:0] LOGICAL_dec31_dec_sub28_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub28_inv_a; reg LOGICAL_dec31_dec_sub28_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub28_inv_out; reg LOGICAL_dec31_dec_sub28_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub28_is_32b; reg LOGICAL_dec31_dec_sub28_is_32b; (* enum_base_type = "LdstLen" *) @@ -15778,56 +15778,56 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_dec_sub28_ldst_len; reg [3:0] LOGICAL_dec31_dec_sub28_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_dec_sub28_rc_sel; reg [1:0] LOGICAL_dec31_dec_sub28_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub28_sgn; reg LOGICAL_dec31_dec_sub28_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; endcase @@ -15835,36 +15835,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; endcase @@ -15872,36 +15872,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; endcase @@ -15909,36 +15909,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; endcase @@ -15946,36 +15946,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; endcase @@ -15983,36 +15983,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_sgn = 1'h0; endcase @@ -16020,36 +16020,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_internal_op = 7'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_internal_op = 7'h0b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_internal_op = 7'h43; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_internal_op = 7'h43; endcase @@ -16057,36 +16057,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; endcase @@ -16094,36 +16094,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; endcase @@ -16131,36 +16131,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; endcase @@ -16168,36 +16168,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; endcase @@ -16205,36 +16205,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; endcase @@ -16242,36 +16242,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; endcase @@ -16279,36 +16279,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: LOGICAL_dec31_dec_sub28_cry_in = 2'h0; endcase @@ -16329,7 +16329,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_cr_in; reg [2:0] MUL_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -16339,7 +16339,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_cr_out; reg [2:0] MUL_dec31_cr_out; (* enum_base_type = "CRInSel" *) @@ -16351,7 +16351,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -16360,7 +16360,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -16377,7 +16377,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -16394,7 +16394,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -16471,19 +16471,19 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] MUL_dec31_dec_sub11_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -16494,7 +16494,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -16503,7 +16503,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -16520,7 +16520,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -16537,7 +16537,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -16614,19 +16614,19 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] MUL_dec31_dec_sub9_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -16643,7 +16643,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] MUL_dec31_function_unit; reg [13:0] MUL_dec31_function_unit; (* enum_base_type = "In2Sel" *) @@ -16661,7 +16661,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] MUL_dec31_in2_sel; reg [3:0] MUL_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -16739,27 +16739,27 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] MUL_dec31_internal_op; reg [6:0] MUL_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_is_32b; reg MUL_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] MUL_dec31_rc_sel; reg [1:0] MUL_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_sgn; reg MUL_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:349" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; MUL_dec31_dec_sub11 MUL_dec31_dec_sub11 ( .MUL_dec31_dec_sub11_cr_in(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in), @@ -16786,12 +16786,12 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: MUL_dec31_is_32b = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: MUL_dec31_is_32b = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b; endcase @@ -16799,12 +16799,12 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: MUL_dec31_sgn = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: MUL_dec31_sgn = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn; endcase @@ -16812,12 +16812,12 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: MUL_dec31_function_unit = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: MUL_dec31_function_unit = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit; endcase @@ -16825,12 +16825,12 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: MUL_dec31_internal_op = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: MUL_dec31_internal_op = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op; endcase @@ -16838,12 +16838,12 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: MUL_dec31_in2_sel = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: MUL_dec31_in2_sel = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel; endcase @@ -16851,12 +16851,12 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: MUL_dec31_cr_in = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: MUL_dec31_cr_in = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in; endcase @@ -16864,12 +16864,12 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: MUL_dec31_cr_out = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: MUL_dec31_cr_out = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out; endcase @@ -16877,12 +16877,12 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: MUL_dec31_rc_sel = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: MUL_dec31_rc_sel = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel; endcase @@ -16906,7 +16906,7 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_dec_sub11_cr_in; reg [2:0] MUL_dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) @@ -16916,7 +16916,7 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_dec_sub11_cr_out; reg [2:0] MUL_dec31_dec_sub11_cr_out; (* enum_base_type = "Function" *) @@ -16934,7 +16934,7 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] MUL_dec31_dec_sub11_function_unit; reg [13:0] MUL_dec31_dec_sub11_function_unit; (* enum_base_type = "In2Sel" *) @@ -16952,7 +16952,7 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] MUL_dec31_dec_sub11_in2_sel; reg [3:0] MUL_dec31_dec_sub11_in2_sel; (* enum_base_type = "MicrOp" *) @@ -17030,47 +17030,47 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] MUL_dec31_dec_sub11_internal_op; reg [6:0] MUL_dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_dec_sub11_is_32b; reg MUL_dec31_dec_sub11_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] MUL_dec31_dec_sub11_rc_sel; reg [1:0] MUL_dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_dec_sub11_sgn; reg MUL_dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub11_function_unit = 14'h0100; endcase @@ -17078,24 +17078,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub11_internal_op = 7'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub11_internal_op = 7'h32; endcase @@ -17103,24 +17103,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub11_in2_sel = 4'h1; endcase @@ -17128,24 +17128,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub11_cr_in = 3'h0; endcase @@ -17153,24 +17153,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub11_cr_out = 3'h1; endcase @@ -17178,24 +17178,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub11_rc_sel = 2'h2; endcase @@ -17203,24 +17203,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub11_is_32b = 1'h1; endcase @@ -17228,24 +17228,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub11_sgn = 1'h1; endcase @@ -17266,7 +17266,7 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_dec_sub9_cr_in; reg [2:0] MUL_dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) @@ -17276,7 +17276,7 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_dec_sub9_cr_out; reg [2:0] MUL_dec31_dec_sub9_cr_out; (* enum_base_type = "Function" *) @@ -17294,7 +17294,7 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] MUL_dec31_dec_sub9_function_unit; reg [13:0] MUL_dec31_dec_sub9_function_unit; (* enum_base_type = "In2Sel" *) @@ -17312,7 +17312,7 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] MUL_dec31_dec_sub9_in2_sel; reg [3:0] MUL_dec31_dec_sub9_in2_sel; (* enum_base_type = "MicrOp" *) @@ -17390,47 +17390,47 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] MUL_dec31_dec_sub9_internal_op; reg [6:0] MUL_dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_dec_sub9_is_32b; reg MUL_dec31_dec_sub9_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] MUL_dec31_dec_sub9_rc_sel; reg [1:0] MUL_dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_dec_sub9_sgn; reg MUL_dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub9_function_unit = 14'h0100; endcase @@ -17438,24 +17438,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub9_internal_op = 7'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub9_internal_op = 7'h32; endcase @@ -17463,24 +17463,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub9_in2_sel = 4'h1; endcase @@ -17488,24 +17488,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub9_cr_in = 3'h0; endcase @@ -17513,24 +17513,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub9_cr_out = 3'h1; endcase @@ -17538,24 +17538,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub9_rc_sel = 2'h2; endcase @@ -17563,24 +17563,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub9_is_32b = 1'h0; endcase @@ -17588,24 +17588,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: MUL_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: MUL_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: MUL_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: MUL_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: MUL_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: MUL_dec31_dec_sub9_sgn = 1'h1; endcase @@ -17626,7 +17626,7 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec30_cr_in; reg [2:0] SHIFT_ROT_dec30_cr_in; (* enum_base_type = "CROutSel" *) @@ -17636,17 +17636,17 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec30_cr_out; reg [2:0] SHIFT_ROT_dec30_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec30_cry_in; reg [1:0] SHIFT_ROT_dec30_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec30_cry_out; reg SHIFT_ROT_dec30_cry_out; (* enum_base_type = "Function" *) @@ -17664,7 +17664,7 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] SHIFT_ROT_dec30_function_unit; reg [13:0] SHIFT_ROT_dec30_function_unit; (* enum_base_type = "In2Sel" *) @@ -17682,7 +17682,7 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_dec30_in2_sel; reg [3:0] SHIFT_ROT_dec30_in2_sel; (* enum_base_type = "MicrOp" *) @@ -17760,62 +17760,62 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_dec30_internal_op; reg [6:0] SHIFT_ROT_dec30_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec30_inv_a; reg SHIFT_ROT_dec30_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec30_is_32b; reg SHIFT_ROT_dec30_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec30_rc_sel; reg [1:0] SHIFT_ROT_dec30_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec30_sgn; reg SHIFT_ROT_dec30_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [3:0] opcode_switch; always @* begin if (\initial ) begin end SHIFT_ROT_dec30_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_function_unit = 14'h0008; endcase @@ -17823,36 +17823,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_is_32b = 1'h0; endcase @@ -17860,36 +17860,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_sgn = 1'h0; endcase @@ -17897,36 +17897,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_internal_op = 7'h3a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_internal_op = 7'h3a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_internal_op = 7'h3a; endcase @@ -17934,36 +17934,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_in2_sel = 4'h1; endcase @@ -17971,36 +17971,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_cr_in = 3'h0; endcase @@ -18008,36 +18008,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_cr_out = 3'h1; endcase @@ -18045,36 +18045,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_rc_sel = 2'h2; endcase @@ -18082,36 +18082,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_cry_in = 2'h0; endcase @@ -18119,36 +18119,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_inv_a = 1'h0; endcase @@ -18156,36 +18156,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: SHIFT_ROT_dec30_cry_out = 1'h0; endcase @@ -18206,7 +18206,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_cr_in; reg [2:0] SHIFT_ROT_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -18216,17 +18216,17 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_cr_out; reg [2:0] SHIFT_ROT_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_cry_in; reg [1:0] SHIFT_ROT_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_cry_out; reg SHIFT_ROT_dec31_cry_out; (* enum_base_type = "CRInSel" *) @@ -18238,7 +18238,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -18247,15 +18247,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -18272,7 +18272,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -18289,7 +18289,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -18366,21 +18366,21 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] SHIFT_ROT_dec31_dec_sub24_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -18391,7 +18391,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -18400,15 +18400,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -18425,7 +18425,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -18442,7 +18442,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -18519,21 +18519,21 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] SHIFT_ROT_dec31_dec_sub26_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -18544,7 +18544,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -18553,15 +18553,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -18578,7 +18578,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -18595,7 +18595,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -18672,21 +18672,21 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] SHIFT_ROT_dec31_dec_sub27_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -18703,7 +18703,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] SHIFT_ROT_dec31_function_unit; reg [13:0] SHIFT_ROT_dec31_function_unit; (* enum_base_type = "In2Sel" *) @@ -18721,7 +18721,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_dec31_in2_sel; reg [3:0] SHIFT_ROT_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -18799,30 +18799,30 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_dec31_internal_op; reg [6:0] SHIFT_ROT_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_inv_a; reg SHIFT_ROT_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_is_32b; reg SHIFT_ROT_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_rc_sel; reg [1:0] SHIFT_ROT_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_sgn; reg SHIFT_ROT_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:349" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; SHIFT_ROT_dec31_dec_sub24 SHIFT_ROT_dec31_dec_sub24 ( .SHIFT_ROT_dec31_dec_sub24_cr_in(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in), @@ -18869,15 +18869,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_rc_sel = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_rc_sel = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_rc_sel = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel; endcase @@ -18885,15 +18885,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_cry_in = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_cry_in = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_cry_in = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in; endcase @@ -18901,15 +18901,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_inv_a = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_inv_a = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_inv_a = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a; endcase @@ -18917,15 +18917,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_cry_out = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_cry_out = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_cry_out = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out; endcase @@ -18933,15 +18933,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_is_32b = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_is_32b = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_is_32b = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b; endcase @@ -18949,15 +18949,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_sgn = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_sgn = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_sgn = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn; endcase @@ -18965,15 +18965,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_function_unit = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_function_unit = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_function_unit = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit; endcase @@ -18981,15 +18981,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_internal_op = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_internal_op = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_internal_op = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op; endcase @@ -18997,15 +18997,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel; endcase @@ -19013,15 +19013,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in; endcase @@ -19029,15 +19029,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out; endcase @@ -19062,7 +19062,7 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub24_cr_in; reg [2:0] SHIFT_ROT_dec31_dec_sub24_cr_in; (* enum_base_type = "CROutSel" *) @@ -19072,17 +19072,17 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub24_cr_out; reg [2:0] SHIFT_ROT_dec31_dec_sub24_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub24_cry_in; reg [1:0] SHIFT_ROT_dec31_dec_sub24_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub24_cry_out; reg SHIFT_ROT_dec31_dec_sub24_cry_out; (* enum_base_type = "Function" *) @@ -19100,7 +19100,7 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] SHIFT_ROT_dec31_dec_sub24_function_unit; reg [13:0] SHIFT_ROT_dec31_dec_sub24_function_unit; (* enum_base_type = "In2Sel" *) @@ -19118,7 +19118,7 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_dec31_dec_sub24_in2_sel; reg [3:0] SHIFT_ROT_dec31_dec_sub24_in2_sel; (* enum_base_type = "MicrOp" *) @@ -19196,44 +19196,44 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_dec31_dec_sub24_internal_op; reg [6:0] SHIFT_ROT_dec31_dec_sub24_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub24_inv_a; reg SHIFT_ROT_dec31_dec_sub24_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub24_is_32b; reg SHIFT_ROT_dec31_dec_sub24_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub24_rc_sel; reg [1:0] SHIFT_ROT_dec31_dec_sub24_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub24_sgn; reg SHIFT_ROT_dec31_dec_sub24_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; endcase @@ -19241,18 +19241,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; endcase @@ -19260,18 +19260,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_sgn = 1'h0; endcase @@ -19279,18 +19279,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3d; endcase @@ -19298,18 +19298,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h1; endcase @@ -19317,18 +19317,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; endcase @@ -19336,18 +19336,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; endcase @@ -19355,18 +19355,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; endcase @@ -19374,18 +19374,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; endcase @@ -19393,18 +19393,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; endcase @@ -19412,18 +19412,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; endcase @@ -19444,7 +19444,7 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub26_cr_in; reg [2:0] SHIFT_ROT_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) @@ -19454,17 +19454,17 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub26_cr_out; reg [2:0] SHIFT_ROT_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub26_cry_in; reg [1:0] SHIFT_ROT_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub26_cry_out; reg SHIFT_ROT_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) @@ -19482,7 +19482,7 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] SHIFT_ROT_dec31_dec_sub26_function_unit; reg [13:0] SHIFT_ROT_dec31_dec_sub26_function_unit; (* enum_base_type = "In2Sel" *) @@ -19500,7 +19500,7 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_dec31_dec_sub26_in2_sel; reg [3:0] SHIFT_ROT_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) @@ -19578,41 +19578,41 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_dec31_dec_sub26_internal_op; reg [6:0] SHIFT_ROT_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub26_inv_a; reg SHIFT_ROT_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub26_is_32b; reg SHIFT_ROT_dec31_dec_sub26_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub26_rc_sel; reg [1:0] SHIFT_ROT_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub26_sgn; reg SHIFT_ROT_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0008; endcase @@ -19620,15 +19620,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; endcase @@ -19636,15 +19636,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_sgn = 1'h1; endcase @@ -19652,15 +19652,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h20; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h3d; endcase @@ -19668,15 +19668,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'ha; endcase @@ -19684,15 +19684,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; endcase @@ -19700,15 +19700,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h1; endcase @@ -19716,15 +19716,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h2; endcase @@ -19732,15 +19732,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; endcase @@ -19748,15 +19748,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; endcase @@ -19764,15 +19764,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h1; endcase @@ -19793,7 +19793,7 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub27_cr_in; reg [2:0] SHIFT_ROT_dec31_dec_sub27_cr_in; (* enum_base_type = "CROutSel" *) @@ -19803,17 +19803,17 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub27_cr_out; reg [2:0] SHIFT_ROT_dec31_dec_sub27_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub27_cry_in; reg [1:0] SHIFT_ROT_dec31_dec_sub27_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub27_cry_out; reg SHIFT_ROT_dec31_dec_sub27_cry_out; (* enum_base_type = "Function" *) @@ -19831,7 +19831,7 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] SHIFT_ROT_dec31_dec_sub27_function_unit; reg [13:0] SHIFT_ROT_dec31_dec_sub27_function_unit; (* enum_base_type = "In2Sel" *) @@ -19849,7 +19849,7 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_dec31_dec_sub27_in2_sel; reg [3:0] SHIFT_ROT_dec31_dec_sub27_in2_sel; (* enum_base_type = "MicrOp" *) @@ -19927,44 +19927,44 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_dec31_dec_sub27_internal_op; reg [6:0] SHIFT_ROT_dec31_dec_sub27_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub27_inv_a; reg SHIFT_ROT_dec31_dec_sub27_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub27_is_32b; reg SHIFT_ROT_dec31_dec_sub27_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub27_rc_sel; reg [1:0] SHIFT_ROT_dec31_dec_sub27_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub27_sgn; reg SHIFT_ROT_dec31_dec_sub27_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; endcase @@ -19972,18 +19972,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; endcase @@ -19991,18 +19991,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; endcase @@ -20010,18 +20010,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h20; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h3c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h3d; endcase @@ -20029,18 +20029,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'h1; endcase @@ -20048,18 +20048,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; endcase @@ -20067,18 +20067,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; endcase @@ -20086,18 +20086,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; endcase @@ -20105,18 +20105,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; endcase @@ -20124,18 +20124,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; endcase @@ -20143,18 +20143,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; endcase @@ -20175,7 +20175,7 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SPR_dec31_cr_in; reg [2:0] SPR_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -20185,7 +20185,7 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SPR_dec31_cr_out; reg [2:0] SPR_dec31_cr_out; (* enum_base_type = "CRInSel" *) @@ -20197,7 +20197,7 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -20206,7 +20206,7 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -20223,7 +20223,7 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -20300,17 +20300,17 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] SPR_dec31_dec_sub19_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -20327,7 +20327,7 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] SPR_dec31_function_unit; reg [13:0] SPR_dec31_function_unit; (* enum_base_type = "MicrOp" *) @@ -20405,24 +20405,24 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SPR_dec31_internal_op; reg [6:0] SPR_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SPR_dec31_is_32b; reg SPR_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SPR_dec31_rc_sel; reg [1:0] SPR_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:349" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; SPR_dec31_dec_sub19 SPR_dec31_dec_sub19 ( .SPR_dec31_dec_sub19_cr_in(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in), @@ -20436,9 +20436,9 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in always @* begin if (\initial ) begin end SPR_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: SPR_dec31_function_unit = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit; endcase @@ -20446,9 +20446,9 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in always @* begin if (\initial ) begin end SPR_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: SPR_dec31_internal_op = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op; endcase @@ -20456,9 +20456,9 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in always @* begin if (\initial ) begin end SPR_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: SPR_dec31_cr_in = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in; endcase @@ -20466,9 +20466,9 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in always @* begin if (\initial ) begin end SPR_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: SPR_dec31_cr_out = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out; endcase @@ -20476,9 +20476,9 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in always @* begin if (\initial ) begin end SPR_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: SPR_dec31_rc_sel = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel; endcase @@ -20486,9 +20486,9 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in always @* begin if (\initial ) begin end SPR_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: SPR_dec31_is_32b = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b; endcase @@ -20511,7 +20511,7 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SPR_dec31_dec_sub19_cr_in; reg [2:0] SPR_dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) @@ -20521,7 +20521,7 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SPR_dec31_dec_sub19_cr_out; reg [2:0] SPR_dec31_dec_sub19_cr_out; (* enum_base_type = "Function" *) @@ -20539,7 +20539,7 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] SPR_dec31_dec_sub19_function_unit; reg [13:0] SPR_dec31_dec_sub19_function_unit; (* enum_base_type = "MicrOp" *) @@ -20617,32 +20617,32 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SPR_dec31_dec_sub19_internal_op; reg [6:0] SPR_dec31_dec_sub19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SPR_dec31_dec_sub19_is_32b; reg SPR_dec31_dec_sub19_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SPR_dec31_dec_sub19_rc_sel; reg [1:0] SPR_dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: SPR_dec31_dec_sub19_function_unit = 14'h0400; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: SPR_dec31_dec_sub19_function_unit = 14'h0400; endcase @@ -20650,12 +20650,12 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: SPR_dec31_dec_sub19_internal_op = 7'h2e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: SPR_dec31_dec_sub19_internal_op = 7'h31; endcase @@ -20663,12 +20663,12 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: SPR_dec31_dec_sub19_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: SPR_dec31_dec_sub19_cr_in = 3'h0; endcase @@ -20676,12 +20676,12 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: SPR_dec31_dec_sub19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: SPR_dec31_dec_sub19_cr_out = 3'h0; endcase @@ -20689,12 +20689,12 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: SPR_dec31_dec_sub19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: SPR_dec31_dec_sub19_rc_sel = 2'h0; endcase @@ -20702,12 +20702,12 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: SPR_dec31_dec_sub19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: SPR_dec31_dec_sub19_is_32b = 1'h0; endcase @@ -20735,9 +20735,9 @@ module adr_l(coresync_rst, s_adr, r_adr, q_adr, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_adr; @@ -20766,7 +20766,7 @@ module adr_l(coresync_rst, s_adr, r_adr, q_adr, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -20797,9 +20797,9 @@ module adrok_l(coresync_rst, s_addr_acked, r_addr_acked, qn_addr_acked, q_addr_a wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_addr_acked; @@ -20828,7 +20828,7 @@ module adrok_l(coresync_rst, s_addr_acked, r_addr_acked, qn_addr_acked, q_addr_a always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -21153,13 +21153,13 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, reg alu_alu0_alu_op__zero_a = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg \alu_alu0_alu_op__zero_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] alu_alu0_cr_a; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_alu0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_alu0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_alu0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_alu0_p_ready_o; @@ -21169,13 +21169,13 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, wire [63:0] alu_alu0_ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] alu_alu0_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] alu_alu0_xer_ca; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] \alu_alu0_xer_ca$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] alu_alu0_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire alu_alu0_xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire \alu_alu0_xer_so$1 ; @@ -21207,11 +21207,11 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -21290,7 +21290,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output dest5_o; reg dest5_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -21518,11 +21518,11 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, wire \src_sel$85 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; assign \$5 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ; assign \$99 = alu_alu0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; @@ -21786,7 +21786,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -21795,7 +21795,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -21804,7 +21804,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -21813,7 +21813,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -21822,7 +21822,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -21831,7 +21831,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -21840,7 +21840,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 4'h0; @@ -21849,7 +21849,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 4'hf; @@ -21858,7 +21858,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 5'h00; @@ -21867,7 +21867,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 5'h1f; @@ -21899,7 +21899,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \alu_alu0_alu_op__insn$next , \alu_alu0_alu_op__data_len$next , \alu_alu0_alu_op__is_signed$next , \alu_alu0_alu_op__is_32bit$next , \alu_alu0_alu_op__output_carry$next , \alu_alu0_alu_op__input_carry$next , \alu_alu0_alu_op__write_cr0$next , \alu_alu0_alu_op__invert_out$next , \alu_alu0_alu_op__zero_a$next , \alu_alu0_alu_op__invert_in$next , \alu_alu0_alu_op__oe__ok$next , \alu_alu0_alu_op__oe__oe$next , \alu_alu0_alu_op__rc__ok$next , \alu_alu0_alu_op__rc__rc$next , \alu_alu0_alu_op__imm_data__ok$next , \alu_alu0_alu_op__imm_data__data$next , \alu_alu0_alu_op__fn_unit$next , \alu_alu0_alu_op__insn_type$next } = { oper_i_alu_alu0__insn, oper_i_alu_alu0__data_len, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -21928,7 +21928,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -21950,7 +21950,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -21972,7 +21972,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r2__xer_ca_ok$next , \data_r2__xer_ca$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__xer_ca_ok$next = 1'h0; @@ -21994,7 +21994,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r3__xer_ov_ok$next , \data_r3__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r3__xer_ov_ok$next = 1'h0; @@ -22016,7 +22016,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r4__xer_so_ok$next , \data_r4__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r4__xer_so_ok$next = 1'h0; @@ -22065,7 +22065,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$99 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -22074,7 +22074,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$101 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -22133,7 +22133,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 5'h00; @@ -22437,13 +22437,13 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ input alu_op__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \alu_op__zero_a$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; @@ -22453,9 +22453,9 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -22721,9 +22721,9 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ wire pipe1_alu_op__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \pipe1_alu_op__zero_a$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] pipe1_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe1_muxid; @@ -22733,9 +22733,9 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ wire pipe1_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe1_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe1_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe1_p_ready_o; @@ -22745,21 +22745,21 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ wire [63:0] pipe1_ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] pipe1_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] pipe1_xer_ca; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] \pipe1_xer_ca$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] pipe1_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire \pipe1_xer_so$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_xer_so_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [3:0] pipe2_alu_op__data_len; @@ -23021,13 +23021,13 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ wire pipe2_alu_op__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \pipe2_alu_op__zero_a$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] pipe2_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \pipe2_cr_a$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe2_cr_a_ok$46 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe2_muxid; @@ -23037,61 +23037,61 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ wire pipe2_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe2_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \pipe2_o$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe2_o_ok$44 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe2_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire pipe2_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] pipe2_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \pipe2_xer_ca$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe2_xer_ca_ok$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] pipe2_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \pipe2_xer_ov$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe2_xer_ov_ok$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe2_xer_so$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe2_xer_so_ok$52 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ca; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] \xer_ca$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input \xer_so$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; n n ( .n_ready_i(n_ready_i), @@ -23471,23 +23471,23 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ input br_op__lk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \br_op__lk$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] fast1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] \fast1$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] fast2; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] \fast2$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast2_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; @@ -23497,9 +23497,9 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output nia_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -23721,15 +23721,15 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ wire [3:0] pipe_cr_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] pipe_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \pipe_fast1$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_fast1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] pipe_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \pipe_fast2$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_fast2_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe_muxid; @@ -23739,9 +23739,9 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ wire pipe_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe_nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_nia_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe_p_ready_o; @@ -23810,15 +23810,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0" *) (* generator = "nMigen" *) module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [3:0] \cr_a$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [3:0] cr_b; @@ -24016,11 +24016,11 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr (* enum_value_1001100 = "OP_SETVL" *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [6:0] \cr_op__insn_type$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [31:0] full_cr; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [31:0] \full_cr$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output full_cr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; @@ -24030,9 +24030,9 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -24040,9 +24040,9 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr input p_valid_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [3:0] pipe_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \pipe_cr_a$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [3:0] pipe_cr_b; @@ -24242,9 +24242,9 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr wire [6:0] \pipe_cr_op__insn_type$4 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [31:0] pipe_full_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [31:0] \pipe_full_cr$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_full_cr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe_muxid; @@ -24254,9 +24254,9 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr wire pipe_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe_p_ready_o; @@ -24329,13 +24329,13 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0" *) (* generator = "nMigen" *) module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) input [3:0] logical_op__data_len; @@ -24605,17 +24605,17 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] pipe_end_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_end_cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) wire pipe_end_div_by_zero; @@ -24895,9 +24895,9 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire pipe_end_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe_end_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe_end_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_end_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe_end_p_ready_o; @@ -24911,15 +24911,15 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire [63:0] pipe_end_rb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) wire [191:0] pipe_end_remainder; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] pipe_end_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_end_xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire pipe_end_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe_end_xer_so$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_end_xer_so_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) wire pipe_middle_0_div_by_zero; @@ -25539,15 +25539,15 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ input [63:0] ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input \xer_so$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; \n$75 n ( .n_ready_i(n_ready_i), @@ -25815,9 +25815,9 @@ module alu_l(coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -25846,7 +25846,7 @@ module alu_l(coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -25877,9 +25877,9 @@ module \alu_l$107 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -25908,7 +25908,7 @@ module \alu_l$107 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -25939,9 +25939,9 @@ module \alu_l$125 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -25970,7 +25970,7 @@ module \alu_l$125 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26001,9 +26001,9 @@ module \alu_l$128 (coresync_rst, s_alu, r_alu, q_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26032,7 +26032,7 @@ module \alu_l$128 (coresync_rst, s_alu, r_alu, q_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26063,9 +26063,9 @@ module \alu_l$16 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26094,7 +26094,7 @@ module \alu_l$16 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26125,9 +26125,9 @@ module \alu_l$29 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26156,7 +26156,7 @@ module \alu_l$29 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26187,9 +26187,9 @@ module \alu_l$45 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26218,7 +26218,7 @@ module \alu_l$45 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26249,9 +26249,9 @@ module \alu_l$61 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26280,7 +26280,7 @@ module \alu_l$61 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26311,9 +26311,9 @@ module \alu_l$73 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26342,7 +26342,7 @@ module \alu_l$73 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26373,9 +26373,9 @@ module \alu_l$90 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26404,7 +26404,7 @@ module \alu_l$90 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26418,13 +26418,13 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0" *) (* generator = "nMigen" *) module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) input [3:0] logical_op__data_len; @@ -26686,9 +26686,9 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o input logical_op__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \logical_op__zero_a$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] logical_pipe1_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire logical_pipe1_cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [3:0] logical_pipe1_logical_op__data_len; @@ -26958,9 +26958,9 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o wire logical_pipe1_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire logical_pipe1_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] logical_pipe1_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire logical_pipe1_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire logical_pipe1_p_ready_o; @@ -26970,19 +26970,19 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o wire [63:0] logical_pipe1_ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] logical_pipe1_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire logical_pipe1_xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire \logical_pipe1_xer_so$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire logical_pipe1_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] logical_pipe2_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \logical_pipe2_cr_a$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire logical_pipe2_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \logical_pipe2_cr_a_ok$43 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [3:0] logical_pipe2_logical_op__data_len; @@ -27252,21 +27252,21 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o wire logical_pipe2_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire logical_pipe2_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] logical_pipe2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \logical_pipe2_o$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire logical_pipe2_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \logical_pipe2_o_ok$41 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire logical_pipe2_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire logical_pipe2_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire logical_pipe2_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire logical_pipe2_xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; @@ -27276,9 +27276,9 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -27435,13 +27435,13 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0" *) (* generator = "nMigen" *) module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -28185,9 +28185,9 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire mul_pipe2_xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire \mul_pipe2_xer_so$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] mul_pipe3_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire mul_pipe3_cr_a_ok; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -28431,23 +28431,23 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire mul_pipe3_neg_res32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [128:0] mul_pipe3_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \mul_pipe3_o$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire mul_pipe3_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire mul_pipe3_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire mul_pipe3_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] mul_pipe3_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire mul_pipe3_xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire mul_pipe3_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \mul_pipe3_xer_so$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire mul_pipe3_xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; @@ -28457,9 +28457,9 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -28469,15 +28469,15 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ input [63:0] ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input \xer_so$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; mul_pipe1 mul_pipe1 ( .coresync_clk(coresync_clk), @@ -28656,13 +28656,13 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" *) (* generator = "nMigen" *) module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; @@ -28672,17 +28672,17 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] pipe1_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe1_muxid; @@ -28692,9 +28692,9 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready wire pipe1_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe1_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe1_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe1_p_ready_o; @@ -28962,25 +28962,25 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready wire pipe1_sr_op__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \pipe1_sr_op__write_cr0$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] pipe1_xer_ca; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] \pipe1_xer_ca$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire \pipe1_xer_so$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe1_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] pipe2_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \pipe2_cr_a$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe2_cr_a_ok$43 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe2_muxid; @@ -28990,13 +28990,13 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready wire pipe2_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe2_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \pipe2_o$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe2_o_ok$41 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe2_p_ready_o; @@ -29258,17 +29258,17 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready wire pipe2_sr_op__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \pipe2_sr_op__write_cr0$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] pipe2_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \pipe2_xer_ca$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe2_xer_ca_ok$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_xer_so_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] ra; @@ -29532,11 +29532,11 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready input sr_op__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \sr_op__write_cr0$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ca; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] \xer_ca$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input xer_so; @@ -29693,15 +29693,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0" *) (* generator = "nMigen" *) module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] fast1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] \fast1$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; @@ -29711,9 +29711,9 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -29721,9 +29721,9 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s input p_valid_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] pipe_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \pipe_fast1$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe_muxid; @@ -29733,9 +29733,9 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s wire pipe_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe_p_ready_o; @@ -29745,9 +29745,9 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s wire [63:0] pipe_ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] pipe_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \pipe_spr1$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_spr1_ok; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -29947,29 +29947,29 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s wire \pipe_spr_op__is_32bit$10 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] pipe_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \pipe_xer_ca$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_xer_ca_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] pipe_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \pipe_xer_ov$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire pipe_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \pipe_xer_so$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe_xer_so_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] spr1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] \spr1$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spr1_ok; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -30167,23 +30167,23 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s input spr_op__is_32bit; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \spr_op__is_32bit$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ca; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] \xer_ca$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ov; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] \xer_ov$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input \xer_so$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; \n$63 n ( .n_ready_i(n_ready_i), @@ -30255,25 +30255,25 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0" *) (* generator = "nMigen" *) module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, o, fast1, fast2, nia, msr, ra, rb, \fast1$1 , \fast2$2 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] fast1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] \fast1$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] fast2; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] \fast2$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output msr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; @@ -30283,13 +30283,13 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -30541,19 +30541,19 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid wire [7:0] \pipe1_trap_op__traptype$10 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] pipe2_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \pipe2_fast1$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_fast1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] pipe2_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \pipe2_fast2$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe2_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_msr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe2_muxid; @@ -30563,13 +30563,13 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid wire pipe2_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe2_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe2_nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pipe2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pipe2_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe2_p_ready_o; @@ -31149,9 +31149,9 @@ module alui_l(coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31180,7 +31180,7 @@ module alui_l(coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31211,9 +31211,9 @@ module \alui_l$106 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31242,7 +31242,7 @@ module \alui_l$106 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31273,9 +31273,9 @@ module \alui_l$124 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31304,7 +31304,7 @@ module \alui_l$124 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31335,9 +31335,9 @@ module \alui_l$15 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31366,7 +31366,7 @@ module \alui_l$15 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31397,9 +31397,9 @@ module \alui_l$28 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31428,7 +31428,7 @@ module \alui_l$28 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31459,9 +31459,9 @@ module \alui_l$44 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31490,7 +31490,7 @@ module \alui_l$44 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31521,9 +31521,9 @@ module \alui_l$60 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31552,7 +31552,7 @@ module \alui_l$60 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31583,9 +31583,9 @@ module \alui_l$72 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31614,7 +31614,7 @@ module \alui_l$72 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31645,9 +31645,9 @@ module \alui_l$89 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31676,7 +31676,7 @@ module \alui_l$89 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -33295,11 +33295,11 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t reg \alu_branch0_br_op__lk$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [3:0] alu_branch0_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_branch0_fast1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] \alu_branch0_fast1$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_branch0_fast2; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] \alu_branch0_fast2$2 ; @@ -33307,7 +33307,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t wire alu_branch0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_branch0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_branch0_nia; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_branch0_p_ready_o; @@ -33341,9 +33341,9 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -33400,11 +33400,11 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [63:0] dest3_o; reg [63:0] dest3_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output nia_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -33805,7 +33805,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -33814,7 +33814,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -33823,7 +33823,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -33832,7 +33832,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -33841,7 +33841,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -33850,7 +33850,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -33859,7 +33859,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -33868,7 +33868,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -33877,7 +33877,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 3'h0; @@ -33886,7 +33886,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 3'h7; @@ -33908,7 +33908,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \alu_branch0_br_op__is_32bit$next , \alu_branch0_br_op__lk$next , \alu_branch0_br_op__imm_data__ok$next , \alu_branch0_br_op__imm_data__data$next , \alu_branch0_br_op__insn$next , \alu_branch0_br_op__fn_unit$next , \alu_branch0_br_op__insn_type$next , \alu_branch0_br_op__cia$next } = { oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__lk, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__insn, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__cia }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -33933,7 +33933,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \data_r0__fast1_ok$next , \data_r0__fast1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__fast1_ok$next = 1'h0; @@ -33955,7 +33955,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \data_r1__fast2_ok$next , \data_r1__fast2$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__fast2_ok$next = 1'h0; @@ -33977,7 +33977,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \data_r2__nia_ok$next , \data_r2__nia$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__nia_ok$next = 1'h0; @@ -34016,7 +34016,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$87 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -34025,7 +34025,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -34064,7 +34064,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 3'h0; @@ -34122,9 +34122,9 @@ module busy_l(coresync_rst, s_busy, r_busy, q_busy, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_busy; @@ -34153,7 +34153,7 @@ module busy_l(coresync_rst, s_busy, r_busy, q_busy, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -35874,103 +35874,103 @@ endmodule (* generator = "nMigen" *) module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, core_terminate_o, msr__data_o, core_rego, core_ea, core_reg1, core_reg1_ok, core_reg2, core_reg2_ok, core_reg3, core_reg3_ok, core_spro, core_spr1, core_spr1_ok, core_xer_in, core_fast1, core_fast1_ok, core_fast2, core_fast2_ok, core_fasto1, core_fasto2, core_cr_in1, core_cr_in1_ok, core_cr_in2, core_cr_in2_ok, \core_cr_in2$1 , \core_cr_in2_ok$2 , core_cr_out, core_core_msr, core_core_cia, core_core_insn, core_core_insn_type, core_core_fn_unit, core_core_rc, core_core_rc_ok, core_core_oe, core_core_oe_ok, core_core_input_carry, core_core_traptype, \core_core_exc_$signal , \core_core_exc_$signal$3 , \core_core_exc_$signal$4 , \core_core_exc_$signal$5 , \core_core_exc_$signal$6 , \core_core_exc_$signal$7 , \core_core_exc_$signal$8 , \core_core_exc_$signal$9 , core_core_trapaddr, core_core_cr_rd, core_core_cr_rd_ok, core_core_cr_wr, core_core_is_32bit, core_pc, raw_insn_i, bigendian_i, sv_a_nz, \wen$10 , \data_i$11 , ivalid_i, issue_i, state_nia_wen, dmi__addr, dmi__ren, dmi__data_o, full_rd2__ren, full_rd2__data_o, full_rd__ren, full_rd__data_o, issue__addr, issue__ren, issue__data_o, \issue__addr$12 , issue__wen, issue__data_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [6:0] \$1001 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1003 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1006 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1010 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1012 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1019 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [6:0] \$1022 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1024 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1027 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1031 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1033 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1037 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [6:0] \$1040 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1042 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1045 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1049 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1051 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1059 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [6:0] \$1062 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1064 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1067 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1071 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1073 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1079 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [6:0] \$1082 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1084 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1087 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1091 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1093 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1099 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [6:0] \$1102 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1104 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1107 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1111 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1113 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1118 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [6:0] \$1121 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1123 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1126 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1130 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1132 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1136 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [6:0] \$1139 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1141 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1144 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1147 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1149 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [6:0] \$1155 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [64:0] \$1157 ; @@ -36030,127 +36030,127 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire \$1209 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire \$1211 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1213 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1215 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1218 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1221 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1223 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1226 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [7:0] \$1229 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1231 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1233 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1235 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1237 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1239 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1241 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1243 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1246 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1249 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1251 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1254 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [7:0] \$1257 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [255:0] \$1259 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [255:0] \$1261 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1263 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1266 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1269 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1271 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1274 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [7:0] \$1277 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [255:0] \$1279 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [255:0] \$1281 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1283 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1286 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1289 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1291 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1294 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [7:0] \$1297 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [255:0] \$1299 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [255:0] \$1301 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1303 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1306 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1309 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1311 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1314 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [7:0] \$1317 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [255:0] \$1319 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [255:0] \$1321 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1323 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1326 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1329 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1331 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1334 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [7:0] \$1337 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [255:0] \$1339 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [255:0] \$1341 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1343 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1346 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1349 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1351 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1354 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [7:0] \$1357 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) wire [255:0] \$1359 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [255:0] \$1361 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [3:0] \$1363 ; @@ -36174,47 +36174,47 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [255:0] \$1380 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [255:0] \$1382 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1384 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1386 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1388 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1390 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1393 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1396 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1398 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1401 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [1:0] \$1404 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1406 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1409 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1412 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1414 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1417 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [1:0] \$1420 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1422 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1425 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1428 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1430 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1433 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [1:0] \$1436 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [1:0] \$1438 ; @@ -36226,61 +36226,61 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [1:0] \$1443 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [1:0] \$1445 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1448 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1450 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1452 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1454 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1456 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1459 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1462 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1464 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1467 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [2:0] \$1470 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1472 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1475 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1478 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1480 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1483 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [2:0] \$1486 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1488 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1491 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1494 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1496 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1499 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [2:0] \$1502 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1504 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1507 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1510 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1512 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1515 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [2:0] \$1518 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [1:0] \$1520 ; @@ -36294,61 +36294,61 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [2:0] \$1528 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [2:0] \$1530 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1532 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1534 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1536 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1538 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1540 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1543 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1546 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1548 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1551 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire \$1554 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1556 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1559 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1562 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1564 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1567 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire \$1570 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1572 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1575 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1578 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1580 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1583 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire \$1586 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1588 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1591 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1594 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1596 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1599 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire \$1602 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [1:0] \$1604 ; @@ -36366,75 +36366,75 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire \$1615 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire \$1617 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1620 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1622 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1624 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1626 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1628 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1630 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1633 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1637 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1639 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1644 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [2:0] \$1647 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1649 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1652 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1655 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1657 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1660 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [2:0] \$1663 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1665 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1668 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1671 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1673 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1676 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [2:0] \$1679 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1681 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1684 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1687 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1689 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1692 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [2:0] \$1695 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1697 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1700 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1703 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1705 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1708 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [2:0] \$1711 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [63:0] \$1713 ; @@ -36460,33 +36460,33 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire \$1733 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire \$1735 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1737 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1739 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1741 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1744 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1747 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1749 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1752 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire \$1755 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1757 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1760 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1763 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1765 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1768 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire \$1771 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [63:0] \$1773 ; @@ -36494,435 +36494,435 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [2:0] \$1775 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire \$1776 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1779 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1781 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1784 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1787 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1789 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1792 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [1:0] \$1795 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [2:0] \$1797 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1799 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$1801 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$1804 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1807 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1809 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire \$181 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1812 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [9:0] \$1815 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire [13:0] \$182 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire \$185 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire [13:0] \$186 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire \$189 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire [13:0] \$190 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire \$193 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire [13:0] \$194 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire \$197 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire [13:0] \$198 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire \$201 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire [13:0] \$202 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire \$205 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire [13:0] \$206 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire \$209 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire [13:0] \$210 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire \$213 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire [13:0] \$214 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire \$217 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) wire [13:0] \$218 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) wire \$221 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) wire [2:0] \$223 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *) - wire [2:0] \$224 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) + wire [2:0] \$224 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) wire \$226 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) wire [3:0] \$228 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$229 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire [2:0] \$231 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$233 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$235 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$237 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$239 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) wire \$241 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire [2:0] \$243 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$245 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$247 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) wire [5:0] \$250 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) wire [2:0] \$252 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) wire [3:0] \$254 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) wire [2:0] \$256 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$257 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire [2:0] \$259 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$261 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$263 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$265 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$267 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) wire [5:0] \$270 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$271 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire [2:0] \$273 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$275 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$277 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$279 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$281 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) wire \$283 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) wire [2:0] \$285 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) wire \$287 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) wire \$289 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) wire \$291 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire [2:0] \$293 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$295 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$297 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) wire [2:0] \$300 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$301 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire [2:0] \$303 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$305 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$307 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$309 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$311 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) wire [2:0] \$314 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$315 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire [2:0] \$317 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$319 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$321 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$323 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$325 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) wire [4:0] \$328 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$329 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire [2:0] \$331 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$333 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$335 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$337 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$339 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) wire \$341 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire [2:0] \$343 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$345 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$347 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) wire [2:0] \$350 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$352 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$354 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$356 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$358 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$360 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$362 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$364 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$366 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$368 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$370 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$372 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$374 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$376 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$378 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$380 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$382 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$384 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$386 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$388 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$390 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$392 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$394 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$396 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$398 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$400 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$402 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$404 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$406 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$408 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$410 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$412 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$414 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$416 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$418 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$420 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$422 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$424 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$426 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$428 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$430 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$432 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$434 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$436 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$438 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$440 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$442 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$444 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$446 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$448 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$450 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$452 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$454 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$456 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$458 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$460 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$462 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$464 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$466 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$468 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$470 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$472 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$474 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$476 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$478 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$480 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$482 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$484 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$486 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$488 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$490 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$492 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$494 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$496 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$498 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$500 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$502 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$504 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$506 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$508 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$510 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$512 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$514 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$516 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$518 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$520 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$522 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$524 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$526 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$528 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$530 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$532 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$534 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$536 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$538 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$540 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$542 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$544 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$546 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$548 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$550 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$552 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$554 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$556 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$558 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$560 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$562 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$564 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$566 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$568 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$570 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$572 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$574 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$576 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [6:0] \$578 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [6:0] \$580 ; @@ -36962,91 +36962,91 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [6:0] \$613 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [6:0] \$615 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) wire \$617 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$619 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire [2:0] \$621 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$623 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$625 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$627 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$629 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$631 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$633 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$635 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$637 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$639 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire \$641 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$643 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$645 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$647 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$649 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$651 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire \$653 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$655 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$657 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$659 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$661 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$663 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire \$665 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$667 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$669 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$671 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$673 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$675 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire \$677 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$679 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$681 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$683 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$685 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$687 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire \$689 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$691 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$693 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$695 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$697 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$699 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire \$701 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [2:0] \$703 ; @@ -37060,49 +37060,49 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire \$710 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire \$712 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) wire \$715 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire [2:0] \$717 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$719 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$721 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$723 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$725 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$727 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$729 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$731 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [1:0] \$733 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$735 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$737 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$739 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$741 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$743 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [1:0] \$745 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$747 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$749 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$751 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$753 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$755 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [1:0] \$757 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [2:0] \$759 ; @@ -37110,165 +37110,165 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [1:0] \$760 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [1:0] \$762 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) wire \$765 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) wire [2:0] \$767 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) wire \$769 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) wire \$771 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$773 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$775 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$777 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$779 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$781 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [2:0] \$783 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$785 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$787 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$789 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$791 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$793 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [7:0] \$795 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$797 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$799 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$801 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$803 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$805 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) wire [7:0] \$807 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) wire [255:0] \$809 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [255:0] \$811 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$813 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$815 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$817 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$819 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$821 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) wire [7:0] \$823 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) wire [255:0] \$825 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [255:0] \$827 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [255:0] \$829 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [255:0] \$830 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$832 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$834 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$836 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$838 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$840 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) wire [7:0] \$842 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) wire [255:0] \$844 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [255:0] \$846 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$848 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$850 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$852 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$854 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$856 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) wire [7:0] \$858 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) wire [255:0] \$860 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [255:0] \$862 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$864 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$866 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$868 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$870 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$872 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [2:0] \$874 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$876 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$878 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$880 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$882 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$884 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [2:0] \$886 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$888 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$890 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$892 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$894 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$896 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [2:0] \$898 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$900 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$902 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$904 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$906 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$908 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [2:0] \$910 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$912 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$914 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$916 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$918 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$920 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [2:0] \$922 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [2:0] \$924 ; @@ -37278,217 +37278,217 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [2:0] \$928 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [2:0] \$930 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) wire \$932 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$934 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) wire \$936 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$938 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) wire \$940 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) wire \$942 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) wire [9:0] \$944 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) wire \$946 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$948 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$950 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$952 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$954 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$956 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$958 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$960 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$962 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$964 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$966 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) wire \$968 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$970 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$972 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$974 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$980 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire [6:0] \$982 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$984 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wire \$987 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$991 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$993 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$998 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [6:0] addr_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [6:0] \addr_en$1000 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [6:0] \addr_en$1021 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [6:0] \addr_en$1039 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [6:0] \addr_en$1061 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [6:0] \addr_en$1081 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [6:0] \addr_en$1101 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [6:0] \addr_en$1120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [6:0] \addr_en$1138 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [6:0] \addr_en$1154 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [7:0] \addr_en$1228 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [255:0] \addr_en$1256 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [255:0] \addr_en$1276 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [255:0] \addr_en$1296 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [255:0] \addr_en$1316 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [255:0] \addr_en$1336 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [255:0] \addr_en$1356 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [1:0] \addr_en$1403 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [1:0] \addr_en$1419 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [1:0] \addr_en$1435 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [2:0] \addr_en$1469 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [2:0] \addr_en$1485 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [2:0] \addr_en$1501 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [2:0] \addr_en$1517 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire \addr_en$1553 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire \addr_en$1569 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire \addr_en$1585 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire \addr_en$1601 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [2:0] \addr_en$1646 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [2:0] \addr_en$1662 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [2:0] \addr_en$1678 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [2:0] \addr_en$1694 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [2:0] \addr_en$1710 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire \addr_en$1754 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire \addr_en$1770 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [1:0] \addr_en$1794 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) wire [9:0] \addr_en$1814 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [255:0] addr_en_CR_cr_a_branch0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [255:0] addr_en_CR_cr_a_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [255:0] addr_en_CR_cr_b_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [255:0] addr_en_CR_cr_c_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [7:0] addr_en_CR_full_cr_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [2:0] addr_en_FAST_fast1_branch0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [2:0] addr_en_FAST_fast1_branch0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [2:0] addr_en_FAST_fast1_spr0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [2:0] addr_en_FAST_fast1_trap0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [2:0] addr_en_FAST_fast1_trap0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_alu0_10; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_cr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_cr0_11; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_div0_15; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_div0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_ldst0_18; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_ldst0_7; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_ldst0_9; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_logical0_13; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_logical0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_mul0_16; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_mul0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_shiftrot0_17; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_shiftrot0_6; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_shiftrot0_8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_spr0_14; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_trap0_12; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [6:0] addr_en_INT_rabc_trap0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [9:0] addr_en_SPR_spr1_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [1:0] addr_en_XER_xer_ca_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [1:0] addr_en_XER_xer_ca_shiftrot0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [1:0] addr_en_XER_xer_ca_spr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire [2:0] addr_en_XER_xer_ov_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire addr_en_XER_xer_so_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire addr_en_XER_xer_so_div0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire addr_en_XER_xer_so_logical0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire addr_en_XER_xer_so_mul0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire addr_en_XER_xer_so_shiftrot0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) wire addr_en_XER_xer_so_spr0_2; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *) input bigendian_i; @@ -37496,29 +37496,29 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c output [63:0] cia__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] cia__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:44" *) input [63:0] core_core_cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [7:0] core_core_cr_rd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_core_cr_rd_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [7:0] core_core_cr_wr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \core_core_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \core_core_exc_$signal$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \core_core_exc_$signal$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \core_core_exc_$signal$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \core_core_exc_$signal$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \core_core_exc_$signal$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \core_core_exc_$signal$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \core_core_exc_$signal$9 ; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -37535,15 +37535,15 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:49" *) input [13:0] core_core_fn_unit; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) input [1:0] core_core_input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) input [31:0] core_core_insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -37620,67 +37620,67 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:48" *) input [6:0] core_core_insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) input core_core_is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:43" *) input [63:0] core_core_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_core_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_core_oe_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_core_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_core_rc_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) input [12:0] core_core_trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:54" *) input [7:0] core_core_traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [6:0] core_cr_in1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_cr_in1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [6:0] core_cr_in2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [6:0] \core_cr_in2$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_cr_in2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input \core_cr_in2_ok$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [6:0] core_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [6:0] core_ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [2:0] core_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [2:0] core_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [2:0] core_fasto1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [2:0] core_fasto2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) input [63:0] core_pc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [6:0] core_reg1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_reg1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [6:0] core_reg2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_reg2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [6:0] core_reg3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_reg3_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [6:0] core_rego; (* enum_base_type = "SPR" *) (* enum_value_0000010010 = "DSISR" *) @@ -37694,9 +37694,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1011000000 = "SVSTATE" *) (* enum_value_1011010000 = "PRTBL" *) (* enum_value_1011010001 = "SVSRR0" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [9:0] core_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input core_spr1_ok; (* enum_base_type = "SPR" *) (* enum_value_0000010010 = "DSISR" *) @@ -37710,25 +37710,25 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1011000000 = "SVSTATE" *) (* enum_value_1011010000 = "PRTBL" *) (* enum_value_1011010001 = "SVSRR0" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [9:0] core_spro; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) output core_terminate_o; reg core_terminate_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) reg \core_terminate_o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:111" *) input [2:0] core_xer_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *) output corebusy_o; reg corebusy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" *) reg [1:0] counter = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" *) reg [1:0] \counter$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [3:0] cr_data_i; @@ -37914,11 +37914,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire dec_ALU_ALU__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire dec_ALU_ALU__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) wire dec_ALU_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) wire [31:0] dec_ALU_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) wire dec_ALU_sv_a_nz; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [63:0] dec_BRANCH_BRANCH__cia; @@ -38026,9 +38026,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire dec_BRANCH_BRANCH__is_32bit; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire dec_BRANCH_BRANCH__lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) wire dec_BRANCH_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) wire [31:0] dec_BRANCH_raw_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -38126,9 +38126,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001100 = "OP_SETVL" *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [6:0] dec_CR_CR__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) wire dec_CR_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) wire [31:0] dec_CR_raw_opcode_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [3:0] dec_DIV_DIV__data_len; @@ -38260,11 +38260,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire dec_DIV_DIV__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire dec_DIV_DIV__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) wire dec_DIV_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) wire [31:0] dec_DIV_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) wire dec_DIV_sv_a_nz; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire dec_LDST_LDST__byte_reverse; @@ -38393,11 +38393,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire dec_LDST_LDST__sign_extend; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire dec_LDST_LDST__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) wire dec_LDST_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) wire [31:0] dec_LDST_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) wire dec_LDST_sv_a_nz; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [3:0] dec_LOGICAL_LOGICAL__data_len; @@ -38529,11 +38529,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire dec_LOGICAL_LOGICAL__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire dec_LOGICAL_LOGICAL__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) wire dec_LOGICAL_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) wire [31:0] dec_LOGICAL_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) wire dec_LOGICAL_sv_a_nz; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -38649,9 +38649,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire dec_MUL_MUL__rc__rc; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire dec_MUL_MUL__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) wire dec_MUL_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) wire [31:0] dec_MUL_raw_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -38781,9 +38781,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire dec_SHIFT_ROT_SHIFT_ROT__rc__rc; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire dec_SHIFT_ROT_SHIFT_ROT__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) wire dec_SHIFT_ROT_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) wire [31:0] dec_SHIFT_ROT_raw_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -38883,9 +38883,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [6:0] dec_SPR_SPR__insn_type; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire dec_SPR_SPR__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) wire dec_SPR_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) wire [31:0] dec_SPR_raw_opcode_in; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [4:0] dmi__addr; @@ -38893,187 +38893,187 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c output [63:0] dmi__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input dmi__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_CR_cr_a_branch0_1 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_CR_cr_a_branch0_1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_CR_cr_a_cr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_CR_cr_a_cr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_CR_cr_b_cr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_CR_cr_b_cr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_CR_cr_c_cr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_CR_cr_c_cr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_CR_full_cr_cr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_CR_full_cr_cr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_FAST_fast1_branch0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_FAST_fast1_branch0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_FAST_fast1_branch0_3 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_FAST_fast1_branch0_3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_FAST_fast1_spr0_2 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_FAST_fast1_spr0_2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_FAST_fast1_trap0_1 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_FAST_fast1_trap0_1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_FAST_fast1_trap0_4 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_FAST_fast1_trap0_4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_alu0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_alu0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_alu0_10 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_alu0_10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_cr0_1 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_cr0_1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_cr0_11 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_cr0_11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_div0_15 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_div0_15$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_div0_4 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_div0_4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_ldst0_18 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_ldst0_18$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_ldst0_7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_ldst0_7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_ldst0_9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_ldst0_9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_logical0_13 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_logical0_13$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_logical0_3 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_logical0_3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_mul0_16 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_mul0_16$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_mul0_5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_mul0_5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_shiftrot0_17 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_shiftrot0_17$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_shiftrot0_6 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_shiftrot0_6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_shiftrot0_8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_shiftrot0_8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_spr0_14 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_spr0_14$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_trap0_12 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_trap0_12$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_INT_rabc_trap0_2 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_INT_rabc_trap0_2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_SPR_spr1_spr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_SPR_spr1_spr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_XER_xer_ca_alu0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_XER_xer_ca_alu0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_XER_xer_ca_shiftrot0_2 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_XER_xer_ca_shiftrot0_2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_XER_xer_ca_spr0_1 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_XER_xer_ca_spr0_1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_XER_xer_ov_spr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_XER_xer_ov_spr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_XER_xer_so_alu0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_XER_xer_so_alu0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_XER_xer_so_div0_3 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_XER_xer_so_div0_3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_XER_xer_so_logical0_1 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_XER_xer_so_logical0_1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_XER_xer_so_mul0_4 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_XER_xer_so_mul0_4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_XER_xer_so_shiftrot0_5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_XER_xer_so_shiftrot0_5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg dp_XER_xer_so_spr0_2 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) reg \dp_XER_xer_so_spr0_2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire ea_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) wire en_alu0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) wire en_branch0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) wire en_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) wire en_div0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) wire en_ldst0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) wire en_logical0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) wire en_mul0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) wire en_shiftrot0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) wire en_spr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) wire en_trap0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [2:0] fast_dest1__addr; @@ -39087,7 +39087,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [63:0] fast_src1__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire fast_src1__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" *) wire [9:0] fu_enable; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [31:0] full_rd2__data_o; @@ -39097,17 +39097,17 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c output [5:0] full_rd__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] full_rd__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_cr_a_ok$122 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_cr_a_ok$123 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_cr_a_ok$124 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_cr_a_ok$125 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_cr_a_ok$126 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) wire fus_cu_busy_o; @@ -39319,23 +39319,23 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [63:0] \fus_dest5_o$161 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [1:0] fus_dest6_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] fus_ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_fast1_ok$150 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_fast1_ok$151 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_fast2_ok$152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_full_cr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [95:0] fus_ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_ldst_port0_addr_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) wire fus_ldst_port0_addr_ok_o; @@ -39343,57 +39343,57 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire fus_ldst_port0_busy_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) wire [3:0] fus_ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \fus_ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \fus_ldst_port0_exc_$signal$163 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \fus_ldst_port0_exc_$signal$164 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \fus_ldst_port0_exc_$signal$165 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \fus_ldst_port0_exc_$signal$166 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \fus_ldst_port0_exc_$signal$167 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \fus_ldst_port0_exc_$signal$168 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \fus_ldst_port0_exc_$signal$169 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) wire fus_ldst_port0_is_ld_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) wire fus_ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] fus_ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] fus_ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_ldst_port0_st_data_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_msr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_nia_ok$158 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] fus_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_o_ok$101 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_o_ok$104 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_o_ok$107 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_o_ok$110 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_o_ok$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_o_ok$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_o_ok$98 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg [3:0] fus_oper_i_alu_alu0__data_len; @@ -40562,7 +40562,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c reg fus_oper_i_ldst_ldst0__sign_extend; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg fus_oper_i_ldst_ldst0__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_spr1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) reg [63:0] fus_src1_i; @@ -40644,27 +40644,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c reg [1:0] fus_src6_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) reg [3:0] \fus_src6_i$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_xer_ca_ok$132 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_xer_ca_ok$133 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_xer_ov_ok$136 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_xer_ov_ok$137 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_xer_ov_ok$138 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire fus_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_xer_so_ok$141 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_xer_so_ok$142 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fus_xer_so_ok$143 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [4:0] int_dest1__addr; @@ -40698,115 +40698,115 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c output [63:0] msr__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] msr__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_CR_cr_a_branch0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_CR_cr_a_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_CR_cr_b_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_CR_cr_c_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_CR_full_cr_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_FAST_fast1_branch0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_FAST_fast1_branch0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_FAST_fast1_spr0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_FAST_fast1_trap0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_FAST_fast1_trap0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_alu0_10; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_cr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_cr0_11; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_div0_15; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_div0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_ldst0_18; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_ldst0_7; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_ldst0_9; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_logical0_13; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_logical0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_mul0_16; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_mul0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_shiftrot0_17; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_shiftrot0_6; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_shiftrot0_8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_spr0_14; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_trap0_12; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_INT_rabc_trap0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_SPR_spr1_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_XER_xer_ca_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_XER_xer_ca_shiftrot0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_XER_xer_ca_spr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_XER_xer_ov_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_XER_xer_so_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_XER_xer_so_div0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_XER_xer_so_logical0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_XER_xer_so_mul0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_XER_xer_so_shiftrot0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) wire pick_XER_xer_so_spr0_2; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *) input [31:0] raw_insn_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_CR_cr_a_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_CR_cr_b_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_CR_cr_c_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_CR_full_cr_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_FAST_fast1_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_FAST_fast1_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_INT_rabc_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_INT_rabc_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_INT_rabc_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_SPR_spr1_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_XER_xer_ca_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_XER_xer_ov_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) wire rdflag_XER_xer_so_0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire rdpick_CR_cr_a_en_o; @@ -40868,85 +40868,85 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [5:0] rdpick_XER_xer_so_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) wire [5:0] rdpick_XER_xer_so_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_CR_cr_a_branch0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_CR_cr_a_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_CR_cr_b_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_CR_cr_c_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_CR_full_cr_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_FAST_fast1_branch0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_FAST_fast1_branch0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_FAST_fast1_spr0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_FAST_fast1_trap0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_FAST_fast1_trap0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_alu0_10; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_cr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_cr0_11; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_div0_15; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_div0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_ldst0_18; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_ldst0_7; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_ldst0_9; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_logical0_13; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_logical0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_mul0_16; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_mul0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_shiftrot0_17; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_shiftrot0_6; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_shiftrot0_8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_spr0_14; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_trap0_12; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_INT_rabc_trap0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_SPR_spr1_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_XER_xer_ca_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_XER_xer_ca_shiftrot0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_XER_xer_ca_spr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_XER_xer_ov_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_XER_xer_so_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_XER_xer_so_div0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_XER_xer_so_logical0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_XER_xer_so_mul0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_XER_xer_so_shiftrot0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) wire rp_XER_xer_so_spr0_2; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [3:0] spr_spr1__addr; @@ -40974,15 +40974,15 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c input [2:0] sv__ren; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *) input sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) wire \sv_a_nz$176 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) wire \sv_a_nz$177 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) wire \sv_a_nz$178 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) wire \sv_a_nz$179 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) wire \sv_a_nz$180 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) input wb_dcache_en; @@ -40990,153 +40990,153 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c input [2:0] wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] \wen$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire wp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1018 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1036 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1058 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1078 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1098 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1117 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1135 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1151 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1225 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1253 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1273 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1293 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1313 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1333 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1353 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1400 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1416 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1432 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1466 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1482 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1498 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1514 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1550 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1566 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1582 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1598 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1643 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1659 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1675 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1691 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1707 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1751 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1767 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1791 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$1811 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) wire \wp$997 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire wr_pick; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1005 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1026 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1044 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1066 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1086 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1106 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1125 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1143 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1217 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1245 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1265 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1285 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1305 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1325 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1345 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1392 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1408 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1424 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1458 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1474 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1490 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1506 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1542 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1558 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1574 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1590 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1632 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1651 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1667 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1683 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1699 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1743 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1759 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1783 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$1803 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) wire \wr_pick$986 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg wr_pick_dly = 1'h0; @@ -41360,79 +41360,79 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire \wr_pick_rise$995 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire \wr_pick_rise$996 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_alu0_cr_a_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_alu0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_alu0_xer_ca_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_alu0_xer_ov_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_alu0_xer_so_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_branch0_fast1_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_branch0_fast1_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_branch0_nia_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_cr0_cr_a_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_cr0_full_cr_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_cr0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_div0_cr_a_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_div0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_div0_xer_ov_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_div0_xer_so_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_ldst0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_ldst0_o_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_logical0_cr_a_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_logical0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_mul0_cr_a_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_mul0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_mul0_xer_ov_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_mul0_xer_so_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_shiftrot0_cr_a_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_shiftrot0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_shiftrot0_xer_ca_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_spr0_fast1_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_spr0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_spr0_spr1_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_spr0_xer_ca_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_spr0_xer_ov_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_spr0_xer_so_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_trap0_fast1_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_trap0_fast1_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_trap0_msr_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_trap0_nia_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) wire wrflag_trap0_o_0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire wrpick_CR_cr_a_en_o; @@ -41518,55 +41518,55 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [2:0] \xer_wen$171 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [2:0] \xer_wen$173 ; - assign \$1001 = \wp$997 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; - assign \$1003 = \fus_o_ok$95 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ; - assign \$1006 = wrpick_INT_o_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1001 = \wp$997 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; + assign \$1003 = \fus_o_ok$95 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ; + assign \$1006 = wrpick_INT_o_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; assign \$1010 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1008 ; assign \$1012 = \wr_pick$1005 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1010 ; - assign \$1019 = \wr_pick$1005 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; - assign \$1022 = \wp$1018 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; - assign \$1024 = \fus_o_ok$98 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$23 ; - assign \$1027 = wrpick_INT_o_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1019 = \wr_pick$1005 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; + assign \$1022 = \wp$1018 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; + assign \$1024 = \fus_o_ok$98 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$23 ; + assign \$1027 = wrpick_INT_o_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; assign \$1031 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1029 ; assign \$1033 = \wr_pick$1026 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1031 ; - assign \$1037 = \wr_pick$1026 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; - assign \$1040 = \wp$1036 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; - assign \$1042 = \fus_o_ok$101 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; - assign \$1045 = wrpick_INT_o_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1037 = \wr_pick$1026 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; + assign \$1040 = \wp$1036 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; + assign \$1042 = \fus_o_ok$101 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; + assign \$1045 = wrpick_INT_o_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; assign \$1049 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1047 ; assign \$1051 = \wr_pick$1044 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1049 ; - assign \$1059 = \wr_pick$1044 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; - assign \$1062 = \wp$1058 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; - assign \$1064 = \fus_o_ok$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ; - assign \$1067 = wrpick_INT_o_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1059 = \wr_pick$1044 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; + assign \$1062 = \wp$1058 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; + assign \$1064 = \fus_o_ok$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ; + assign \$1067 = wrpick_INT_o_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; assign \$1071 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1069 ; assign \$1073 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1071 ; - assign \$1079 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; - assign \$1082 = \wp$1078 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; - assign \$1084 = \fus_o_ok$107 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ; - assign \$1087 = wrpick_INT_o_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1079 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; + assign \$1082 = \wp$1078 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; + assign \$1084 = \fus_o_ok$107 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ; + assign \$1087 = wrpick_INT_o_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; assign \$1091 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1089 ; assign \$1093 = \wr_pick$1086 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1091 ; - assign \$1099 = \wr_pick$1086 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; - assign \$1102 = \wp$1098 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; - assign \$1104 = \fus_o_ok$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ; - assign \$1107 = wrpick_INT_o_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1099 = \wr_pick$1086 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; + assign \$1102 = \wp$1098 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; + assign \$1104 = \fus_o_ok$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$35 ; + assign \$1107 = wrpick_INT_o_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; assign \$1111 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1109 ; assign \$1113 = \wr_pick$1106 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1111 ; - assign \$1118 = \wr_pick$1106 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; - assign \$1121 = \wp$1117 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; - assign \$1123 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$38 ; - assign \$1126 = wrpick_INT_o_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1118 = \wr_pick$1106 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; + assign \$1121 = \wp$1117 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; + assign \$1123 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$38 ; + assign \$1126 = wrpick_INT_o_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; assign \$1130 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1128 ; assign \$1132 = \wr_pick$1125 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1130 ; - assign \$1136 = \wr_pick$1125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; - assign \$1139 = \wp$1135 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; - assign \$1141 = ea_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$38 ; - assign \$1144 = wrpick_INT_o_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1136 = \wr_pick$1125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; + assign \$1139 = \wp$1135 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; + assign \$1141 = ea_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$38 ; + assign \$1144 = wrpick_INT_o_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; assign \$1147 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1146 ; assign \$1149 = \wr_pick$1143 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1147 ; - assign \$1152 = \wr_pick$1143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; - assign \$1155 = \wp$1151 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_ea : 7'h00; + assign \$1152 = \wr_pick$1143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; + assign \$1155 = \wp$1151 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_ea : 7'h00; assign \$1158 = fus_dest1_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$115 ; assign \$1160 = \fus_dest1_o$117 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$118 ; assign \$1162 = \fus_dest1_o$116 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1160 ; @@ -41594,67 +41594,67 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c assign \$1207 = \wp$1117 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1205 ; assign \$1209 = \$1203 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1207 ; assign \$1211 = \$1201 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1209 ; - assign \$1213 = fus_full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ; - assign \$1215 = \fus_cu_wr__rel_o$93 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1]; - assign \$1218 = wrpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_full_cr_en_o; + assign \$1213 = fus_full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$14 ; + assign \$1215 = \fus_cu_wr__rel_o$93 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[1]; + assign \$1218 = wrpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_full_cr_en_o; assign \$1221 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1220 ; assign \$1223 = \wr_pick$1217 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1221 ; - assign \$1226 = \wr_pick$1217 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_full_cr_en_o; - assign \$1229 = \wp$1225 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_core_cr_wr : 8'h00; - assign \$1231 = fus_cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o; - assign \$1233 = fus_cu_wr__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0]; - assign \$1235 = \fus_cu_wr__rel_o$93 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1]; - assign \$1237 = \fus_cu_wr__rel_o$99 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[4]; - assign \$1239 = \fus_cu_wr__rel_o$105 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6]; - assign \$1241 = \fus_cu_wr__rel_o$108 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7]; - assign \$1243 = \fus_cu_wr__rel_o$111 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8]; - assign \$1246 = wrpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1226 = \wr_pick$1217 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_full_cr_en_o; + assign \$1229 = \wp$1225 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_core_cr_wr : 8'h00; + assign \$1231 = fus_cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o; + assign \$1233 = fus_cu_wr__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0]; + assign \$1235 = \fus_cu_wr__rel_o$93 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[1]; + assign \$1237 = \fus_cu_wr__rel_o$99 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[4]; + assign \$1239 = \fus_cu_wr__rel_o$105 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6]; + assign \$1241 = \fus_cu_wr__rel_o$108 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7]; + assign \$1243 = \fus_cu_wr__rel_o$111 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[8]; + assign \$1246 = wrpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; assign \$1249 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1248 ; assign \$1251 = \wr_pick$1245 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1249 ; - assign \$1254 = \wr_pick$1245 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; - assign \$1257 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1259 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1257 ; - assign \$1261 = \wp$1253 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1259 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1263 = \fus_cr_a_ok$122 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ; - assign \$1266 = wrpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1254 = \wr_pick$1245 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; + assign \$1257 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1259 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) \$1257 ; + assign \$1261 = \wp$1253 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1259 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1263 = \fus_cr_a_ok$122 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$14 ; + assign \$1266 = wrpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; assign \$1269 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1268 ; assign \$1271 = \wr_pick$1265 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1269 ; - assign \$1274 = \wr_pick$1265 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; - assign \$1277 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1279 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1277 ; - assign \$1281 = \wp$1273 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1279 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1283 = \fus_cr_a_ok$123 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$23 ; - assign \$1286 = wrpick_CR_cr_a_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1274 = \wr_pick$1265 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; + assign \$1277 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1279 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) \$1277 ; + assign \$1281 = \wp$1273 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1279 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1283 = \fus_cr_a_ok$123 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$23 ; + assign \$1286 = wrpick_CR_cr_a_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; assign \$1289 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1288 ; assign \$1291 = \wr_pick$1285 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1289 ; - assign \$1294 = \wr_pick$1285 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; - assign \$1297 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1299 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1297 ; - assign \$1301 = \wp$1293 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1299 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1303 = \fus_cr_a_ok$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ; - assign \$1306 = wrpick_CR_cr_a_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1294 = \wr_pick$1285 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; + assign \$1297 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1299 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) \$1297 ; + assign \$1301 = \wp$1293 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1299 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1303 = \fus_cr_a_ok$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ; + assign \$1306 = wrpick_CR_cr_a_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; assign \$1309 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1308 ; assign \$1311 = \wr_pick$1305 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1309 ; - assign \$1314 = \wr_pick$1305 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; - assign \$1317 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1319 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1317 ; - assign \$1321 = \wp$1313 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1319 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1323 = \fus_cr_a_ok$125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ; - assign \$1326 = wrpick_CR_cr_a_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1314 = \wr_pick$1305 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; + assign \$1317 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1319 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) \$1317 ; + assign \$1321 = \wp$1313 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1319 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1323 = \fus_cr_a_ok$125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ; + assign \$1326 = wrpick_CR_cr_a_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; assign \$1329 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1328 ; assign \$1331 = \wr_pick$1325 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1329 ; - assign \$1334 = \wr_pick$1325 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; - assign \$1337 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1339 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1337 ; - assign \$1341 = \wp$1333 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1339 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1343 = \fus_cr_a_ok$126 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ; - assign \$1346 = wrpick_CR_cr_a_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1334 = \wr_pick$1325 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; + assign \$1337 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1339 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) \$1337 ; + assign \$1341 = \wp$1333 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1339 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1343 = \fus_cr_a_ok$126 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$35 ; + assign \$1346 = wrpick_CR_cr_a_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; assign \$1349 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1348 ; assign \$1351 = \wr_pick$1345 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1349 ; - assign \$1354 = \wr_pick$1345 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; - assign \$1357 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1359 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1357 ; - assign \$1361 = \wp$1353 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1359 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1354 = \wr_pick$1345 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; + assign \$1357 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1359 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:140" *) \$1357 ; + assign \$1361 = \wp$1353 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1359 : 256'h0000000000000000000000000000000000000000000000000000000000000000; assign \$1363 = fus_dest3_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$128 ; assign \$1365 = \fus_dest2_o$127 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1363 ; assign \$1367 = \fus_dest2_o$130 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$131 ; @@ -41665,94 +41665,94 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c assign \$1378 = \addr_en$1336 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1356 ; assign \$1380 = \addr_en$1316 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1378 ; assign \$1382 = \$1376 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1380 ; - assign \$1384 = fus_xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o; - assign \$1386 = fus_cu_wr__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0]; - assign \$1388 = \fus_cu_wr__rel_o$102 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; - assign \$1390 = \fus_cu_wr__rel_o$111 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8]; - assign \$1393 = wrpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o; + assign \$1384 = fus_xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o; + assign \$1386 = fus_cu_wr__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0]; + assign \$1388 = \fus_cu_wr__rel_o$102 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; + assign \$1390 = \fus_cu_wr__rel_o$111 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[8]; + assign \$1393 = wrpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ca_en_o; assign \$1396 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1395 ; assign \$1398 = \wr_pick$1392 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1396 ; - assign \$1401 = \wr_pick$1392 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o; - assign \$1404 = \wp$1400 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0; - assign \$1406 = \fus_xer_ca_ok$132 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; - assign \$1409 = wrpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o; + assign \$1401 = \wr_pick$1392 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ca_en_o; + assign \$1404 = \wp$1400 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0; + assign \$1406 = \fus_xer_ca_ok$132 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; + assign \$1409 = wrpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ca_en_o; assign \$1412 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1411 ; assign \$1414 = \wr_pick$1408 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1412 ; - assign \$1417 = \wr_pick$1408 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o; - assign \$1420 = \wp$1416 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0; - assign \$1422 = \fus_xer_ca_ok$133 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ; - assign \$1425 = wrpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o; + assign \$1417 = \wr_pick$1408 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ca_en_o; + assign \$1420 = \wp$1416 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0; + assign \$1422 = \fus_xer_ca_ok$133 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$35 ; + assign \$1425 = wrpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ca_en_o; assign \$1428 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1427 ; assign \$1430 = \wr_pick$1424 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1428 ; - assign \$1433 = \wr_pick$1424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o; - assign \$1436 = \wp$1432 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0; + assign \$1433 = \wr_pick$1424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ca_en_o; + assign \$1436 = \wp$1432 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0; assign \$1438 = fus_dest6_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$135 ; assign \$1440 = \fus_dest3_o$134 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1438 ; assign \$1443 = \addr_en$1419 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1435 ; assign \$1445 = \addr_en$1403 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1443 ; assign \$1442 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1445 ; - assign \$1448 = fus_xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o; - assign \$1450 = fus_cu_wr__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0]; - assign \$1452 = \fus_cu_wr__rel_o$102 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; - assign \$1454 = \fus_cu_wr__rel_o$105 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6]; - assign \$1456 = \fus_cu_wr__rel_o$108 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7]; - assign \$1459 = wrpick_XER_xer_ov_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o; + assign \$1448 = fus_xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o; + assign \$1450 = fus_cu_wr__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0]; + assign \$1452 = \fus_cu_wr__rel_o$102 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; + assign \$1454 = \fus_cu_wr__rel_o$105 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6]; + assign \$1456 = \fus_cu_wr__rel_o$108 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7]; + assign \$1459 = wrpick_XER_xer_ov_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o; assign \$1462 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1461 ; assign \$1464 = \wr_pick$1458 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1462 ; - assign \$1467 = \wr_pick$1458 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o; - assign \$1470 = \wp$1466 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0; - assign \$1472 = \fus_xer_ov_ok$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; - assign \$1475 = wrpick_XER_xer_ov_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o; + assign \$1467 = \wr_pick$1458 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o; + assign \$1470 = \wp$1466 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0; + assign \$1472 = \fus_xer_ov_ok$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; + assign \$1475 = wrpick_XER_xer_ov_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o; assign \$1478 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1477 ; assign \$1480 = \wr_pick$1474 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1478 ; - assign \$1483 = \wr_pick$1474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o; - assign \$1486 = \wp$1482 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0; - assign \$1488 = \fus_xer_ov_ok$137 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ; - assign \$1491 = wrpick_XER_xer_ov_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o; + assign \$1483 = \wr_pick$1474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o; + assign \$1486 = \wp$1482 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0; + assign \$1488 = \fus_xer_ov_ok$137 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ; + assign \$1491 = wrpick_XER_xer_ov_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o; assign \$1494 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1493 ; assign \$1496 = \wr_pick$1490 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1494 ; - assign \$1499 = \wr_pick$1490 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o; - assign \$1502 = \wp$1498 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0; - assign \$1504 = \fus_xer_ov_ok$138 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ; - assign \$1507 = wrpick_XER_xer_ov_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o; + assign \$1499 = \wr_pick$1490 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o; + assign \$1502 = \wp$1498 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0; + assign \$1504 = \fus_xer_ov_ok$138 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ; + assign \$1507 = wrpick_XER_xer_ov_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o; assign \$1510 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1509 ; assign \$1512 = \wr_pick$1506 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1510 ; - assign \$1515 = \wr_pick$1506 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o; - assign \$1518 = \wp$1514 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0; + assign \$1515 = \wr_pick$1506 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o; + assign \$1518 = \wp$1514 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0; assign \$1520 = fus_dest4_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) fus_dest5_o; assign \$1522 = \fus_dest3_o$139 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$140 ; assign \$1524 = \$1520 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1522 ; assign \$1526 = \addr_en$1469 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1485 ; assign \$1528 = \addr_en$1501 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1517 ; assign \$1530 = \$1526 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1528 ; - assign \$1532 = fus_xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o; - assign \$1534 = fus_cu_wr__rel_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0]; - assign \$1536 = \fus_cu_wr__rel_o$102 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; - assign \$1538 = \fus_cu_wr__rel_o$105 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6]; - assign \$1540 = \fus_cu_wr__rel_o$108 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7]; - assign \$1543 = wrpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o; + assign \$1532 = fus_xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o; + assign \$1534 = fus_cu_wr__rel_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0]; + assign \$1536 = \fus_cu_wr__rel_o$102 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; + assign \$1538 = \fus_cu_wr__rel_o$105 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6]; + assign \$1540 = \fus_cu_wr__rel_o$108 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7]; + assign \$1543 = wrpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o; assign \$1546 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1545 ; assign \$1548 = \wr_pick$1542 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1546 ; - assign \$1551 = \wr_pick$1542 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o; - assign \$1554 = \wp$1550 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; - assign \$1556 = \fus_xer_so_ok$141 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; - assign \$1559 = wrpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o; + assign \$1551 = \wr_pick$1542 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o; + assign \$1554 = \wp$1550 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; + assign \$1556 = \fus_xer_so_ok$141 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; + assign \$1559 = wrpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o; assign \$1562 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1561 ; assign \$1564 = \wr_pick$1558 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1562 ; - assign \$1567 = \wr_pick$1558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o; - assign \$1570 = \wp$1566 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; - assign \$1572 = \fus_xer_so_ok$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ; - assign \$1575 = wrpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o; + assign \$1567 = \wr_pick$1558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o; + assign \$1570 = \wp$1566 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; + assign \$1572 = \fus_xer_so_ok$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ; + assign \$1575 = wrpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o; assign \$1578 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1577 ; assign \$1580 = \wr_pick$1574 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1578 ; - assign \$1583 = \wr_pick$1574 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o; - assign \$1586 = \wp$1582 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; - assign \$1588 = \fus_xer_so_ok$143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ; - assign \$1591 = wrpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o; + assign \$1583 = \wr_pick$1574 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o; + assign \$1586 = \wp$1582 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; + assign \$1588 = \fus_xer_so_ok$143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ; + assign \$1591 = wrpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o; assign \$1594 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1593 ; assign \$1596 = \wr_pick$1590 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1594 ; - assign \$1599 = \wr_pick$1590 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o; - assign \$1602 = \wp$1598 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; + assign \$1599 = \wr_pick$1590 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o; + assign \$1602 = \wp$1598 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; assign \$1605 = \fus_dest5_o$144 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$145 ; assign \$1607 = \fus_dest4_o$146 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$147 ; assign \$1609 = \$1605 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1607 ; @@ -41761,41 +41761,41 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c assign \$1615 = \addr_en$1585 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1601 ; assign \$1617 = \$1613 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1615 ; assign \$1612 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1617 ; - assign \$1620 = fus_fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ; - assign \$1622 = \fus_cu_wr__rel_o$148 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2]; - assign \$1624 = \fus_cu_wr__rel_o$96 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3]; - assign \$1626 = \fus_cu_wr__rel_o$102 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; - assign \$1628 = \fus_cu_wr__rel_o$148 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2]; - assign \$1630 = \fus_cu_wr__rel_o$96 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3]; - assign \$1633 = wrpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o; + assign \$1620 = fus_fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$17 ; + assign \$1622 = \fus_cu_wr__rel_o$148 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[2]; + assign \$1624 = \fus_cu_wr__rel_o$96 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3]; + assign \$1626 = \fus_cu_wr__rel_o$102 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; + assign \$1628 = \fus_cu_wr__rel_o$148 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[2]; + assign \$1630 = \fus_cu_wr__rel_o$96 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3]; + assign \$1633 = wrpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o; assign \$1637 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1635 ; assign \$1639 = \wr_pick$1632 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1637 ; - assign \$1644 = \wr_pick$1632 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o; - assign \$1647 = \wp$1643 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0; - assign \$1649 = \fus_fast1_ok$150 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ; - assign \$1652 = wrpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o; + assign \$1644 = \wr_pick$1632 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o; + assign \$1647 = \wp$1643 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto1 : 3'h0; + assign \$1649 = \fus_fast1_ok$150 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ; + assign \$1652 = wrpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o; assign \$1655 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1654 ; assign \$1657 = \wr_pick$1651 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1655 ; - assign \$1660 = \wr_pick$1651 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o; - assign \$1663 = \wp$1659 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0; - assign \$1665 = \fus_fast1_ok$151 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; - assign \$1668 = wrpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o; + assign \$1660 = \wr_pick$1651 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o; + assign \$1663 = \wp$1659 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto1 : 3'h0; + assign \$1665 = \fus_fast1_ok$151 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; + assign \$1668 = wrpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o; assign \$1671 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1670 ; assign \$1673 = \wr_pick$1667 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1671 ; - assign \$1676 = \wr_pick$1667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o; - assign \$1679 = \wp$1675 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0; - assign \$1681 = fus_fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ; - assign \$1684 = wrpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o; + assign \$1676 = \wr_pick$1667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o; + assign \$1679 = \wp$1675 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto1 : 3'h0; + assign \$1681 = fus_fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$17 ; + assign \$1684 = wrpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o; assign \$1687 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1686 ; assign \$1689 = \wr_pick$1683 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1687 ; - assign \$1692 = \wr_pick$1683 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o; - assign \$1695 = \wp$1691 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto2 : 3'h0; - assign \$1697 = \fus_fast2_ok$152 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ; - assign \$1700 = wrpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o; + assign \$1692 = \wr_pick$1683 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o; + assign \$1695 = \wp$1691 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto2 : 3'h0; + assign \$1697 = \fus_fast2_ok$152 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ; + assign \$1700 = wrpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o; assign \$1703 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1702 ; assign \$1705 = \wr_pick$1699 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1703 ; - assign \$1708 = \wr_pick$1699 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o; - assign \$1711 = \wp$1707 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto2 : 3'h0; + assign \$1708 = \wr_pick$1699 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o; + assign \$1711 = \wp$1707 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto2 : 3'h0; assign \$1713 = \fus_dest1_o$153 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$154 ; assign \$1715 = \fus_dest2_o$156 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$157 ; assign \$1717 = \fus_dest3_o$155 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1715 ; @@ -41808,237 +41808,237 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c assign \$1731 = \wp$1691 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1707 ; assign \$1733 = \wp$1675 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1731 ; assign \$1735 = \$1729 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1733 ; - assign \$1737 = fus_nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ; - assign \$1739 = \fus_cu_wr__rel_o$148 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2]; - assign \$1741 = \fus_cu_wr__rel_o$96 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3]; - assign \$1744 = wrpick_STATE_nia_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_nia_en_o; + assign \$1737 = fus_nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$17 ; + assign \$1739 = \fus_cu_wr__rel_o$148 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[2]; + assign \$1741 = \fus_cu_wr__rel_o$96 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3]; + assign \$1744 = wrpick_STATE_nia_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_STATE_nia_en_o; assign \$1747 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1746 ; assign \$1749 = \wr_pick$1743 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1747 ; - assign \$1752 = \wr_pick$1743 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_nia_en_o; - assign \$1755 = \wp$1751 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; - assign \$1757 = \fus_nia_ok$158 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ; - assign \$1760 = wrpick_STATE_nia_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_nia_en_o; + assign \$1752 = \wr_pick$1743 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_STATE_nia_en_o; + assign \$1755 = \wp$1751 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; + assign \$1757 = \fus_nia_ok$158 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ; + assign \$1760 = wrpick_STATE_nia_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_STATE_nia_en_o; assign \$1763 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1762 ; assign \$1765 = \wr_pick$1759 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1763 ; - assign \$1768 = \wr_pick$1759 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_nia_en_o; - assign \$1771 = \wp$1767 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; + assign \$1768 = \wr_pick$1759 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_STATE_nia_en_o; + assign \$1771 = \wp$1767 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; assign \$1773 = \fus_dest3_o$159 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$160 ; assign \$1776 = \addr_en$1754 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1770 ; assign \$1775 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \$1776 ; - assign \$1779 = fus_msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ; - assign \$1781 = \fus_cu_wr__rel_o$96 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3]; - assign \$1784 = wrpick_STATE_msr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_msr_en_o; + assign \$1779 = fus_msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ; + assign \$1781 = \fus_cu_wr__rel_o$96 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3]; + assign \$1784 = wrpick_STATE_msr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_STATE_msr_en_o; assign \$1787 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1786 ; assign \$1789 = \wr_pick$1783 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1787 ; - assign \$1792 = \wr_pick$1783 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_msr_en_o; - assign \$1795 = \wp$1791 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0; - assign \$1797 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) \addr_en$1794 ; - assign \$1799 = fus_spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; - assign \$1801 = \fus_cu_wr__rel_o$102 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; - assign \$1804 = wrpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_SPR_spr1_en_o; + assign \$1792 = \wr_pick$1783 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_STATE_msr_en_o; + assign \$1795 = \wp$1791 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0; + assign \$1797 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) \addr_en$1794 ; + assign \$1799 = fus_spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; + assign \$1801 = \fus_cu_wr__rel_o$102 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; + assign \$1804 = wrpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_SPR_spr1_en_o; assign \$1807 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1806 ; assign \$1809 = \wr_pick$1803 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1807 ; - assign \$1812 = \wr_pick$1803 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_SPR_spr1_en_o; - assign \$1815 = \wp$1811 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_spro : 10'h000; - assign \$182 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 2'h2; - assign \$181 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$182 ; - assign \$186 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 7'h40; - assign \$185 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$186 ; - assign \$190 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 6'h20; - assign \$189 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$190 ; - assign \$194 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 8'h80; - assign \$193 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$194 ; - assign \$198 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 5'h10; - assign \$197 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$198 ; - assign \$202 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 11'h400; - assign \$201 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$202 ; - assign \$206 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 10'h200; - assign \$205 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$206 ; - assign \$210 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 9'h100; - assign \$209 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$210 ; - assign \$214 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 4'h8; - assign \$213 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$214 ; - assign \$218 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 3'h4; - assign \$217 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$218 ; - assign \$221 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h0; - assign \$224 = counter - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *) 1'h1; - assign \$226 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h0; - assign \$229 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$231 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$233 = \$231 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$235 = \$229 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$233 ; - assign \$237 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$239 = \$235 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$237 ; - assign \$241 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; - assign \$243 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$245 = \$243 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$247 = \$241 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$245 ; - assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$247 , \$239 , core_reg2_ok, core_reg1_ok }; - assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \core_cr_in2_ok$2 , core_cr_in2_ok, core_cr_in1_ok, core_core_cr_rd_ok, core_reg2_ok, core_reg1_ok }; - assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_cr_in1_ok, core_fast2_ok, core_fast1_ok }; - assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_fast2_ok, core_fast1_ok, core_reg2_ok, core_reg1_ok }; - assign \$257 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$259 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$261 = \$259 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$263 = \$257 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$261 ; - assign \$265 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$267 = \$263 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$265 ; - assign \$256 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$267 , core_reg2_ok, core_reg1_ok }; - assign \$271 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$273 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$275 = \$273 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$277 = \$271 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$275 ; - assign \$279 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$281 = \$277 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$279 ; - assign \$283 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) core_core_oe_ok; - assign \$285 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; - assign \$287 = \$285 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; - assign \$289 = \$283 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) \$287 ; - assign \$291 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; - assign \$293 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$295 = \$293 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$297 = \$291 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$295 ; - assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$297 , \$289 , \$281 , core_fast1_ok, core_spr1_ok, core_reg1_ok }; - assign \$301 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$303 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$305 = \$303 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$307 = \$301 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$305 ; - assign \$309 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$311 = \$307 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$309 ; - assign \$300 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$311 , core_reg2_ok, core_reg1_ok }; - assign \$315 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$317 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$319 = \$317 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$321 = \$315 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$319 ; - assign \$323 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$325 = \$321 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$323 ; - assign \$314 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$325 , core_reg2_ok, core_reg1_ok }; - assign \$329 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$331 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$333 = \$331 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$335 = \$329 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$333 ; - assign \$337 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$339 = \$335 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$337 ; - assign \$341 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; - assign \$343 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$345 = \$343 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$347 = \$341 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$345 ; - assign \$328 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$347 , \$339 , core_reg3_ok, core_reg2_ok, core_reg1_ok }; - assign \$350 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_reg3_ok, core_reg2_ok, core_reg1_ok }; - assign \$352 = fus_cu_rd__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0]; - assign \$354 = \$352 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; - assign \$356 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_alu0_0; - assign \$358 = \$354 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$356 ; - assign \$360 = rdpick_INT_rabc_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$362 = rp_INT_rabc_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; - assign \$364 = \fus_cu_rd__rel_o$40 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; - assign \$366 = \$364 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; - assign \$368 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_cr0_1; - assign \$370 = \$366 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$368 ; - assign \$372 = rdpick_INT_rabc_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$374 = rp_INT_rabc_cr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; - assign \$376 = \fus_cu_rd__rel_o$43 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3]; - assign \$378 = \$376 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; - assign \$380 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_trap0_2; - assign \$382 = \$378 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$380 ; - assign \$384 = rdpick_INT_rabc_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$386 = rp_INT_rabc_trap0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; - assign \$388 = \fus_cu_rd__rel_o$46 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4]; - assign \$390 = \$388 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; - assign \$392 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_logical0_3; - assign \$394 = \$390 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$392 ; - assign \$396 = rdpick_INT_rabc_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$398 = rp_INT_rabc_logical0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; - assign \$400 = \fus_cu_rd__rel_o$49 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6]; - assign \$402 = \$400 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; - assign \$404 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_div0_4; - assign \$406 = \$402 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$404 ; - assign \$408 = rdpick_INT_rabc_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$410 = rp_INT_rabc_div0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; - assign \$412 = \fus_cu_rd__rel_o$52 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7]; - assign \$414 = \$412 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; - assign \$416 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_mul0_5; - assign \$418 = \$414 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$416 ; - assign \$420 = rdpick_INT_rabc_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$422 = rp_INT_rabc_mul0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; - assign \$424 = \fus_cu_rd__rel_o$55 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8]; - assign \$426 = \$424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; - assign \$428 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_6; - assign \$430 = \$426 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$428 ; - assign \$432 = rdpick_INT_rabc_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$434 = rp_INT_rabc_shiftrot0_6 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; - assign \$436 = \fus_cu_rd__rel_o$58 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9]; - assign \$438 = \$436 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; - assign \$440 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_7; - assign \$442 = \$438 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$440 ; - assign \$444 = rdpick_INT_rabc_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$446 = rp_INT_rabc_ldst0_7 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; - assign \$448 = \fus_cu_rd__rel_o$55 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8]; - assign \$450 = \$448 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_1; - assign \$452 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_8; - assign \$454 = \$450 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$452 ; - assign \$456 = rdpick_INT_rabc_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$458 = rp_INT_rabc_shiftrot0_8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg3 : 7'h00; - assign \$460 = \fus_cu_rd__rel_o$58 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9]; - assign \$462 = \$460 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_1; - assign \$464 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_9; - assign \$466 = \$462 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$464 ; - assign \$468 = rdpick_INT_rabc_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$470 = rp_INT_rabc_ldst0_9 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg3 : 7'h00; - assign \$472 = fus_cu_rd__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0]; - assign \$474 = \$472 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; - assign \$476 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_alu0_10; - assign \$478 = \$474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$476 ; - assign \$480 = rdpick_INT_rabc_o[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$482 = rp_INT_rabc_alu0_10 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; - assign \$484 = \fus_cu_rd__rel_o$40 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; - assign \$486 = \$484 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; - assign \$488 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_cr0_11; - assign \$490 = \$486 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$488 ; - assign \$492 = rdpick_INT_rabc_o[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$494 = rp_INT_rabc_cr0_11 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; - assign \$496 = \fus_cu_rd__rel_o$43 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3]; - assign \$498 = \$496 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; - assign \$500 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_trap0_12; - assign \$502 = \$498 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$500 ; - assign \$504 = rdpick_INT_rabc_o[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$506 = rp_INT_rabc_trap0_12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; - assign \$508 = \fus_cu_rd__rel_o$46 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4]; - assign \$510 = \$508 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; - assign \$512 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_logical0_13; - assign \$514 = \$510 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$512 ; - assign \$516 = rdpick_INT_rabc_o[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$518 = rp_INT_rabc_logical0_13 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; - assign \$520 = \fus_cu_rd__rel_o$65 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; - assign \$522 = \$520 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; - assign \$524 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_spr0_14; - assign \$526 = \$522 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$524 ; - assign \$528 = rdpick_INT_rabc_o[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$530 = rp_INT_rabc_spr0_14 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; - assign \$532 = \fus_cu_rd__rel_o$49 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6]; - assign \$534 = \$532 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; - assign \$536 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_div0_15; - assign \$538 = \$534 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$536 ; - assign \$540 = rdpick_INT_rabc_o[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$542 = rp_INT_rabc_div0_15 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; - assign \$544 = \fus_cu_rd__rel_o$52 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7]; - assign \$546 = \$544 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; - assign \$548 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_mul0_16; - assign \$550 = \$546 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$548 ; - assign \$552 = rdpick_INT_rabc_o[16] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$554 = rp_INT_rabc_mul0_16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; - assign \$556 = \fus_cu_rd__rel_o$55 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8]; - assign \$558 = \$556 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; - assign \$560 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_17; - assign \$562 = \$558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$560 ; - assign \$564 = rdpick_INT_rabc_o[17] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$566 = rp_INT_rabc_shiftrot0_17 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; - assign \$568 = \fus_cu_rd__rel_o$58 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9]; - assign \$570 = \$568 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; - assign \$572 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_18; - assign \$574 = \$570 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$572 ; - assign \$576 = rdpick_INT_rabc_o[18] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; - assign \$578 = rp_INT_rabc_ldst0_18 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; + assign \$1812 = \wr_pick$1803 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_SPR_spr1_en_o; + assign \$1815 = \wp$1811 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_spro : 10'h000; + assign \$182 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 2'h2; + assign \$181 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$182 ; + assign \$186 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 7'h40; + assign \$185 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$186 ; + assign \$190 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 6'h20; + assign \$189 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$190 ; + assign \$194 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 8'h80; + assign \$193 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$194 ; + assign \$198 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 5'h10; + assign \$197 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$198 ; + assign \$202 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 11'h400; + assign \$201 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$202 ; + assign \$206 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 10'h200; + assign \$205 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$206 ; + assign \$210 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 9'h100; + assign \$209 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$210 ; + assign \$214 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 4'h8; + assign \$213 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$214 ; + assign \$218 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 3'h4; + assign \$217 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$218 ; + assign \$221 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) 1'h0; + assign \$224 = counter - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h1; + assign \$226 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) 1'h0; + assign \$229 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$231 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$233 = \$231 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$235 = \$229 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$233 ; + assign \$237 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$239 = \$235 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$237 ; + assign \$241 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$243 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$245 = \$243 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$247 = \$241 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$245 ; + assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$247 , \$239 , core_reg2_ok, core_reg1_ok }; + assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \core_cr_in2_ok$2 , core_cr_in2_ok, core_cr_in1_ok, core_core_cr_rd_ok, core_reg2_ok, core_reg1_ok }; + assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { core_cr_in1_ok, core_fast2_ok, core_fast1_ok }; + assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { core_fast2_ok, core_fast1_ok, core_reg2_ok, core_reg1_ok }; + assign \$257 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$259 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$261 = \$259 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$263 = \$257 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$261 ; + assign \$265 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$267 = \$263 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$265 ; + assign \$256 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$267 , core_reg2_ok, core_reg1_ok }; + assign \$271 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$273 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$275 = \$273 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$277 = \$271 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$275 ; + assign \$279 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$281 = \$277 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$279 ; + assign \$283 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) core_core_oe_ok; + assign \$285 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$287 = \$285 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$289 = \$283 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) \$287 ; + assign \$291 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$293 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$295 = \$293 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$297 = \$291 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$295 ; + assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$297 , \$289 , \$281 , core_fast1_ok, core_spr1_ok, core_reg1_ok }; + assign \$301 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$303 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$305 = \$303 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$307 = \$301 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$305 ; + assign \$309 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$311 = \$307 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$309 ; + assign \$300 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$311 , core_reg2_ok, core_reg1_ok }; + assign \$315 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$317 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$319 = \$317 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$321 = \$315 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$319 ; + assign \$323 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$325 = \$321 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$323 ; + assign \$314 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$325 , core_reg2_ok, core_reg1_ok }; + assign \$329 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$331 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$333 = \$331 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$335 = \$329 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$333 ; + assign \$337 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$339 = \$335 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$337 ; + assign \$341 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$343 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$345 = \$343 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$347 = \$341 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$345 ; + assign \$328 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$347 , \$339 , core_reg3_ok, core_reg2_ok, core_reg1_ok }; + assign \$350 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { core_reg3_ok, core_reg2_ok, core_reg1_ok }; + assign \$352 = fus_cu_rd__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0]; + assign \$354 = \$352 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; + assign \$356 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_alu0_0; + assign \$358 = \$354 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$356 ; + assign \$360 = rdpick_INT_rabc_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$362 = rp_INT_rabc_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; + assign \$364 = \fus_cu_rd__rel_o$40 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; + assign \$366 = \$364 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; + assign \$368 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_cr0_1; + assign \$370 = \$366 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$368 ; + assign \$372 = rdpick_INT_rabc_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$374 = rp_INT_rabc_cr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; + assign \$376 = \fus_cu_rd__rel_o$43 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3]; + assign \$378 = \$376 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; + assign \$380 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_trap0_2; + assign \$382 = \$378 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$380 ; + assign \$384 = rdpick_INT_rabc_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$386 = rp_INT_rabc_trap0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; + assign \$388 = \fus_cu_rd__rel_o$46 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[4]; + assign \$390 = \$388 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; + assign \$392 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_logical0_3; + assign \$394 = \$390 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$392 ; + assign \$396 = rdpick_INT_rabc_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$398 = rp_INT_rabc_logical0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; + assign \$400 = \fus_cu_rd__rel_o$49 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[6]; + assign \$402 = \$400 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; + assign \$404 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_div0_4; + assign \$406 = \$402 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$404 ; + assign \$408 = rdpick_INT_rabc_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$410 = rp_INT_rabc_div0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; + assign \$412 = \fus_cu_rd__rel_o$52 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[7]; + assign \$414 = \$412 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; + assign \$416 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_mul0_5; + assign \$418 = \$414 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$416 ; + assign \$420 = rdpick_INT_rabc_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$422 = rp_INT_rabc_mul0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; + assign \$424 = \fus_cu_rd__rel_o$55 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8]; + assign \$426 = \$424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; + assign \$428 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_shiftrot0_6; + assign \$430 = \$426 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$428 ; + assign \$432 = rdpick_INT_rabc_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$434 = rp_INT_rabc_shiftrot0_6 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; + assign \$436 = \fus_cu_rd__rel_o$58 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[9]; + assign \$438 = \$436 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; + assign \$440 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_ldst0_7; + assign \$442 = \$438 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$440 ; + assign \$444 = rdpick_INT_rabc_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$446 = rp_INT_rabc_ldst0_7 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; + assign \$448 = \fus_cu_rd__rel_o$55 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8]; + assign \$450 = \$448 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_1; + assign \$452 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_shiftrot0_8; + assign \$454 = \$450 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$452 ; + assign \$456 = rdpick_INT_rabc_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$458 = rp_INT_rabc_shiftrot0_8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg3 : 7'h00; + assign \$460 = \fus_cu_rd__rel_o$58 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[9]; + assign \$462 = \$460 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_1; + assign \$464 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_ldst0_9; + assign \$466 = \$462 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$464 ; + assign \$468 = rdpick_INT_rabc_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$470 = rp_INT_rabc_ldst0_9 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg3 : 7'h00; + assign \$472 = fus_cu_rd__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0]; + assign \$474 = \$472 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; + assign \$476 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_alu0_10; + assign \$478 = \$474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$476 ; + assign \$480 = rdpick_INT_rabc_o[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$482 = rp_INT_rabc_alu0_10 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; + assign \$484 = \fus_cu_rd__rel_o$40 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; + assign \$486 = \$484 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; + assign \$488 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_cr0_11; + assign \$490 = \$486 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$488 ; + assign \$492 = rdpick_INT_rabc_o[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$494 = rp_INT_rabc_cr0_11 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; + assign \$496 = \fus_cu_rd__rel_o$43 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3]; + assign \$498 = \$496 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; + assign \$500 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_trap0_12; + assign \$502 = \$498 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$500 ; + assign \$504 = rdpick_INT_rabc_o[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$506 = rp_INT_rabc_trap0_12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; + assign \$508 = \fus_cu_rd__rel_o$46 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[4]; + assign \$510 = \$508 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; + assign \$512 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_logical0_13; + assign \$514 = \$510 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$512 ; + assign \$516 = rdpick_INT_rabc_o[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$518 = rp_INT_rabc_logical0_13 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; + assign \$520 = \fus_cu_rd__rel_o$65 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; + assign \$522 = \$520 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; + assign \$524 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_spr0_14; + assign \$526 = \$522 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$524 ; + assign \$528 = rdpick_INT_rabc_o[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$530 = rp_INT_rabc_spr0_14 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; + assign \$532 = \fus_cu_rd__rel_o$49 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[6]; + assign \$534 = \$532 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; + assign \$536 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_div0_15; + assign \$538 = \$534 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$536 ; + assign \$540 = rdpick_INT_rabc_o[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$542 = rp_INT_rabc_div0_15 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; + assign \$544 = \fus_cu_rd__rel_o$52 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[7]; + assign \$546 = \$544 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; + assign \$548 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_mul0_16; + assign \$550 = \$546 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$548 ; + assign \$552 = rdpick_INT_rabc_o[16] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$554 = rp_INT_rabc_mul0_16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; + assign \$556 = \fus_cu_rd__rel_o$55 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8]; + assign \$558 = \$556 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; + assign \$560 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_shiftrot0_17; + assign \$562 = \$558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$560 ; + assign \$564 = rdpick_INT_rabc_o[17] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$566 = rp_INT_rabc_shiftrot0_17 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; + assign \$568 = \fus_cu_rd__rel_o$58 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[9]; + assign \$570 = \$568 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; + assign \$572 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_ldst0_18; + assign \$574 = \$570 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$572 ; + assign \$576 = rdpick_INT_rabc_o[18] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; + assign \$578 = rp_INT_rabc_ldst0_18 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; assign \$581 = addr_en_INT_rabc_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_cr0_1; assign \$583 = addr_en_INT_rabc_trap0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_3; assign \$585 = \$581 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$583 ; @@ -42057,192 +42057,192 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c assign \$611 = \$605 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$609 ; assign \$613 = \$603 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$611 ; assign \$615 = \$595 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$613 ; - assign \$617 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) { rp_INT_rabc_ldst0_18, rp_INT_rabc_shiftrot0_17, rp_INT_rabc_mul0_16, rp_INT_rabc_div0_15, rp_INT_rabc_spr0_14, rp_INT_rabc_logical0_13, rp_INT_rabc_trap0_12, rp_INT_rabc_cr0_11, rp_INT_rabc_alu0_10, rp_INT_rabc_ldst0_9, rp_INT_rabc_shiftrot0_8, rp_INT_rabc_ldst0_7, rp_INT_rabc_shiftrot0_6, rp_INT_rabc_mul0_5, rp_INT_rabc_div0_4, rp_INT_rabc_logical0_3, rp_INT_rabc_trap0_2, rp_INT_rabc_cr0_1, rp_INT_rabc_alu0_0 }; - assign \$619 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$621 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$623 = \$621 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$625 = \$619 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$623 ; - assign \$627 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$629 = \$625 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$627 ; - assign \$631 = fus_cu_rd__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0]; - assign \$633 = \$631 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; - assign \$635 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_alu0_0; - assign \$637 = \$633 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$635 ; - assign \$639 = rdpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; - assign \$641 = rp_XER_xer_so_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; - assign \$643 = \fus_cu_rd__rel_o$46 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4]; - assign \$645 = \$643 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; - assign \$647 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_logical0_1; - assign \$649 = \$645 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$647 ; - assign \$651 = rdpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; - assign \$653 = rp_XER_xer_so_logical0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; - assign \$655 = \fus_cu_rd__rel_o$65 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; - assign \$657 = \$655 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; - assign \$659 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_spr0_2; - assign \$661 = \$657 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$659 ; - assign \$663 = rdpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; - assign \$665 = rp_XER_xer_so_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; - assign \$667 = \fus_cu_rd__rel_o$49 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6]; - assign \$669 = \$667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; - assign \$671 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_div0_3; - assign \$673 = \$669 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$671 ; - assign \$675 = rdpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; - assign \$677 = rp_XER_xer_so_div0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; - assign \$679 = \fus_cu_rd__rel_o$52 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7]; - assign \$681 = \$679 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; - assign \$683 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_mul0_4; - assign \$685 = \$681 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$683 ; - assign \$687 = rdpick_XER_xer_so_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; - assign \$689 = rp_XER_xer_so_mul0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; - assign \$691 = \fus_cu_rd__rel_o$55 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8]; - assign \$693 = \$691 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; - assign \$695 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_shiftrot0_5; - assign \$697 = \$693 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$695 ; - assign \$699 = rdpick_XER_xer_so_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; - assign \$701 = rp_XER_xer_so_shiftrot0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; + assign \$617 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) { rp_INT_rabc_ldst0_18, rp_INT_rabc_shiftrot0_17, rp_INT_rabc_mul0_16, rp_INT_rabc_div0_15, rp_INT_rabc_spr0_14, rp_INT_rabc_logical0_13, rp_INT_rabc_trap0_12, rp_INT_rabc_cr0_11, rp_INT_rabc_alu0_10, rp_INT_rabc_ldst0_9, rp_INT_rabc_shiftrot0_8, rp_INT_rabc_ldst0_7, rp_INT_rabc_shiftrot0_6, rp_INT_rabc_mul0_5, rp_INT_rabc_div0_4, rp_INT_rabc_logical0_3, rp_INT_rabc_trap0_2, rp_INT_rabc_cr0_1, rp_INT_rabc_alu0_0 }; + assign \$619 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$621 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$623 = \$621 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$625 = \$619 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$623 ; + assign \$627 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$629 = \$625 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$627 ; + assign \$631 = fus_cu_rd__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0]; + assign \$633 = \$631 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; + assign \$635 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_alu0_0; + assign \$637 = \$633 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$635 ; + assign \$639 = rdpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; + assign \$641 = rp_XER_xer_so_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; + assign \$643 = \fus_cu_rd__rel_o$46 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[4]; + assign \$645 = \$643 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; + assign \$647 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_logical0_1; + assign \$649 = \$645 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$647 ; + assign \$651 = rdpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; + assign \$653 = rp_XER_xer_so_logical0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; + assign \$655 = \fus_cu_rd__rel_o$65 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; + assign \$657 = \$655 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; + assign \$659 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_spr0_2; + assign \$661 = \$657 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$659 ; + assign \$663 = rdpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; + assign \$665 = rp_XER_xer_so_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; + assign \$667 = \fus_cu_rd__rel_o$49 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[6]; + assign \$669 = \$667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; + assign \$671 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_div0_3; + assign \$673 = \$669 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$671 ; + assign \$675 = rdpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; + assign \$677 = rp_XER_xer_so_div0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; + assign \$679 = \fus_cu_rd__rel_o$52 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[7]; + assign \$681 = \$679 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; + assign \$683 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_mul0_4; + assign \$685 = \$681 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$683 ; + assign \$687 = rdpick_XER_xer_so_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; + assign \$689 = rp_XER_xer_so_mul0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; + assign \$691 = \fus_cu_rd__rel_o$55 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8]; + assign \$693 = \$691 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; + assign \$695 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_shiftrot0_5; + assign \$697 = \$693 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$695 ; + assign \$699 = rdpick_XER_xer_so_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; + assign \$701 = rp_XER_xer_so_shiftrot0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; assign \$704 = addr_en_XER_xer_so_logical0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_spr0_2; assign \$706 = addr_en_XER_xer_so_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$704 ; assign \$708 = addr_en_XER_xer_so_mul0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_shiftrot0_5; assign \$710 = addr_en_XER_xer_so_div0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$708 ; assign \$712 = \$706 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$710 ; assign \$703 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$712 ; - assign \$715 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; - assign \$717 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$719 = \$717 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$721 = \$715 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$719 ; - assign \$723 = fus_cu_rd__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0]; - assign \$725 = \$723 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0; - assign \$727 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_alu0_0; - assign \$729 = \$725 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$727 ; - assign \$731 = rdpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o; - assign \$733 = rp_XER_xer_ca_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0; - assign \$735 = \fus_cu_rd__rel_o$65 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; - assign \$737 = \$735 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0; - assign \$739 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_spr0_1; - assign \$741 = \$737 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$739 ; - assign \$743 = rdpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o; - assign \$745 = rp_XER_xer_ca_spr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0; - assign \$747 = \fus_cu_rd__rel_o$55 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8]; - assign \$749 = \$747 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0; - assign \$751 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_shiftrot0_2; - assign \$753 = \$749 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$751 ; - assign \$755 = rdpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o; - assign \$757 = rp_XER_xer_ca_shiftrot0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0; + assign \$715 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$717 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$719 = \$717 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$721 = \$715 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$719 ; + assign \$723 = fus_cu_rd__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0]; + assign \$725 = \$723 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ca_0; + assign \$727 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ca_alu0_0; + assign \$729 = \$725 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$727 ; + assign \$731 = rdpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ca_en_o; + assign \$733 = rp_XER_xer_ca_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 2'h2 : 2'h0; + assign \$735 = \fus_cu_rd__rel_o$65 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; + assign \$737 = \$735 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ca_0; + assign \$739 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ca_spr0_1; + assign \$741 = \$737 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$739 ; + assign \$743 = rdpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ca_en_o; + assign \$745 = rp_XER_xer_ca_spr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 2'h2 : 2'h0; + assign \$747 = \fus_cu_rd__rel_o$55 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8]; + assign \$749 = \$747 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ca_0; + assign \$751 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ca_shiftrot0_2; + assign \$753 = \$749 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$751 ; + assign \$755 = rdpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ca_en_o; + assign \$757 = rp_XER_xer_ca_shiftrot0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 2'h2 : 2'h0; assign \$760 = addr_en_XER_xer_ca_spr0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_ca_shiftrot0_2; assign \$762 = addr_en_XER_xer_ca_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$760 ; assign \$759 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$762 ; - assign \$765 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) core_core_oe_ok; - assign \$767 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; - assign \$769 = \$767 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; - assign \$771 = \$765 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) \$769 ; - assign \$773 = \fus_cu_rd__rel_o$65 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; - assign \$775 = \$773 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ov_0; - assign \$777 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ov_spr0_0; - assign \$779 = \$775 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$777 ; - assign \$781 = rdpick_XER_xer_ov_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ov_en_o; - assign \$783 = rp_XER_xer_ov_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 3'h4 : 3'h0; - assign \$785 = \fus_cu_rd__rel_o$40 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; - assign \$787 = \$785 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_full_cr_0; - assign \$789 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_full_cr_cr0_0; - assign \$791 = \$787 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$789 ; - assign \$793 = rdpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_full_cr_en_o; - assign \$795 = rp_CR_full_cr_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_core_cr_rd : 8'h00; - assign \$797 = \fus_cu_rd__rel_o$40 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; - assign \$799 = \$797 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_a_0; - assign \$801 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_a_cr0_0; - assign \$803 = \$799 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$801 ; - assign \$805 = rdpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_a_en_o; - assign \$807 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) core_cr_in1; - assign \$809 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) \$807 ; - assign \$811 = rp_CR_cr_a_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$809 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$813 = \fus_cu_rd__rel_o$81 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2]; - assign \$815 = \$813 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_a_0; - assign \$817 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_a_branch0_1; - assign \$819 = \$815 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$817 ; - assign \$821 = rdpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_a_en_o; - assign \$823 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) core_cr_in1; - assign \$825 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) \$823 ; - assign \$827 = rp_CR_cr_a_branch0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$825 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$765 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) core_core_oe_ok; + assign \$767 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$769 = \$767 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$771 = \$765 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) \$769 ; + assign \$773 = \fus_cu_rd__rel_o$65 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; + assign \$775 = \$773 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ov_0; + assign \$777 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ov_spr0_0; + assign \$779 = \$775 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$777 ; + assign \$781 = rdpick_XER_xer_ov_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ov_en_o; + assign \$783 = rp_XER_xer_ov_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 3'h4 : 3'h0; + assign \$785 = \fus_cu_rd__rel_o$40 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; + assign \$787 = \$785 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_full_cr_0; + assign \$789 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_full_cr_cr0_0; + assign \$791 = \$787 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$789 ; + assign \$793 = rdpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_full_cr_en_o; + assign \$795 = rp_CR_full_cr_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_core_cr_rd : 8'h00; + assign \$797 = \fus_cu_rd__rel_o$40 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; + assign \$799 = \$797 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_a_0; + assign \$801 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_a_cr0_0; + assign \$803 = \$799 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$801 ; + assign \$805 = rdpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_a_en_o; + assign \$807 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) core_cr_in1; + assign \$809 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) \$807 ; + assign \$811 = rp_CR_cr_a_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$809 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$813 = \fus_cu_rd__rel_o$81 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[2]; + assign \$815 = \$813 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_a_0; + assign \$817 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_a_branch0_1; + assign \$819 = \$815 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$817 ; + assign \$821 = rdpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_a_en_o; + assign \$823 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) core_cr_in1; + assign \$825 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) \$823 ; + assign \$827 = rp_CR_cr_a_branch0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$825 : 256'h0000000000000000000000000000000000000000000000000000000000000000; assign \$830 = addr_en_CR_cr_a_cr0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_CR_cr_a_branch0_1; - assign \$832 = \fus_cu_rd__rel_o$40 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; - assign \$834 = \$832 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_b_0; - assign \$836 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_b_cr0_0; - assign \$838 = \$834 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$836 ; - assign \$840 = rdpick_CR_cr_b_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_b_en_o; - assign \$842 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) core_cr_in2; - assign \$844 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) \$842 ; - assign \$846 = rp_CR_cr_b_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$844 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$848 = \fus_cu_rd__rel_o$40 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; - assign \$850 = \$848 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_c_0; - assign \$852 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_c_cr0_0; - assign \$854 = \$850 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$852 ; - assign \$856 = rdpick_CR_cr_c_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_c_en_o; - assign \$858 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) \core_cr_in2$1 ; - assign \$860 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) \$858 ; - assign \$862 = rp_CR_cr_c_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$860 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$864 = \fus_cu_rd__rel_o$81 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2]; - assign \$866 = \$864 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0; - assign \$868 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_branch0_0; - assign \$870 = \$866 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$868 ; - assign \$872 = rdpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o; - assign \$874 = rp_FAST_fast1_branch0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0; - assign \$876 = \fus_cu_rd__rel_o$43 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3]; - assign \$878 = \$876 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0; - assign \$880 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_trap0_1; - assign \$882 = \$878 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$880 ; - assign \$884 = rdpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o; - assign \$886 = rp_FAST_fast1_trap0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0; - assign \$888 = \fus_cu_rd__rel_o$65 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; - assign \$890 = \$888 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0; - assign \$892 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_spr0_2; - assign \$894 = \$890 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$892 ; - assign \$896 = rdpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o; - assign \$898 = rp_FAST_fast1_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0; - assign \$900 = \fus_cu_rd__rel_o$81 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2]; - assign \$902 = \$900 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_1; - assign \$904 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_branch0_3; - assign \$906 = \$902 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$904 ; - assign \$908 = rdpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o; - assign \$910 = rp_FAST_fast1_branch0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast2 : 3'h0; - assign \$912 = \fus_cu_rd__rel_o$43 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3]; - assign \$914 = \$912 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_1; - assign \$916 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_trap0_4; - assign \$918 = \$914 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$916 ; - assign \$920 = rdpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o; - assign \$922 = rp_FAST_fast1_trap0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast2 : 3'h0; + assign \$832 = \fus_cu_rd__rel_o$40 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; + assign \$834 = \$832 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_b_0; + assign \$836 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_b_cr0_0; + assign \$838 = \$834 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$836 ; + assign \$840 = rdpick_CR_cr_b_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_b_en_o; + assign \$842 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) core_cr_in2; + assign \$844 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) \$842 ; + assign \$846 = rp_CR_cr_b_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$844 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$848 = \fus_cu_rd__rel_o$40 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; + assign \$850 = \$848 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_c_0; + assign \$852 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_c_cr0_0; + assign \$854 = \$850 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$852 ; + assign \$856 = rdpick_CR_cr_c_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_c_en_o; + assign \$858 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) \core_cr_in2$1 ; + assign \$860 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) \$858 ; + assign \$862 = rp_CR_cr_c_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$860 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$864 = \fus_cu_rd__rel_o$81 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[2]; + assign \$866 = \$864 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_0; + assign \$868 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_branch0_0; + assign \$870 = \$866 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$868 ; + assign \$872 = rdpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o; + assign \$874 = rp_FAST_fast1_branch0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast1 : 3'h0; + assign \$876 = \fus_cu_rd__rel_o$43 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3]; + assign \$878 = \$876 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_0; + assign \$880 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_trap0_1; + assign \$882 = \$878 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$880 ; + assign \$884 = rdpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o; + assign \$886 = rp_FAST_fast1_trap0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast1 : 3'h0; + assign \$888 = \fus_cu_rd__rel_o$65 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; + assign \$890 = \$888 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_0; + assign \$892 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_spr0_2; + assign \$894 = \$890 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$892 ; + assign \$896 = rdpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o; + assign \$898 = rp_FAST_fast1_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast1 : 3'h0; + assign \$900 = \fus_cu_rd__rel_o$81 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[2]; + assign \$902 = \$900 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_1; + assign \$904 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_branch0_3; + assign \$906 = \$902 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$904 ; + assign \$908 = rdpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o; + assign \$910 = rp_FAST_fast1_branch0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast2 : 3'h0; + assign \$912 = \fus_cu_rd__rel_o$43 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3]; + assign \$914 = \$912 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_1; + assign \$916 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_trap0_4; + assign \$918 = \$914 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$916 ; + assign \$920 = rdpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o; + assign \$922 = rp_FAST_fast1_trap0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast2 : 3'h0; assign \$924 = addr_en_FAST_fast1_branch0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_1; assign \$926 = addr_en_FAST_fast1_branch0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_4; assign \$928 = addr_en_FAST_fast1_spr0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$926 ; assign \$930 = \$924 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$928 ; - assign \$932 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) { rp_FAST_fast1_trap0_4, rp_FAST_fast1_branch0_3, rp_FAST_fast1_spr0_2, rp_FAST_fast1_trap0_1, rp_FAST_fast1_branch0_0 }; - assign \$934 = \fus_cu_rd__rel_o$65 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; - assign \$936 = \$934 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_SPR_spr1_0; - assign \$938 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_SPR_spr1_spr0_0; - assign \$940 = \$936 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$938 ; - assign \$942 = rdpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_SPR_spr1_en_o; - assign \$944 = rp_SPR_spr1_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_spr1 : 10'h000; - assign \$946 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) rp_SPR_spr1_spr0_0; - assign \$948 = fus_o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o; - assign \$950 = fus_cu_wr__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0]; - assign \$952 = \fus_cu_wr__rel_o$93 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1]; - assign \$954 = \fus_cu_wr__rel_o$96 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3]; - assign \$956 = \fus_cu_wr__rel_o$99 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[4]; - assign \$958 = \fus_cu_wr__rel_o$102 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; - assign \$960 = \fus_cu_wr__rel_o$105 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6]; - assign \$962 = \fus_cu_wr__rel_o$108 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7]; - assign \$964 = \fus_cu_wr__rel_o$111 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8]; - assign \$966 = \fus_cu_wr__rel_o$113 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[9]; - assign \$968 = \fus_cu_wr__rel_o$113 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[9]; - assign \$970 = wrpick_INT_o_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$932 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) { rp_FAST_fast1_trap0_4, rp_FAST_fast1_branch0_3, rp_FAST_fast1_spr0_2, rp_FAST_fast1_trap0_1, rp_FAST_fast1_branch0_0 }; + assign \$934 = \fus_cu_rd__rel_o$65 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; + assign \$936 = \$934 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_SPR_spr1_0; + assign \$938 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_SPR_spr1_spr0_0; + assign \$940 = \$936 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$938 ; + assign \$942 = rdpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_SPR_spr1_en_o; + assign \$944 = rp_SPR_spr1_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_spr1 : 10'h000; + assign \$946 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) rp_SPR_spr1_spr0_0; + assign \$948 = fus_o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o; + assign \$950 = fus_cu_wr__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0]; + assign \$952 = \fus_cu_wr__rel_o$93 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[1]; + assign \$954 = \fus_cu_wr__rel_o$96 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3]; + assign \$956 = \fus_cu_wr__rel_o$99 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[4]; + assign \$958 = \fus_cu_wr__rel_o$102 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; + assign \$960 = \fus_cu_wr__rel_o$105 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6]; + assign \$962 = \fus_cu_wr__rel_o$108 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7]; + assign \$964 = \fus_cu_wr__rel_o$111 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[8]; + assign \$966 = \fus_cu_wr__rel_o$113 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[9]; + assign \$968 = \fus_cu_wr__rel_o$113 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[9]; + assign \$970 = wrpick_INT_o_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; assign \$972 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wr_pick_dly; assign \$974 = wr_pick & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$972 ; - assign \$980 = wr_pick & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; - assign \$982 = wp ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; - assign \$984 = \fus_o_ok$92 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ; - assign \$987 = wrpick_INT_o_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$980 = wr_pick & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; + assign \$982 = wp ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; + assign \$984 = \fus_o_ok$92 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$14 ; + assign \$987 = wrpick_INT_o_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; assign \$991 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$989 ; assign \$993 = \wr_pick$986 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$991 ; - assign \$998 = \wr_pick$986 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + assign \$998 = \wr_pick$986 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; always @(posedge coresync_clk) \wr_pick_dly$1806 <= \wr_pick_dly$1806$next ; always @(posedge coresync_clk) @@ -43117,27 +43117,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__output_carry = dec_LOGICAL_LOGICAL__output_carry; endcase @@ -43147,27 +43147,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__is_32bit = dec_LOGICAL_LOGICAL__is_32bit; endcase @@ -43177,27 +43177,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__is_signed = dec_LOGICAL_LOGICAL__is_signed; endcase @@ -43207,27 +43207,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__data_len = dec_LOGICAL_LOGICAL__data_len; endcase @@ -43237,27 +43237,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__insn = dec_LOGICAL_LOGICAL__insn; endcase @@ -43267,27 +43267,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_issue_i$22 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_issue_i$22 = issue_i; endcase @@ -43297,27 +43297,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$24 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_rdmaskn_i$24 = \$256 ; endcase @@ -43327,27 +43327,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_spr0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_spr0__insn_type = dec_SPR_SPR__insn_type; endcase @@ -43357,27 +43357,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_spr0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_spr0__fn_unit = dec_SPR_SPR__fn_unit; endcase @@ -43387,27 +43387,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_spr0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_spr0__insn = dec_SPR_SPR__insn; endcase @@ -43417,27 +43417,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_spr0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_spr0__is_32bit = dec_SPR_SPR__is_32bit; endcase @@ -43447,27 +43447,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_issue_i$25 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_issue_i$25 = issue_i; endcase @@ -43477,27 +43477,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$27 = 6'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_rdmaskn_i$27 = \$270 ; endcase @@ -43507,27 +43507,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__insn_type = dec_DIV_DIV__insn_type; endcase @@ -43537,27 +43537,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__fn_unit = dec_DIV_DIV__fn_unit; endcase @@ -43568,27 +43568,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_div0__imm_data__data = 64'h0000000000000000; fus_oper_i_alu_div0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_div0__imm_data__ok, fus_oper_i_alu_div0__imm_data__data } = { dec_DIV_DIV__imm_data__ok, dec_DIV_DIV__imm_data__data }; endcase @@ -43599,27 +43599,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_div0__rc__rc = 1'h0; fus_oper_i_alu_div0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_div0__rc__ok, fus_oper_i_alu_div0__rc__rc } = { dec_DIV_DIV__rc__ok, dec_DIV_DIV__rc__rc }; endcase @@ -43630,27 +43630,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_div0__oe__oe = 1'h0; fus_oper_i_alu_div0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_div0__oe__ok, fus_oper_i_alu_div0__oe__oe } = { dec_DIV_DIV__oe__ok, dec_DIV_DIV__oe__oe }; endcase @@ -43660,27 +43660,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__invert_in = dec_DIV_DIV__invert_in; endcase @@ -43690,27 +43690,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__zero_a = dec_DIV_DIV__zero_a; endcase @@ -43720,27 +43720,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__input_carry = dec_DIV_DIV__input_carry; endcase @@ -43750,27 +43750,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__invert_out = dec_DIV_DIV__invert_out; endcase @@ -43780,27 +43780,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__write_cr0 = dec_DIV_DIV__write_cr0; endcase @@ -43810,27 +43810,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__output_carry = dec_DIV_DIV__output_carry; endcase @@ -43840,27 +43840,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__is_32bit = dec_DIV_DIV__is_32bit; endcase @@ -43870,27 +43870,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__is_signed = dec_DIV_DIV__is_signed; endcase @@ -43900,27 +43900,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__data_len = dec_DIV_DIV__data_len; endcase @@ -43930,27 +43930,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_div0__insn = dec_DIV_DIV__insn; endcase @@ -43960,27 +43960,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_issue_i$28 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_issue_i$28 = issue_i; endcase @@ -43990,27 +43990,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$30 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_rdmaskn_i$30 = \$300 ; endcase @@ -44020,27 +44020,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_mul0__insn_type = dec_MUL_MUL__insn_type; endcase @@ -44050,27 +44050,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_mul0__fn_unit = dec_MUL_MUL__fn_unit; endcase @@ -44081,27 +44081,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_mul0__imm_data__data = 64'h0000000000000000; fus_oper_i_alu_mul0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_mul0__imm_data__ok, fus_oper_i_alu_mul0__imm_data__data } = { dec_MUL_MUL__imm_data__ok, dec_MUL_MUL__imm_data__data }; endcase @@ -44112,27 +44112,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_mul0__rc__rc = 1'h0; fus_oper_i_alu_mul0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_mul0__rc__ok, fus_oper_i_alu_mul0__rc__rc } = { dec_MUL_MUL__rc__ok, dec_MUL_MUL__rc__rc }; endcase @@ -44143,27 +44143,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_mul0__oe__oe = 1'h0; fus_oper_i_alu_mul0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_mul0__oe__ok, fus_oper_i_alu_mul0__oe__oe } = { dec_MUL_MUL__oe__ok, dec_MUL_MUL__oe__oe }; endcase @@ -44173,27 +44173,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_mul0__write_cr0 = dec_MUL_MUL__write_cr0; endcase @@ -44203,27 +44203,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_mul0__is_32bit = dec_MUL_MUL__is_32bit; endcase @@ -44233,27 +44233,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_mul0__is_signed = dec_MUL_MUL__is_signed; endcase @@ -44263,27 +44263,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_mul0__insn = dec_MUL_MUL__insn; endcase @@ -44293,27 +44293,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_issue_i$31 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_issue_i$31 = issue_i; endcase @@ -44323,27 +44323,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$33 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_rdmaskn_i$33 = \$314 ; endcase @@ -44353,27 +44353,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__insn_type = dec_SHIFT_ROT_SHIFT_ROT__insn_type; endcase @@ -44383,27 +44383,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__fn_unit = dec_SHIFT_ROT_SHIFT_ROT__fn_unit; endcase @@ -44414,27 +44414,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_shift_rot0__imm_data__data = 64'h0000000000000000; fus_oper_i_alu_shift_rot0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_shift_rot0__imm_data__ok, fus_oper_i_alu_shift_rot0__imm_data__data } = { dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok, dec_SHIFT_ROT_SHIFT_ROT__imm_data__data }; endcase @@ -44445,27 +44445,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_shift_rot0__rc__rc = 1'h0; fus_oper_i_alu_shift_rot0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_shift_rot0__rc__ok, fus_oper_i_alu_shift_rot0__rc__rc } = { dec_SHIFT_ROT_SHIFT_ROT__rc__ok, dec_SHIFT_ROT_SHIFT_ROT__rc__rc }; endcase @@ -44476,27 +44476,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_shift_rot0__oe__oe = 1'h0; fus_oper_i_alu_shift_rot0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_shift_rot0__oe__ok, fus_oper_i_alu_shift_rot0__oe__oe } = { dec_SHIFT_ROT_SHIFT_ROT__oe__ok, dec_SHIFT_ROT_SHIFT_ROT__oe__oe }; endcase @@ -44506,27 +44506,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__write_cr0 = dec_SHIFT_ROT_SHIFT_ROT__write_cr0; endcase @@ -44536,27 +44536,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__invert_in = dec_SHIFT_ROT_SHIFT_ROT__invert_in; endcase @@ -44566,27 +44566,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__input_carry = dec_SHIFT_ROT_SHIFT_ROT__input_carry; endcase @@ -44596,27 +44596,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__output_carry = dec_SHIFT_ROT_SHIFT_ROT__output_carry; endcase @@ -44626,27 +44626,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__input_cr = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__input_cr = dec_SHIFT_ROT_SHIFT_ROT__input_cr; endcase @@ -44656,27 +44656,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__output_cr = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__output_cr = dec_SHIFT_ROT_SHIFT_ROT__output_cr; endcase @@ -44686,27 +44686,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__is_32bit = dec_SHIFT_ROT_SHIFT_ROT__is_32bit; endcase @@ -44716,27 +44716,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__is_signed = dec_SHIFT_ROT_SHIFT_ROT__is_signed; endcase @@ -44746,27 +44746,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_shift_rot0__insn = dec_SHIFT_ROT_SHIFT_ROT__insn; endcase @@ -44776,27 +44776,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_issue_i$34 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_issue_i$34 = issue_i; endcase @@ -44806,27 +44806,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$36 = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_rdmaskn_i$36 = \$328 ; endcase @@ -44836,27 +44836,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_ldst_ldst0__insn_type = dec_LDST_LDST__insn_type; endcase @@ -44866,27 +44866,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_ldst_ldst0__fn_unit = dec_LDST_LDST__fn_unit; endcase @@ -44897,27 +44897,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_ldst_ldst0__imm_data__data = 64'h0000000000000000; fus_oper_i_ldst_ldst0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_ldst_ldst0__imm_data__ok, fus_oper_i_ldst_ldst0__imm_data__data } = { dec_LDST_LDST__imm_data__ok, dec_LDST_LDST__imm_data__data }; endcase @@ -44927,27 +44927,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_ldst_ldst0__zero_a = dec_LDST_LDST__zero_a; endcase @@ -44958,27 +44958,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_ldst_ldst0__rc__rc = 1'h0; fus_oper_i_ldst_ldst0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_ldst_ldst0__rc__ok, fus_oper_i_ldst_ldst0__rc__rc } = { dec_LDST_LDST__rc__ok, dec_LDST_LDST__rc__rc }; endcase @@ -44989,27 +44989,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_ldst_ldst0__oe__oe = 1'h0; fus_oper_i_ldst_ldst0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_ldst_ldst0__oe__ok, fus_oper_i_ldst_ldst0__oe__oe } = { dec_LDST_LDST__oe__ok, dec_LDST_LDST__oe__oe }; endcase @@ -45019,27 +45019,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_ldst_ldst0__is_32bit = dec_LDST_LDST__is_32bit; endcase @@ -45049,27 +45049,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_ldst_ldst0__is_signed = dec_LDST_LDST__is_signed; endcase @@ -45079,27 +45079,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_ldst_ldst0__data_len = dec_LDST_LDST__data_len; endcase @@ -45109,27 +45109,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__byte_reverse = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_ldst_ldst0__byte_reverse = dec_LDST_LDST__byte_reverse; endcase @@ -45139,27 +45139,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__sign_extend = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_ldst_ldst0__sign_extend = dec_LDST_LDST__sign_extend; endcase @@ -45169,27 +45169,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__ldst_mode = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_ldst_ldst0__ldst_mode = dec_LDST_LDST__ldst_mode; endcase @@ -45199,27 +45199,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_ldst_ldst0__insn = dec_LDST_LDST__insn; endcase @@ -45229,27 +45229,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_issue_i$37 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_issue_i$37 = issue_i; endcase @@ -45259,27 +45259,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$39 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_rdmaskn_i$39 = \$350 ; endcase @@ -45289,7 +45289,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_alu0_0$next = rp_INT_rabc_alu0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_alu0_0$next = 1'h0; @@ -45298,9 +45298,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src2_i = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_alu0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: fus_src2_i = int_src1__data_o; endcase @@ -45308,7 +45308,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_cr0_1$next = rp_INT_rabc_cr0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_cr0_1$next = 1'h0; @@ -45317,9 +45317,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$42 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_cr0_1) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src2_i$42 = int_src1__data_o; endcase @@ -45327,7 +45327,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_trap0_2$next = rp_INT_rabc_trap0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_trap0_2$next = 1'h0; @@ -45336,9 +45336,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$45 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_trap0_2) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src2_i$45 = int_src1__data_o; endcase @@ -45346,7 +45346,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_logical0_3$next = rp_INT_rabc_logical0_3; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_logical0_3$next = 1'h0; @@ -45355,9 +45355,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$48 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_logical0_3) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src2_i$48 = int_src1__data_o; endcase @@ -45365,7 +45365,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_div0_4$next = rp_INT_rabc_div0_4; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_div0_4$next = 1'h0; @@ -45374,9 +45374,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$51 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_div0_4) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src2_i$51 = int_src1__data_o; endcase @@ -45384,7 +45384,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_mul0_5$next = rp_INT_rabc_mul0_5; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_mul0_5$next = 1'h0; @@ -45393,9 +45393,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$54 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_mul0_5) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src2_i$54 = int_src1__data_o; endcase @@ -45403,7 +45403,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_shiftrot0_6$next = rp_INT_rabc_shiftrot0_6; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_shiftrot0_6$next = 1'h0; @@ -45412,9 +45412,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$57 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_shiftrot0_6) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src2_i$57 = int_src1__data_o; endcase @@ -45422,7 +45422,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_ldst0_7$next = rp_INT_rabc_ldst0_7; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_ldst0_7$next = 1'h0; @@ -45431,9 +45431,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$60 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_ldst0_7) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src2_i$60 = int_src1__data_o; endcase @@ -45441,7 +45441,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_shiftrot0_8$next = rp_INT_rabc_shiftrot0_8; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_shiftrot0_8$next = 1'h0; @@ -45450,9 +45450,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src3_i = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_shiftrot0_8) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: fus_src3_i = int_src1__data_o; endcase @@ -45460,7 +45460,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_ldst0_9$next = rp_INT_rabc_ldst0_9; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_ldst0_9$next = 1'h0; @@ -45469,9 +45469,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$61 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_ldst0_9) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src3_i$61 = int_src1__data_o; endcase @@ -45479,7 +45479,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_alu0_10$next = rp_INT_rabc_alu0_10; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_alu0_10$next = 1'h0; @@ -45488,9 +45488,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src1_i = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_alu0_10) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: fus_src1_i = int_src1__data_o; endcase @@ -45498,7 +45498,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_cr0_11$next = rp_INT_rabc_cr0_11; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_cr0_11$next = 1'h0; @@ -45507,9 +45507,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$62 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_cr0_11) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src1_i$62 = int_src1__data_o; endcase @@ -45517,7 +45517,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_trap0_12$next = rp_INT_rabc_trap0_12; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_trap0_12$next = 1'h0; @@ -45526,9 +45526,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$63 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_trap0_12) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src1_i$63 = int_src1__data_o; endcase @@ -45536,7 +45536,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_logical0_13$next = rp_INT_rabc_logical0_13; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_logical0_13$next = 1'h0; @@ -45545,9 +45545,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$64 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_logical0_13) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src1_i$64 = int_src1__data_o; endcase @@ -45555,7 +45555,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_spr0_14$next = rp_INT_rabc_spr0_14; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_spr0_14$next = 1'h0; @@ -45564,9 +45564,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$67 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_spr0_14) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src1_i$67 = int_src1__data_o; endcase @@ -45574,7 +45574,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_div0_15$next = rp_INT_rabc_div0_15; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_div0_15$next = 1'h0; @@ -45583,9 +45583,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$68 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_div0_15) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src1_i$68 = int_src1__data_o; endcase @@ -45593,7 +45593,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_mul0_16$next = rp_INT_rabc_mul0_16; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_mul0_16$next = 1'h0; @@ -45602,9 +45602,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$69 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_mul0_16) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src1_i$69 = int_src1__data_o; endcase @@ -45612,7 +45612,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_shiftrot0_17$next = rp_INT_rabc_shiftrot0_17; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_shiftrot0_17$next = 1'h0; @@ -45621,9 +45621,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$70 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_shiftrot0_17) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src1_i$70 = int_src1__data_o; endcase @@ -45631,7 +45631,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_ldst0_18$next = rp_INT_rabc_ldst0_18; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_ldst0_18$next = 1'h0; @@ -45640,9 +45640,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$71 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_INT_rabc_ldst0_18) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src1_i$71 = int_src1__data_o; endcase @@ -45650,7 +45650,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_alu0_0$next = rp_XER_xer_so_alu0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_alu0_0$next = 1'h0; @@ -45659,9 +45659,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$72 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_XER_xer_so_alu0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src3_i$72 = xer_src1__data_o[0]; endcase @@ -45669,7 +45669,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_logical0_1$next = rp_XER_xer_so_logical0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_logical0_1$next = 1'h0; @@ -45678,9 +45678,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$73 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_XER_xer_so_logical0_1) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src3_i$73 = xer_src1__data_o[0]; endcase @@ -45688,7 +45688,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_spr0_2$next = rp_XER_xer_so_spr0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_spr0_2$next = 1'h0; @@ -45697,9 +45697,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src4_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_XER_xer_so_spr0_2) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: fus_src4_i = xer_src1__data_o[0]; endcase @@ -45707,7 +45707,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_div0_3$next = rp_XER_xer_so_div0_3; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_div0_3$next = 1'h0; @@ -45716,9 +45716,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$74 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_XER_xer_so_div0_3) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src3_i$74 = xer_src1__data_o[0]; endcase @@ -45726,7 +45726,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_mul0_4$next = rp_XER_xer_so_mul0_4; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_mul0_4$next = 1'h0; @@ -45735,9 +45735,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$75 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_XER_xer_so_mul0_4) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src3_i$75 = xer_src1__data_o[0]; endcase @@ -45745,7 +45745,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_shiftrot0_5$next = rp_XER_xer_so_shiftrot0_5; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_shiftrot0_5$next = 1'h0; @@ -45754,9 +45754,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src4_i$76 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_XER_xer_so_shiftrot0_5) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src4_i$76 = xer_src1__data_o[0]; endcase @@ -45764,7 +45764,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ca_alu0_0$next = rp_XER_xer_ca_alu0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ca_alu0_0$next = 1'h0; @@ -45773,9 +45773,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src4_i$77 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_XER_xer_ca_alu0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src4_i$77 = xer_src2__data_o; endcase @@ -45783,7 +45783,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ca_spr0_1$next = rp_XER_xer_ca_spr0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ca_spr0_1$next = 1'h0; @@ -45792,9 +45792,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src6_i = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_XER_xer_ca_spr0_1) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: fus_src6_i = xer_src2__data_o; endcase @@ -45802,7 +45802,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ca_shiftrot0_2$next = rp_XER_xer_ca_shiftrot0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ca_shiftrot0_2$next = 1'h0; @@ -45811,9 +45811,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src5_i = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_XER_xer_ca_shiftrot0_2) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: fus_src5_i = xer_src2__data_o; endcase @@ -45821,7 +45821,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ov_spr0_0$next = rp_XER_xer_ov_spr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ov_spr0_0$next = 1'h0; @@ -45830,9 +45830,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src5_i$78 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_XER_xer_ov_spr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src5_i$78 = xer_src3__data_o; endcase @@ -45840,7 +45840,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_full_cr_cr0_0$next = rp_CR_full_cr_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_CR_full_cr_cr0_0$next = 1'h0; @@ -45849,9 +45849,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$79 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_CR_full_cr_cr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src3_i$79 = cr_full_rd__data_o; endcase @@ -45859,7 +45859,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_cr_a_cr0_0$next = rp_CR_cr_a_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_CR_cr_a_cr0_0$next = 1'h0; @@ -45868,9 +45868,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src4_i$80 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_CR_cr_a_cr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src4_i$80 = cr_src1__data_o; endcase @@ -45878,7 +45878,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_cr_a_branch0_1$next = rp_CR_cr_a_branch0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_CR_cr_a_branch0_1$next = 1'h0; @@ -45887,9 +45887,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$83 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_CR_cr_a_branch0_1) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src3_i$83 = cr_src1__data_o; endcase @@ -45897,7 +45897,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_cr_b_cr0_0$next = rp_CR_cr_b_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_CR_cr_b_cr0_0$next = 1'h0; @@ -45906,29 +45906,29 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \counter$next = counter; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) casez (\$221 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" */ 1'h1: \counter$next = \$223 [1:0]; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: \counter$next = 2'h2; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \counter$next = 2'h0; @@ -45937,9 +45937,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src5_i$84 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_CR_cr_b_cr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src5_i$84 = cr_src2__data_o; endcase @@ -45947,7 +45947,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_cr_c_cr0_0$next = rp_CR_cr_c_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_CR_cr_c_cr0_0$next = 1'h0; @@ -45956,9 +45956,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src6_i$85 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_CR_cr_c_cr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src6_i$85 = cr_src3__data_o; endcase @@ -45966,88 +45966,88 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end corebusy_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) casez (\$226 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" */ 1'h1: corebusy_o = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: corebusy_o = 1'h1; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: begin - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: corebusy_o = fus_cu_busy_o; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: corebusy_o = \fus_cu_busy_o$14 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: corebusy_o = \fus_cu_busy_o$17 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: corebusy_o = \fus_cu_busy_o$20 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: corebusy_o = \fus_cu_busy_o$23 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: corebusy_o = \fus_cu_busy_o$26 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: corebusy_o = \fus_cu_busy_o$29 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: corebusy_o = \fus_cu_busy_o$32 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: corebusy_o = \fus_cu_busy_o$35 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: corebusy_o = \fus_cu_busy_o$38 ; endcase @@ -46058,7 +46058,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_branch0_0$next = rp_FAST_fast1_branch0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_branch0_0$next = 1'h0; @@ -46067,9 +46067,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$86 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_FAST_fast1_branch0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src1_i$86 = fast_src1__data_o; endcase @@ -46077,19 +46077,19 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \core_terminate_o$next = core_terminate_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: \core_terminate_o$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \core_terminate_o$next = 1'h0; @@ -46098,7 +46098,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_trap0_1$next = rp_FAST_fast1_trap0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_trap0_1$next = 1'h0; @@ -46107,9 +46107,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$87 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_FAST_fast1_trap0_1) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src3_i$87 = fast_src1__data_o; endcase @@ -46117,7 +46117,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_spr0_2$next = rp_FAST_fast1_spr0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_spr0_2$next = 1'h0; @@ -46126,9 +46126,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$88 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_FAST_fast1_spr0_2) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src3_i$88 = fast_src1__data_o; endcase @@ -46136,27 +46136,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__insn_type = dec_ALU_ALU__insn_type; endcase @@ -46166,7 +46166,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_branch0_3$next = rp_FAST_fast1_branch0_3; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_branch0_3$next = 1'h0; @@ -46175,9 +46175,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$89 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_FAST_fast1_branch0_3) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src2_i$89 = fast_src1__data_o; endcase @@ -46185,7 +46185,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_trap0_4$next = rp_FAST_fast1_trap0_4; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_trap0_4$next = 1'h0; @@ -46194,9 +46194,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src4_i$90 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_FAST_fast1_trap0_4) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src4_i$90 = fast_src1__data_o; endcase @@ -46204,27 +46204,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__fn_unit = dec_ALU_ALU__fn_unit; endcase @@ -46234,7 +46234,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_SPR_spr1_spr0_0$next = rp_SPR_spr1_spr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_SPR_spr1_spr0_0$next = 1'h0; @@ -46243,9 +46243,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$91 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) casez (dp_SPR_spr1_spr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ 1'h1: \fus_src2_i$91 = spr_spr1__data_o; endcase @@ -46254,27 +46254,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_alu0__imm_data__data = 64'h0000000000000000; fus_oper_i_alu_alu0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_alu0__imm_data__ok, fus_oper_i_alu_alu0__imm_data__data } = { dec_ALU_ALU__imm_data__ok, dec_ALU_ALU__imm_data__data }; endcase @@ -46284,7 +46284,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$next = wr_pick; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$next = 1'h0; @@ -46293,7 +46293,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$989$next = \wr_pick$986 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$989$next = 1'h0; @@ -46302,7 +46302,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1008$next = \wr_pick$1005 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1008$next = 1'h0; @@ -46312,27 +46312,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_alu0__rc__rc = 1'h0; fus_oper_i_alu_alu0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_alu0__rc__ok, fus_oper_i_alu_alu0__rc__rc } = { dec_ALU_ALU__rc__ok, dec_ALU_ALU__rc__rc }; endcase @@ -46342,7 +46342,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1029$next = \wr_pick$1026 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1029$next = 1'h0; @@ -46351,7 +46351,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1047$next = \wr_pick$1044 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1047$next = 1'h0; @@ -46360,7 +46360,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1069$next = \wr_pick$1066 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1069$next = 1'h0; @@ -46370,27 +46370,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_alu0__oe__oe = 1'h0; fus_oper_i_alu_alu0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_alu0__oe__ok, fus_oper_i_alu_alu0__oe__oe } = { dec_ALU_ALU__oe__ok, dec_ALU_ALU__oe__oe }; endcase @@ -46400,7 +46400,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1089$next = \wr_pick$1086 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1089$next = 1'h0; @@ -46409,7 +46409,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1109$next = \wr_pick$1106 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1109$next = 1'h0; @@ -46418,7 +46418,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1128$next = \wr_pick$1125 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1128$next = 1'h0; @@ -46427,27 +46427,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__invert_in = dec_ALU_ALU__invert_in; endcase @@ -46457,7 +46457,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1146$next = \wr_pick$1143 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1146$next = 1'h0; @@ -46466,27 +46466,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__zero_a = dec_ALU_ALU__zero_a; endcase @@ -46496,7 +46496,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1220$next = \wr_pick$1217 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1220$next = 1'h0; @@ -46505,27 +46505,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__invert_out = dec_ALU_ALU__invert_out; endcase @@ -46535,7 +46535,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1248$next = \wr_pick$1245 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1248$next = 1'h0; @@ -46544,27 +46544,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__write_cr0 = dec_ALU_ALU__write_cr0; endcase @@ -46574,7 +46574,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1268$next = \wr_pick$1265 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1268$next = 1'h0; @@ -46583,7 +46583,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1288$next = \wr_pick$1285 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1288$next = 1'h0; @@ -46592,27 +46592,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__input_carry = dec_ALU_ALU__input_carry; endcase @@ -46622,7 +46622,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1308$next = \wr_pick$1305 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1308$next = 1'h0; @@ -46631,7 +46631,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1328$next = \wr_pick$1325 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1328$next = 1'h0; @@ -46640,27 +46640,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__output_carry = dec_ALU_ALU__output_carry; endcase @@ -46670,7 +46670,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1348$next = \wr_pick$1345 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1348$next = 1'h0; @@ -46679,27 +46679,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__is_32bit = dec_ALU_ALU__is_32bit; endcase @@ -46709,7 +46709,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1395$next = \wr_pick$1392 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1395$next = 1'h0; @@ -46718,27 +46718,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__is_signed = dec_ALU_ALU__is_signed; endcase @@ -46748,7 +46748,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1411$next = \wr_pick$1408 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1411$next = 1'h0; @@ -46757,7 +46757,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1427$next = \wr_pick$1424 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1427$next = 1'h0; @@ -46766,27 +46766,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__data_len = dec_ALU_ALU__data_len; endcase @@ -46796,7 +46796,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1461$next = \wr_pick$1458 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1461$next = 1'h0; @@ -46805,27 +46805,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_alu0__insn = dec_ALU_ALU__insn; endcase @@ -46835,7 +46835,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1477$next = \wr_pick$1474 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1477$next = 1'h0; @@ -46844,7 +46844,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1493$next = \wr_pick$1490 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1493$next = 1'h0; @@ -46853,27 +46853,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_cu_issue_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_cu_issue_i = issue_i; endcase @@ -46883,7 +46883,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1509$next = \wr_pick$1506 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1509$next = 1'h0; @@ -46892,27 +46892,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_cu_rdmaskn_i = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_cu_rdmaskn_i = \$228 ; endcase @@ -46922,7 +46922,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1545$next = \wr_pick$1542 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1545$next = 1'h0; @@ -46931,7 +46931,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1561$next = \wr_pick$1558 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1561$next = 1'h0; @@ -46940,27 +46940,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_cr0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_cr0__insn_type = dec_CR_CR__insn_type; endcase @@ -46970,7 +46970,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1577$next = \wr_pick$1574 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1577$next = 1'h0; @@ -46979,27 +46979,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_cr0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_cr0__fn_unit = dec_CR_CR__fn_unit; endcase @@ -47009,7 +47009,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1593$next = \wr_pick$1590 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1593$next = 1'h0; @@ -47018,7 +47018,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1635$next = \wr_pick$1632 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1635$next = 1'h0; @@ -47027,27 +47027,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_cr0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_cr0__insn = dec_CR_CR__insn; endcase @@ -47057,7 +47057,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1654$next = \wr_pick$1651 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1654$next = 1'h0; @@ -47066,27 +47066,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_issue_i$13 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_issue_i$13 = issue_i; endcase @@ -47096,7 +47096,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1670$next = \wr_pick$1667 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1670$next = 1'h0; @@ -47105,7 +47105,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1686$next = \wr_pick$1683 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1686$next = 1'h0; @@ -47114,27 +47114,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$15 = 6'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_rdmaskn_i$15 = \$250 ; endcase @@ -47144,7 +47144,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1702$next = \wr_pick$1699 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1702$next = 1'h0; @@ -47153,27 +47153,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_branch0__cia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_branch0__cia = dec_BRANCH_BRANCH__cia; endcase @@ -47183,7 +47183,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1746$next = \wr_pick$1743 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1746$next = 1'h0; @@ -47192,27 +47192,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_branch0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_branch0__insn_type = dec_BRANCH_BRANCH__insn_type; endcase @@ -47222,7 +47222,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1762$next = \wr_pick$1759 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1762$next = 1'h0; @@ -47231,7 +47231,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1786$next = \wr_pick$1783 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1786$next = 1'h0; @@ -47240,27 +47240,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_branch0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_branch0__fn_unit = dec_BRANCH_BRANCH__fn_unit; endcase @@ -47270,7 +47270,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1806$next = \wr_pick$1803 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1806$next = 1'h0; @@ -47279,27 +47279,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_branch0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_branch0__insn = dec_BRANCH_BRANCH__insn; endcase @@ -47310,27 +47310,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_branch0__imm_data__data = 64'h0000000000000000; fus_oper_i_alu_branch0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_branch0__imm_data__ok, fus_oper_i_alu_branch0__imm_data__data } = { dec_BRANCH_BRANCH__imm_data__ok, dec_BRANCH_BRANCH__imm_data__data }; endcase @@ -47340,27 +47340,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_branch0__lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_branch0__lk = dec_BRANCH_BRANCH__lk; endcase @@ -47370,27 +47370,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_branch0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_branch0__is_32bit = dec_BRANCH_BRANCH__is_32bit; endcase @@ -47400,27 +47400,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_issue_i$16 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_issue_i$16 = issue_i; endcase @@ -47430,27 +47430,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$18 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_rdmaskn_i$18 = \$252 ; endcase @@ -47460,27 +47460,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_trap0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_trap0__insn_type = core_core_insn_type; endcase @@ -47490,27 +47490,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_trap0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_trap0__fn_unit = core_core_fn_unit; endcase @@ -47520,27 +47520,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_trap0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_trap0__insn = core_core_insn; endcase @@ -47550,27 +47550,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_trap0__msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_trap0__msr = core_core_msr; endcase @@ -47580,27 +47580,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_trap0__cia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_trap0__cia = core_core_cia; endcase @@ -47610,27 +47610,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_trap0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_trap0__is_32bit = core_core_is_32bit; endcase @@ -47640,27 +47640,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_trap0__traptype = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_trap0__traptype = core_core_traptype; endcase @@ -47670,27 +47670,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_trap0__trapaddr = 13'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_trap0__trapaddr = core_core_trapaddr; endcase @@ -47700,27 +47700,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_trap0__ldst_exc = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_trap0__ldst_exc = { \core_core_exc_$signal$9 , \core_core_exc_$signal$8 , \core_core_exc_$signal$7 , \core_core_exc_$signal$6 , \core_core_exc_$signal$5 , \core_core_exc_$signal$4 , \core_core_exc_$signal$3 , \core_core_exc_$signal }; endcase @@ -47730,27 +47730,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_issue_i$19 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_issue_i$19 = issue_i; endcase @@ -47760,27 +47760,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$21 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: \fus_cu_rdmaskn_i$21 = \$254 ; endcase @@ -47790,27 +47790,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__insn_type = dec_LOGICAL_LOGICAL__insn_type; endcase @@ -47820,27 +47820,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__fn_unit = dec_LOGICAL_LOGICAL__fn_unit; endcase @@ -47851,27 +47851,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_logical0__imm_data__data = 64'h0000000000000000; fus_oper_i_alu_logical0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_logical0__imm_data__ok, fus_oper_i_alu_logical0__imm_data__data } = { dec_LOGICAL_LOGICAL__imm_data__ok, dec_LOGICAL_LOGICAL__imm_data__data }; endcase @@ -47882,27 +47882,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_logical0__rc__rc = 1'h0; fus_oper_i_alu_logical0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_logical0__rc__ok, fus_oper_i_alu_logical0__rc__rc } = { dec_LOGICAL_LOGICAL__rc__ok, dec_LOGICAL_LOGICAL__rc__rc }; endcase @@ -47913,27 +47913,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_logical0__oe__oe = 1'h0; fus_oper_i_alu_logical0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: { fus_oper_i_alu_logical0__oe__ok, fus_oper_i_alu_logical0__oe__oe } = { dec_LOGICAL_LOGICAL__oe__ok, dec_LOGICAL_LOGICAL__oe__oe }; endcase @@ -47943,27 +47943,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__invert_in = dec_LOGICAL_LOGICAL__invert_in; endcase @@ -47973,27 +47973,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__zero_a = dec_LOGICAL_LOGICAL__zero_a; endcase @@ -48003,27 +48003,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__input_carry = dec_LOGICAL_LOGICAL__input_carry; endcase @@ -48033,27 +48033,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__invert_out = dec_LOGICAL_LOGICAL__invert_out; endcase @@ -48063,27 +48063,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: fus_oper_i_alu_logical0__write_cr0 = dec_LOGICAL_LOGICAL__write_cr0; endcase @@ -48707,9 +48707,9 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] data_i; @@ -48983,17 +48983,17 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r wire [3:0] reg_7_w7__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire reg_7_w7__wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] ren_delay = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] \ren_delay$17 = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] \ren_delay$17$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] \ren_delay$34 = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] \ren_delay$34$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [3:0] src1__data_o; @@ -49207,7 +49207,7 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end \ren_delay$17$next = src2__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$17$next = 8'h00; @@ -49216,9 +49216,9 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end src2__data_o = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$18 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src2__data_o = \$32 ; endcase @@ -49226,7 +49226,7 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end \ren_delay$34$next = src3__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$34$next = 8'h00; @@ -49235,9 +49235,9 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end src3__data_o = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$35 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src3__data_o = \$49 ; endcase @@ -49245,7 +49245,7 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end \ren_delay$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 8'h00; @@ -49254,9 +49254,9 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end src1__data_o = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src1__data_o = \$15 ; endcase @@ -49420,7 +49420,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope wire all_rd_pulse; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire all_rd_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] alu_cr0_cr_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [3:0] \alu_cr0_cr_a$2 ; @@ -49530,7 +49530,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope reg [6:0] alu_cr0_cr_op__insn_type = 7'h00; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg [6:0] \alu_cr0_cr_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [31:0] alu_cr0_full_cr; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [31:0] \alu_cr0_full_cr$1 ; @@ -49538,7 +49538,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope wire alu_cr0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_cr0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_cr0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_cr0_p_ready_o; @@ -49576,11 +49576,11 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -49637,9 +49637,9 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [3:0] dest3_o; reg [3:0] dest3_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output full_cr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -50038,7 +50038,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -50047,7 +50047,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -50056,7 +50056,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -50065,7 +50065,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -50074,7 +50074,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -50083,7 +50083,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -50092,7 +50092,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 6'h00; @@ -50101,7 +50101,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 6'h3f; @@ -50110,7 +50110,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 3'h0; @@ -50119,7 +50119,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 3'h7; @@ -50153,7 +50153,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -50175,7 +50175,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope 1'h1: { \data_r1__full_cr_ok$next , \data_r1__full_cr$next } = 33'h000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__full_cr_ok$next = 1'h0; @@ -50197,7 +50197,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope 1'h1: { \data_r2__cr_a_ok$next , \data_r2__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__cr_a_ok$next = 1'h0; @@ -50266,7 +50266,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -50275,7 +50275,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$91 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -50314,7 +50314,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 3'h0; @@ -50367,9 +50367,9 @@ module cyc_l(coresync_rst, s_cyc, r_cyc, q_cyc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_cyc; @@ -50395,7 +50395,7 @@ module cyc_l(coresync_rst, s_cyc, r_cyc, q_cyc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -50538,23 +50538,23 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r wire \$97 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) wire \$99 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) input [6:0] core_dbg_core_dbg_dststep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) input [6:0] core_dbg_core_dbg_maxvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) input [6:0] core_dbg_core_dbg_srcstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) input [1:0] core_dbg_core_dbg_subvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) input [1:0] core_dbg_core_dbg_svstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) input [6:0] core_dbg_core_dbg_vl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) input [63:0] core_dbg_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) input [63:0] core_dbg_pc; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" *) output core_rst_o; @@ -50641,7 +50641,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r wire [63:0] log_dmi_data; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" *) wire [31:0] log_write_addr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" *) wire [63:0] stat_reg; @@ -50774,7 +50774,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r always @* begin if (\initial ) begin end \dmi_req_i_1$next = dmi_req_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi_req_i_1$next = 1'h0; @@ -50824,7 +50824,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r 1'h1: \terminated$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \terminated$next = 1'h0; @@ -50868,7 +50868,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r 1'h1: \stopping$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \stopping$next = 1'h0; @@ -50896,7 +50896,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \gspr_index$next = 7'h00; @@ -50930,7 +50930,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r 2'b1?: \log_dmi_addr$next [1:0] = \$117 [1:0]; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \log_dmi_addr$next = 32'd0; @@ -50939,7 +50939,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r always @* begin if (\initial ) begin end \dmi_read_log_data_1$next = dmi_read_log_data; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi_read_log_data_1$next = 1'h0; @@ -50948,7 +50948,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r always @* begin if (\initial ) begin end \dmi_read_log_data$next = \$122 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi_read_log_data$next = 1'h0; @@ -51041,7 +51041,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \do_step$next = 1'h0; @@ -51071,7 +51071,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \do_reset$next = 1'h0; @@ -51101,7 +51101,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \do_icreset$next = 1'h0; @@ -51135,7 +51135,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r 2'b1?: \do_dmi_log_rd$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \do_dmi_log_rd$next = 1'h0; @@ -51156,75 +51156,75 @@ endmodule (* generator = "nMigen" *) module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_function_unit, ALU_in1_sel, ALU_in2_sel, ALU_cr_out, ALU_ldst_len, ALU_inv_a, ALU_inv_out, ALU_cry_in, ALU_cry_out, ALU_is_32b, ALU_sgn, ALU_RA, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_Rc, ALU_OE, ALU_BD, ALU_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire ALU_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] ALU_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [2:0] ALU_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [1:0] ALU_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] ALU_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] ALU_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] ALU_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [7:0] ALU_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire ALU_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [23:0] ALU_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire ALU_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output ALU_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] ALU_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] ALU_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output ALU_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] ALU_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] ALU_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [9:0] ALU_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ALU_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] ALU_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -51235,7 +51235,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] ALU_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -51244,17 +51244,17 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_cr_out; reg [2:0] ALU_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_cry_in; reg [1:0] ALU_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_cry_out; reg ALU_cry_out; (* enum_base_type = "CRInSel" *) @@ -51266,7 +51266,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec19_ALU_dec19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -51275,15 +51275,15 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec19_ALU_dec19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec19_ALU_dec19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec19_ALU_dec19_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -51300,7 +51300,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] ALU_dec19_ALU_dec19_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -51308,7 +51308,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec19_ALU_dec19_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -51325,7 +51325,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec19_ALU_dec19_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -51402,13 +51402,13 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec19_ALU_dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec19_ALU_dec19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec19_ALU_dec19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec19_ALU_dec19_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -51416,17 +51416,17 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec19_ALU_dec19_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec19_ALU_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec19_ALU_dec19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] ALU_dec19_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -51437,7 +51437,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_ALU_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -51446,15 +51446,15 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_ALU_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_ALU_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_ALU_dec31_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -51471,7 +51471,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] ALU_dec31_ALU_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -51479,7 +51479,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_ALU_dec31_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -51496,7 +51496,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_ALU_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -51573,13 +51573,13 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_ALU_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_ALU_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_ALU_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_ALU_dec31_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -51587,17 +51587,17 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_ALU_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_ALU_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_ALU_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] ALU_dec31_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -51614,7 +51614,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] ALU_function_unit; reg [13:0] ALU_function_unit; (* enum_base_type = "In1Sel" *) @@ -51623,7 +51623,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_in1_sel; reg [2:0] ALU_in1_sel; (* enum_base_type = "In2Sel" *) @@ -51641,7 +51641,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_in2_sel; reg [3:0] ALU_in2_sel; (* enum_base_type = "MicrOp" *) @@ -51719,16 +51719,16 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_internal_op; reg [6:0] ALU_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_inv_a; reg ALU_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_inv_out; reg ALU_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_is_32b; reg ALU_is_32b; (* enum_base_type = "LdstLen" *) @@ -51737,626 +51737,626 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_ldst_len; reg [3:0] ALU_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_rc_sel; reg [1:0] ALU_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_sgn; reg ALU_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [5:0] ALU_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; ALU_dec19 ALU_dec19 ( .ALU_dec19_cr_in(ALU_dec19_ALU_dec19_cr_in), .ALU_dec19_cr_out(ALU_dec19_ALU_dec19_cr_out), @@ -52394,33 +52394,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_rc_sel = ALU_dec19_ALU_dec19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_rc_sel = ALU_dec31_ALU_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_rc_sel = 2'h0; endcase @@ -52428,33 +52428,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_cry_in = ALU_dec19_ALU_dec19_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_cry_in = ALU_dec31_ALU_dec31_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_cry_in = 2'h1; endcase @@ -52462,33 +52462,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_inv_a = ALU_dec19_ALU_dec19_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_inv_a = ALU_dec31_ALU_dec31_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_inv_a = 1'h1; endcase @@ -52496,33 +52496,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_inv_out = ALU_dec19_ALU_dec19_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_inv_out = ALU_dec31_ALU_dec31_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_inv_out = 1'h0; endcase @@ -52530,33 +52530,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_cry_out = ALU_dec19_ALU_dec19_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_cry_out = ALU_dec31_ALU_dec31_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_cry_out = 1'h1; endcase @@ -52564,33 +52564,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_is_32b = ALU_dec19_ALU_dec19_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_is_32b = ALU_dec31_ALU_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_is_32b = 1'h0; endcase @@ -52598,33 +52598,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_sgn = ALU_dec19_ALU_dec19_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_sgn = ALU_dec31_ALU_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_sgn = 1'h0; endcase @@ -52632,33 +52632,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_function_unit = ALU_dec19_ALU_dec19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_function_unit = ALU_dec31_ALU_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_function_unit = 14'h0002; endcase @@ -52666,33 +52666,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_internal_op = ALU_dec19_ALU_dec19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_internal_op = ALU_dec31_ALU_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_internal_op = 7'h02; endcase @@ -52700,33 +52700,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_in1_sel = ALU_dec19_ALU_dec19_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_in1_sel = ALU_dec31_ALU_dec31_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_in1_sel = 3'h1; endcase @@ -52734,33 +52734,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_in2_sel = ALU_dec19_ALU_dec19_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_in2_sel = ALU_dec31_ALU_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_in2_sel = 4'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_in2_sel = 4'h3; endcase @@ -52768,33 +52768,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_cr_in = ALU_dec19_ALU_dec19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_cr_in = ALU_dec31_ALU_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_cr_in = 3'h0; endcase @@ -52802,33 +52802,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_cr_out = ALU_dec19_ALU_dec19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_cr_out = ALU_dec31_ALU_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_cr_out = 3'h0; endcase @@ -52836,33 +52836,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ALU_ldst_len = ALU_dec19_ALU_dec19_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ALU_ldst_len = ALU_dec31_ALU_dec31_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ALU_ldst_len = 4'h0; endcase @@ -53210,105 +53210,105 @@ endmodule (* generator = "nMigen" *) module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_function_unit, CR_cr_out, CR_Rc, CR_OE, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire CR_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] CR_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [2:0] CR_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [1:0] CR_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] CR_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] CR_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] CR_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [7:0] CR_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire CR_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [23:0] CR_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire CR_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output CR_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] CR_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output CR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] CR_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [9:0] CR_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] CR_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] CR_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -53319,7 +53319,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] CR_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -53328,7 +53328,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_cr_out; reg [2:0] CR_cr_out; (* enum_base_type = "CRInSel" *) @@ -53340,7 +53340,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec19_CR_dec19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -53349,7 +53349,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec19_CR_dec19_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -53366,7 +53366,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] CR_dec19_CR_dec19_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -53443,15 +53443,15 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec19_CR_dec19_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec19_CR_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] CR_dec19_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -53462,7 +53462,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_CR_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -53471,7 +53471,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_CR_dec31_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -53488,7 +53488,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] CR_dec31_CR_dec31_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -53565,15 +53565,15 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec31_CR_dec31_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec31_CR_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] CR_dec31_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -53590,7 +53590,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] CR_function_unit; reg [13:0] CR_function_unit; (* enum_base_type = "MicrOp" *) @@ -53668,593 +53668,593 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_internal_op; reg [6:0] CR_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_rc_sel; reg [1:0] CR_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] CR_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; CR_dec19 CR_dec19 ( .CR_dec19_cr_in(CR_dec19_CR_dec19_cr_in), .CR_dec19_cr_out(CR_dec19_CR_dec19_cr_out), @@ -54274,12 +54274,12 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun always @* begin if (\initial ) begin end CR_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: CR_function_unit = CR_dec19_CR_dec19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: CR_function_unit = CR_dec31_CR_dec31_function_unit; endcase @@ -54287,12 +54287,12 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun always @* begin if (\initial ) begin end CR_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: CR_internal_op = CR_dec19_CR_dec19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: CR_internal_op = CR_dec31_CR_dec31_internal_op; endcase @@ -54300,12 +54300,12 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun always @* begin if (\initial ) begin end CR_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: CR_cr_in = CR_dec19_CR_dec19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: CR_cr_in = CR_dec31_CR_dec31_cr_in; endcase @@ -54313,12 +54313,12 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun always @* begin if (\initial ) begin end CR_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: CR_cr_out = CR_dec19_CR_dec19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: CR_cr_out = CR_dec31_CR_dec31_cr_out; endcase @@ -54326,12 +54326,12 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun always @* begin if (\initial ) begin end CR_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: CR_rc_sel = CR_dec19_CR_dec19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: CR_rc_sel = CR_dec31_CR_dec31_rc_sel; endcase @@ -54679,95 +54679,95 @@ endmodule (* generator = "nMigen" *) module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH_SPR, BRANCH_function_unit, BRANCH_in2_sel, BRANCH_cr_out, BRANCH_is_32b, BRANCH_lk, BRANCH_LK, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_sh, BRANCH_LI, BRANCH_Rc, BRANCH_OE, BRANCH_BD, BRANCH_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire BRANCH_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] BRANCH_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [2:0] BRANCH_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [1:0] BRANCH_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] BRANCH_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] BRANCH_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] BRANCH_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [7:0] BRANCH_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire BRANCH_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [23:0] BRANCH_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output BRANCH_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output BRANCH_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] BRANCH_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output BRANCH_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] BRANCH_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] BRANCH_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [9:0] BRANCH_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] BRANCH_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] BRANCH_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -54778,7 +54778,7 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] BRANCH_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -54787,7 +54787,7 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] BRANCH_cr_out; reg [2:0] BRANCH_cr_out; (* enum_base_type = "CRInSel" *) @@ -54799,7 +54799,7 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] BRANCH_dec19_BRANCH_dec19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -54808,7 +54808,7 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] BRANCH_dec19_BRANCH_dec19_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -54825,7 +54825,7 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] BRANCH_dec19_BRANCH_dec19_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -54842,7 +54842,7 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] BRANCH_dec19_BRANCH_dec19_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -54919,19 +54919,19 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] BRANCH_dec19_BRANCH_dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire BRANCH_dec19_BRANCH_dec19_is_32b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire BRANCH_dec19_BRANCH_dec19_lk; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] BRANCH_dec19_BRANCH_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] BRANCH_dec19_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -54948,7 +54948,7 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] BRANCH_function_unit; reg [13:0] BRANCH_function_unit; (* enum_base_type = "In2Sel" *) @@ -54966,7 +54966,7 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] BRANCH_in2_sel; reg [3:0] BRANCH_in2_sel; (* enum_base_type = "MicrOp" *) @@ -55044,609 +55044,609 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] BRANCH_internal_op; reg [6:0] BRANCH_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output BRANCH_is_32b; reg BRANCH_is_32b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output BRANCH_lk; reg BRANCH_lk; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] BRANCH_rc_sel; reg [1:0] BRANCH_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [5:0] BRANCH_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; BRANCH_dec19 BRANCH_dec19 ( .BRANCH_dec19_cr_in(BRANCH_dec19_BRANCH_dec19_cr_in), .BRANCH_dec19_cr_out(BRANCH_dec19_BRANCH_dec19_cr_out), @@ -55661,15 +55661,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: BRANCH_function_unit = BRANCH_dec19_BRANCH_dec19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: BRANCH_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: BRANCH_function_unit = 14'h0020; endcase @@ -55677,15 +55677,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: BRANCH_internal_op = BRANCH_dec19_BRANCH_dec19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: BRANCH_internal_op = 7'h06; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: BRANCH_internal_op = 7'h07; endcase @@ -55693,15 +55693,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: BRANCH_in2_sel = BRANCH_dec19_BRANCH_dec19_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: BRANCH_in2_sel = 4'h6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: BRANCH_in2_sel = 4'h7; endcase @@ -55709,15 +55709,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: BRANCH_cr_in = BRANCH_dec19_BRANCH_dec19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: BRANCH_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: BRANCH_cr_in = 3'h2; endcase @@ -55725,15 +55725,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: BRANCH_cr_out = BRANCH_dec19_BRANCH_dec19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: BRANCH_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: BRANCH_cr_out = 3'h0; endcase @@ -55741,15 +55741,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: BRANCH_rc_sel = BRANCH_dec19_BRANCH_dec19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: BRANCH_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: BRANCH_rc_sel = 2'h0; endcase @@ -55757,15 +55757,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: BRANCH_is_32b = BRANCH_dec19_BRANCH_dec19_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: BRANCH_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: BRANCH_is_32b = 1'h0; endcase @@ -55773,15 +55773,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: BRANCH_lk = BRANCH_dec19_BRANCH_dec19_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: BRANCH_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: BRANCH_lk = 1'h1; endcase @@ -56128,195 +56128,195 @@ endmodule (* generator = "nMigen" *) module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGICAL_SPR, LOGICAL_function_unit, LOGICAL_in1_sel, LOGICAL_in2_sel, LOGICAL_cr_out, LOGICAL_ldst_len, LOGICAL_inv_a, LOGICAL_inv_out, LOGICAL_cry_in, LOGICAL_cry_out, LOGICAL_is_32b, LOGICAL_sgn, LOGICAL_RA, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGICAL_sh, LOGICAL_LI, LOGICAL_Rc, LOGICAL_OE, LOGICAL_BD, LOGICAL_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire LOGICAL_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] LOGICAL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [2:0] LOGICAL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [1:0] LOGICAL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] LOGICAL_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] LOGICAL_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] LOGICAL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [7:0] LOGICAL_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire LOGICAL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [23:0] LOGICAL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire LOGICAL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output LOGICAL_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] LOGICAL_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] LOGICAL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output LOGICAL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] LOGICAL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] LOGICAL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [9:0] LOGICAL_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LOGICAL_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] LOGICAL_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -56327,7 +56327,7 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] LOGICAL_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -56336,17 +56336,17 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_cr_out; reg [2:0] LOGICAL_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_cry_in; reg [1:0] LOGICAL_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_cry_out; reg LOGICAL_cry_out; (* enum_base_type = "CRInSel" *) @@ -56358,7 +56358,7 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_LOGICAL_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -56367,15 +56367,15 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_LOGICAL_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_LOGICAL_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_LOGICAL_dec31_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -56392,7 +56392,7 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] LOGICAL_dec31_LOGICAL_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -56400,7 +56400,7 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_LOGICAL_dec31_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -56417,7 +56417,7 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_LOGICAL_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -56494,13 +56494,13 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LOGICAL_dec31_LOGICAL_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_LOGICAL_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_LOGICAL_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_LOGICAL_dec31_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -56508,17 +56508,17 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_LOGICAL_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_LOGICAL_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_LOGICAL_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] LOGICAL_dec31_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -56535,7 +56535,7 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LOGICAL_function_unit; reg [13:0] LOGICAL_function_unit; (* enum_base_type = "In1Sel" *) @@ -56544,7 +56544,7 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_in1_sel; reg [2:0] LOGICAL_in1_sel; (* enum_base_type = "In2Sel" *) @@ -56562,7 +56562,7 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_in2_sel; reg [3:0] LOGICAL_in2_sel; (* enum_base_type = "MicrOp" *) @@ -56640,16 +56640,16 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LOGICAL_internal_op; reg [6:0] LOGICAL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_inv_a; reg LOGICAL_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_inv_out; reg LOGICAL_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_is_32b; reg LOGICAL_is_32b; (* enum_base_type = "LdstLen" *) @@ -56658,506 +56658,506 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_ldst_len; reg [3:0] LOGICAL_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_rc_sel; reg [1:0] LOGICAL_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_sgn; reg LOGICAL_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [5:0] LOGICAL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; LOGICAL_dec31 LOGICAL_dec31 ( .LOGICAL_dec31_cr_in(LOGICAL_dec31_LOGICAL_dec31_cr_in), .LOGICAL_dec31_cr_out(LOGICAL_dec31_LOGICAL_dec31_cr_out), @@ -57178,27 +57178,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_cry_in = LOGICAL_dec31_LOGICAL_dec31_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_cry_in = 2'h0; endcase @@ -57206,27 +57206,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_inv_a = LOGICAL_dec31_LOGICAL_dec31_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_inv_a = 1'h0; endcase @@ -57234,27 +57234,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_inv_out = LOGICAL_dec31_LOGICAL_dec31_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_inv_out = 1'h0; endcase @@ -57262,27 +57262,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_cry_out = LOGICAL_dec31_LOGICAL_dec31_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_cry_out = 1'h0; endcase @@ -57290,27 +57290,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_is_32b = LOGICAL_dec31_LOGICAL_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_is_32b = 1'h0; endcase @@ -57318,27 +57318,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_sgn = LOGICAL_dec31_LOGICAL_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_sgn = 1'h0; endcase @@ -57346,27 +57346,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_function_unit = LOGICAL_dec31_LOGICAL_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_function_unit = 14'h0010; endcase @@ -57374,27 +57374,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_internal_op = LOGICAL_dec31_LOGICAL_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_internal_op = 7'h43; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_internal_op = 7'h43; endcase @@ -57402,27 +57402,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_in1_sel = LOGICAL_dec31_LOGICAL_dec31_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_in1_sel = 3'h4; endcase @@ -57430,27 +57430,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_in2_sel = LOGICAL_dec31_LOGICAL_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_in2_sel = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_in2_sel = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_in2_sel = 4'h4; endcase @@ -57458,27 +57458,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_cr_in = LOGICAL_dec31_LOGICAL_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_cr_in = 3'h0; endcase @@ -57486,27 +57486,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_cr_out = LOGICAL_dec31_LOGICAL_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_cr_out = 3'h0; endcase @@ -57514,27 +57514,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_ldst_len = LOGICAL_dec31_LOGICAL_dec31_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_ldst_len = 4'h0; endcase @@ -57542,27 +57542,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LOGICAL_rc_sel = LOGICAL_dec31_LOGICAL_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: LOGICAL_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: LOGICAL_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: LOGICAL_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: LOGICAL_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: LOGICAL_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: LOGICAL_rc_sel = 2'h0; endcase @@ -57909,251 +57909,251 @@ endmodule (* generator = "nMigen" *) module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR_function_unit, SPR_cr_out, SPR_is_32b, SPR_Rc, SPR_OE, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire SPR_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] SPR_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [2:0] SPR_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [1:0] SPR_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] SPR_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] SPR_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] SPR_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [7:0] SPR_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire SPR_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [23:0] SPR_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire SPR_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output SPR_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] SPR_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output SPR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] SPR_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [9:0] SPR_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SPR_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] SPR_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -58164,7 +58164,7 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] SPR_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -58173,7 +58173,7 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SPR_cr_out; reg [2:0] SPR_cr_out; (* enum_base_type = "CRInSel" *) @@ -58185,7 +58185,7 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SPR_dec31_SPR_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -58194,7 +58194,7 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SPR_dec31_SPR_dec31_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -58211,7 +58211,7 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] SPR_dec31_SPR_dec31_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -58288,17 +58288,17 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SPR_dec31_SPR_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SPR_dec31_SPR_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SPR_dec31_SPR_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] SPR_dec31_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -58315,7 +58315,7 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] SPR_function_unit; reg [13:0] SPR_function_unit; (* enum_base_type = "MicrOp" *) @@ -58393,450 +58393,450 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SPR_internal_op; reg [6:0] SPR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SPR_is_32b; reg SPR_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SPR_rc_sel; reg [1:0] SPR_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] SPR_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; SPR_dec31 SPR_dec31 ( .SPR_dec31_cr_in(SPR_dec31_SPR_dec31_cr_in), .SPR_dec31_cr_out(SPR_dec31_SPR_dec31_cr_out), @@ -58849,9 +58849,9 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR always @* begin if (\initial ) begin end SPR_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SPR_function_unit = SPR_dec31_SPR_dec31_function_unit; endcase @@ -58859,9 +58859,9 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR always @* begin if (\initial ) begin end SPR_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SPR_internal_op = SPR_dec31_SPR_dec31_internal_op; endcase @@ -58869,9 +58869,9 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR always @* begin if (\initial ) begin end SPR_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SPR_cr_in = SPR_dec31_SPR_dec31_cr_in; endcase @@ -58879,9 +58879,9 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR always @* begin if (\initial ) begin end SPR_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SPR_cr_out = SPR_dec31_SPR_dec31_cr_out; endcase @@ -58889,9 +58889,9 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR always @* begin if (\initial ) begin end SPR_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SPR_rc_sel = SPR_dec31_SPR_dec31_rc_sel; endcase @@ -58899,9 +58899,9 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR always @* begin if (\initial ) begin end SPR_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SPR_is_32b = SPR_dec31_SPR_dec31_is_32b; endcase @@ -59248,105 +59248,105 @@ endmodule (* generator = "nMigen" *) module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV_function_unit, DIV_in1_sel, DIV_in2_sel, DIV_cr_out, DIV_ldst_len, DIV_inv_a, DIV_inv_out, DIV_cry_in, DIV_cry_out, DIV_is_32b, DIV_sgn, DIV_RA, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, DIV_Rc, DIV_OE, DIV_BD, DIV_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire DIV_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] DIV_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [2:0] DIV_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [1:0] DIV_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] DIV_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] DIV_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] DIV_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [7:0] DIV_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire DIV_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [23:0] DIV_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire DIV_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output DIV_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] DIV_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] DIV_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output DIV_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] DIV_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] DIV_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [9:0] DIV_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] DIV_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] DIV_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -59357,7 +59357,7 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] DIV_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -59366,17 +59366,17 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_cr_out; reg [2:0] DIV_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_cry_in; reg [1:0] DIV_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_cry_out; reg DIV_cry_out; (* enum_base_type = "CRInSel" *) @@ -59388,7 +59388,7 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_DIV_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -59397,15 +59397,15 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_DIV_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_DIV_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_DIV_dec31_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -59422,7 +59422,7 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] DIV_dec31_DIV_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -59430,7 +59430,7 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_DIV_dec31_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -59447,7 +59447,7 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_DIV_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -59524,13 +59524,13 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] DIV_dec31_DIV_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_DIV_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_DIV_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_DIV_dec31_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -59538,17 +59538,17 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_DIV_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_DIV_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_DIV_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] DIV_dec31_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -59565,7 +59565,7 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] DIV_function_unit; reg [13:0] DIV_function_unit; (* enum_base_type = "In1Sel" *) @@ -59574,7 +59574,7 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_in1_sel; reg [2:0] DIV_in1_sel; (* enum_base_type = "In2Sel" *) @@ -59592,7 +59592,7 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_in2_sel; reg [3:0] DIV_in2_sel; (* enum_base_type = "MicrOp" *) @@ -59670,16 +59670,16 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] DIV_internal_op; reg [6:0] DIV_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_inv_a; reg DIV_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_inv_out; reg DIV_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_is_32b; reg DIV_is_32b; (* enum_base_type = "LdstLen" *) @@ -59688,596 +59688,596 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_ldst_len; reg [3:0] DIV_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_rc_sel; reg [1:0] DIV_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_sgn; reg DIV_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [5:0] DIV_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; DIV_dec31 DIV_dec31 ( .DIV_dec31_cr_in(DIV_dec31_DIV_dec31_cr_in), .DIV_dec31_cr_out(DIV_dec31_DIV_dec31_cr_out), @@ -60298,9 +60298,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_cry_in = DIV_dec31_DIV_dec31_cry_in; endcase @@ -60308,9 +60308,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_inv_a = DIV_dec31_DIV_dec31_inv_a; endcase @@ -60318,9 +60318,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_inv_out = DIV_dec31_DIV_dec31_inv_out; endcase @@ -60328,9 +60328,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_cry_out = DIV_dec31_DIV_dec31_cry_out; endcase @@ -60338,9 +60338,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_is_32b = DIV_dec31_DIV_dec31_is_32b; endcase @@ -60348,9 +60348,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_sgn = DIV_dec31_DIV_dec31_sgn; endcase @@ -60358,9 +60358,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_function_unit = DIV_dec31_DIV_dec31_function_unit; endcase @@ -60368,9 +60368,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_internal_op = DIV_dec31_DIV_dec31_internal_op; endcase @@ -60378,9 +60378,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_in1_sel = DIV_dec31_DIV_dec31_in1_sel; endcase @@ -60388,9 +60388,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_in2_sel = DIV_dec31_DIV_dec31_in2_sel; endcase @@ -60398,9 +60398,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_cr_in = DIV_dec31_DIV_dec31_cr_in; endcase @@ -60408,9 +60408,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_cr_out = DIV_dec31_DIV_dec31_cr_out; endcase @@ -60418,9 +60418,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_ldst_len = DIV_dec31_DIV_dec31_ldst_len; endcase @@ -60428,9 +60428,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: DIV_rc_sel = DIV_dec31_DIV_dec31_rc_sel; endcase @@ -60777,231 +60777,231 @@ endmodule (* generator = "nMigen" *) module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL_function_unit, MUL_in2_sel, MUL_cr_out, MUL_is_32b, MUL_sgn, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, MUL_Rc, MUL_OE, MUL_BD, MUL_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire MUL_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] MUL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [2:0] MUL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [1:0] MUL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] MUL_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] MUL_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] MUL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [7:0] MUL_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire MUL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [23:0] MUL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire MUL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output MUL_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] MUL_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output MUL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] MUL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] MUL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [9:0] MUL_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MUL_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] MUL_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -61012,7 +61012,7 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] MUL_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -61021,7 +61021,7 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_cr_out; reg [2:0] MUL_cr_out; (* enum_base_type = "CRInSel" *) @@ -61033,7 +61033,7 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_MUL_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -61042,7 +61042,7 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_MUL_dec31_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -61059,7 +61059,7 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] MUL_dec31_MUL_dec31_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -61076,7 +61076,7 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] MUL_dec31_MUL_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -61153,19 +61153,19 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] MUL_dec31_MUL_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_MUL_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] MUL_dec31_MUL_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_MUL_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] MUL_dec31_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -61182,7 +61182,7 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] MUL_function_unit; reg [13:0] MUL_function_unit; (* enum_base_type = "In2Sel" *) @@ -61200,7 +61200,7 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] MUL_in2_sel; reg [3:0] MUL_in2_sel; (* enum_base_type = "MicrOp" *) @@ -61278,473 +61278,473 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] MUL_internal_op; reg [6:0] MUL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_is_32b; reg MUL_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] MUL_rc_sel; reg [1:0] MUL_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_sgn; reg MUL_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [5:0] MUL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; MUL_dec31 MUL_dec31 ( .MUL_dec31_cr_in(MUL_dec31_MUL_dec31_cr_in), .MUL_dec31_cr_out(MUL_dec31_MUL_dec31_cr_out), @@ -61759,12 +61759,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: MUL_function_unit = MUL_dec31_MUL_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: MUL_function_unit = 14'h0100; endcase @@ -61772,12 +61772,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: MUL_internal_op = MUL_dec31_MUL_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: MUL_internal_op = 7'h32; endcase @@ -61785,12 +61785,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: MUL_in2_sel = MUL_dec31_MUL_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: MUL_in2_sel = 4'h3; endcase @@ -61798,12 +61798,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: MUL_cr_in = MUL_dec31_MUL_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: MUL_cr_in = 3'h0; endcase @@ -61811,12 +61811,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: MUL_cr_out = MUL_dec31_MUL_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: MUL_cr_out = 3'h1; endcase @@ -61824,12 +61824,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: MUL_rc_sel = MUL_dec31_MUL_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: MUL_rc_sel = 2'h0; endcase @@ -61837,12 +61837,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: MUL_is_32b = MUL_dec31_MUL_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: MUL_is_32b = 1'h0; endcase @@ -61850,12 +61850,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: MUL_sgn = MUL_dec31_MUL_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: MUL_sgn = 1'h1; endcase @@ -62202,251 +62202,251 @@ endmodule (* generator = "nMigen" *) module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, SHIFT_ROT_SPR, SHIFT_ROT_function_unit, SHIFT_ROT_in2_sel, SHIFT_ROT_cr_out, SHIFT_ROT_cr_in, SHIFT_ROT_inv_a, SHIFT_ROT_cry_in, SHIFT_ROT_cry_out, SHIFT_ROT_is_32b, SHIFT_ROT_sgn, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, SHIFT_ROT_sh, SHIFT_ROT_LI, SHIFT_ROT_Rc, SHIFT_ROT_OE, SHIFT_ROT_BD, SHIFT_ROT_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire SHIFT_ROT_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] SHIFT_ROT_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [2:0] SHIFT_ROT_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [1:0] SHIFT_ROT_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] SHIFT_ROT_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] SHIFT_ROT_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] SHIFT_ROT_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [7:0] SHIFT_ROT_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire SHIFT_ROT_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [23:0] SHIFT_ROT_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire SHIFT_ROT_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output SHIFT_ROT_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] SHIFT_ROT_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output SHIFT_ROT_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] SHIFT_ROT_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] SHIFT_ROT_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [9:0] SHIFT_ROT_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SHIFT_ROT_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] SHIFT_ROT_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -62457,7 +62457,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_cr_in; reg [2:0] SHIFT_ROT_cr_in; (* enum_base_type = "CROutSel" *) @@ -62467,17 +62467,17 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_cr_out; reg [2:0] SHIFT_ROT_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_cry_in; reg [1:0] SHIFT_ROT_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_cry_out; reg SHIFT_ROT_cry_out; (* enum_base_type = "CRInSel" *) @@ -62489,7 +62489,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -62498,15 +62498,15 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -62523,7 +62523,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -62540,7 +62540,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -62617,21 +62617,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] SHIFT_ROT_dec30_opcode_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -62642,7 +62642,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -62651,15 +62651,15 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -62676,7 +62676,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -62693,7 +62693,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -62770,21 +62770,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] SHIFT_ROT_dec31_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -62801,7 +62801,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] SHIFT_ROT_function_unit; reg [13:0] SHIFT_ROT_function_unit; (* enum_base_type = "In2Sel" *) @@ -62819,7 +62819,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_in2_sel; reg [3:0] SHIFT_ROT_in2_sel; (* enum_base_type = "MicrOp" *) @@ -62897,456 +62897,456 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_internal_op; reg [6:0] SHIFT_ROT_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_inv_a; reg SHIFT_ROT_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_is_32b; reg SHIFT_ROT_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_rc_sel; reg [1:0] SHIFT_ROT_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_sgn; reg SHIFT_ROT_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [5:0] SHIFT_ROT_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; SHIFT_ROT_dec30 SHIFT_ROT_dec30 ( .SHIFT_ROT_dec30_cr_in(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in), .SHIFT_ROT_dec30_cr_out(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out), @@ -63378,21 +63378,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_inv_a = SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_inv_a = SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_inv_a = 1'h0; endcase @@ -63400,21 +63400,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_cry_out = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_cry_out = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_cry_out = 1'h0; endcase @@ -63422,21 +63422,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_is_32b = SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_is_32b = SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_is_32b = 1'h1; endcase @@ -63444,21 +63444,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_sgn = SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_sgn = SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_sgn = 1'h0; endcase @@ -63466,21 +63466,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_function_unit = SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_function_unit = SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_function_unit = 14'h0008; endcase @@ -63488,21 +63488,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_internal_op = SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_internal_op = SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_internal_op = 7'h38; endcase @@ -63510,21 +63510,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_in2_sel = SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_in2_sel = SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_in2_sel = 4'h1; endcase @@ -63532,21 +63532,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_cr_in = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_cr_in = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_cr_in = 3'h0; endcase @@ -63554,21 +63554,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_cr_out = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_cr_out = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_cr_out = 3'h1; endcase @@ -63576,21 +63576,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_rc_sel = SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_rc_sel = SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_rc_sel = 2'h2; endcase @@ -63598,21 +63598,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SHIFT_ROT_cry_in = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SHIFT_ROT_cry_in = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SHIFT_ROT_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SHIFT_ROT_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SHIFT_ROT_cry_in = 2'h0; endcase @@ -63960,197 +63960,197 @@ endmodule (* generator = "nMigen" *) module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, LDST_function_unit, LDST_in1_sel, LDST_in2_sel, LDST_cr_out, LDST_ldst_len, LDST_is_32b, LDST_sgn, LDST_br, LDST_sgn_ext, LDST_upd, LDST_RA, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_LI, LDST_Rc, LDST_OE, LDST_BD, LDST_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire LDST_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] LDST_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [2:0] LDST_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [1:0] LDST_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] LDST_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] LDST_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [13:0] LDST_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [7:0] LDST_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire LDST_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [23:0] LDST_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire LDST_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output LDST_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] LDST_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] LDST_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output LDST_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] LDST_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] LDST_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [9:0] LDST_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] LDST_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [15:0] LDST_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_br; reg LDST_br; (* enum_base_type = "CRInSel" *) @@ -64162,7 +64162,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] LDST_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -64171,10 +64171,10 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_cr_out; reg [2:0] LDST_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_LDST_dec31_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -64185,7 +64185,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_LDST_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -64194,7 +64194,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_LDST_dec31_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -64211,7 +64211,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] LDST_dec31_LDST_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -64219,7 +64219,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_LDST_dec31_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -64236,7 +64236,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_LDST_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -64313,9 +64313,9 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec31_LDST_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_LDST_dec31_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -64323,28 +64323,28 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_LDST_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_LDST_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_LDST_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_LDST_dec31_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_LDST_dec31_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] LDST_dec31_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec58_LDST_dec58_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -64355,7 +64355,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec58_LDST_dec58_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -64364,7 +64364,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec58_LDST_dec58_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -64381,7 +64381,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] LDST_dec58_LDST_dec58_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -64389,7 +64389,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec58_LDST_dec58_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -64406,7 +64406,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec58_LDST_dec58_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -64483,9 +64483,9 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec58_LDST_dec58_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec58_LDST_dec58_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -64493,28 +64493,28 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec58_LDST_dec58_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec58_LDST_dec58_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec58_LDST_dec58_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec58_LDST_dec58_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec58_LDST_dec58_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] LDST_dec58_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec62_LDST_dec62_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -64525,7 +64525,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec62_LDST_dec62_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -64534,7 +64534,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec62_LDST_dec62_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -64551,7 +64551,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] LDST_dec62_LDST_dec62_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -64559,7 +64559,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec62_LDST_dec62_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -64576,7 +64576,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec62_LDST_dec62_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -64653,9 +64653,9 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec62_LDST_dec62_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec62_LDST_dec62_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -64663,26 +64663,26 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec62_LDST_dec62_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec62_LDST_dec62_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec62_LDST_dec62_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec62_LDST_dec62_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec62_LDST_dec62_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] LDST_dec62_opcode_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -64699,7 +64699,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] LDST_function_unit; reg [13:0] LDST_function_unit; (* enum_base_type = "In1Sel" *) @@ -64708,7 +64708,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_in1_sel; reg [2:0] LDST_in1_sel; (* enum_base_type = "In2Sel" *) @@ -64726,7 +64726,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_in2_sel; reg [3:0] LDST_in2_sel; (* enum_base_type = "MicrOp" *) @@ -64804,10 +64804,10 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_internal_op; reg [6:0] LDST_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_is_32b; reg LDST_is_32b; (* enum_base_type = "LdstLen" *) @@ -64816,517 +64816,517 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_ldst_len; reg [3:0] LDST_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_rc_sel; reg [1:0] LDST_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_sgn; reg LDST_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_sgn_ext; reg LDST_sgn_ext; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [5:0] LDST_sh; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_upd; reg [1:0] LDST_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; LDST_dec31 LDST_dec31 ( .LDST_dec31_br(LDST_dec31_LDST_dec31_br), .LDST_dec31_cr_in(LDST_dec31_LDST_dec31_cr_in), @@ -65378,57 +65378,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_ldst_len = LDST_dec31_LDST_dec31_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_ldst_len = LDST_dec58_LDST_dec58_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_ldst_len = LDST_dec62_LDST_dec62_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_ldst_len = 4'h4; endcase @@ -65436,57 +65436,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_upd = LDST_dec31_LDST_dec31_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_upd = LDST_dec58_LDST_dec58_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_upd = LDST_dec62_LDST_dec62_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_upd = 2'h1; endcase @@ -65494,57 +65494,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_rc_sel = LDST_dec31_LDST_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_rc_sel = LDST_dec58_LDST_dec58_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_rc_sel = LDST_dec62_LDST_dec62_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_rc_sel = 2'h0; endcase @@ -65552,57 +65552,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_br = LDST_dec31_LDST_dec31_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_br = LDST_dec58_LDST_dec58_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_br = LDST_dec62_LDST_dec62_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_br = 1'h0; endcase @@ -65610,57 +65610,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_sgn_ext = LDST_dec31_LDST_dec31_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_sgn_ext = LDST_dec58_LDST_dec58_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_sgn_ext = LDST_dec62_LDST_dec62_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_sgn_ext = 1'h0; endcase @@ -65668,57 +65668,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_is_32b = LDST_dec31_LDST_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_is_32b = LDST_dec58_LDST_dec58_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_is_32b = LDST_dec62_LDST_dec62_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_is_32b = 1'h0; endcase @@ -65726,57 +65726,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_sgn = LDST_dec31_LDST_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_sgn = LDST_dec58_LDST_dec58_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_sgn = LDST_dec62_LDST_dec62_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_sgn = 1'h0; endcase @@ -65784,57 +65784,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_function_unit = LDST_dec31_LDST_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_function_unit = LDST_dec58_LDST_dec58_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_function_unit = LDST_dec62_LDST_dec62_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_function_unit = 14'h0004; endcase @@ -65842,57 +65842,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_internal_op = LDST_dec31_LDST_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_internal_op = LDST_dec58_LDST_dec58_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_internal_op = LDST_dec62_LDST_dec62_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_internal_op = 7'h26; endcase @@ -65900,57 +65900,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_in1_sel = LDST_dec31_LDST_dec31_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_in1_sel = LDST_dec58_LDST_dec58_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_in1_sel = LDST_dec62_LDST_dec62_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_in1_sel = 3'h2; endcase @@ -65958,57 +65958,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_in2_sel = LDST_dec31_LDST_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_in2_sel = LDST_dec58_LDST_dec58_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_in2_sel = LDST_dec62_LDST_dec62_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_in2_sel = 4'h3; endcase @@ -66016,57 +66016,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_cr_in = LDST_dec31_LDST_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_cr_in = LDST_dec58_LDST_dec58_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_cr_in = LDST_dec62_LDST_dec62_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_cr_in = 3'h0; endcase @@ -66074,57 +66074,57 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: LDST_cr_out = LDST_dec31_LDST_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: LDST_cr_out = LDST_dec58_LDST_dec58_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: LDST_cr_out = LDST_dec62_LDST_dec62_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: LDST_cr_out = 3'h0; endcase @@ -66473,690 +66473,690 @@ endmodule (* generator = "nMigen" *) module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_unit, cr_out, cry_in, is_32b, lk, LK, cr_in, in1_sel, in2_sel, in3_sel, out_sel, asmcode, upd, RS, RT, RA, RB, Rc, OE, BB, BA, BT, FXM, BO, BI, BC, X_BF, X_BFA, XL_BT, XL_XO, bigendian); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) wire [31:0] \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [2:0] BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [1:0] BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [7:0] FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [23:0] LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [4:0] RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) output [9:0] SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SVL_vs; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [1:0] SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [1:0] SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] asmcode; reg [7:0] asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -67167,7 +67167,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] cr_in; reg [2:0] cr_in; (* enum_base_type = "CROutSel" *) @@ -67177,33 +67177,33 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] cr_out; reg [2:0] cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] cry_in; reg [1:0] cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg cry_out; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec19_dec19_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -67214,7 +67214,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -67223,15 +67223,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -67264,7 +67264,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec19_dec19_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -67281,7 +67281,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec19_dec19_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -67289,7 +67289,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -67306,13 +67306,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec19_dec19_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -67389,13 +67389,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec19_dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -67403,9 +67403,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec19_dec19_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -67413,21 +67413,21 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67436,7 +67436,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67445,7 +67445,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67454,7 +67454,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67463,7 +67463,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67472,7 +67472,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67481,7 +67481,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67490,32 +67490,32 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec19_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec22_dec22_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -67526,7 +67526,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -67535,15 +67535,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -67576,7 +67576,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec22_dec22_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -67593,7 +67593,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec22_dec22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -67601,7 +67601,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -67618,13 +67618,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec22_dec22_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -67701,13 +67701,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec22_dec22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -67715,9 +67715,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec22_dec22_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -67725,21 +67725,21 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67748,7 +67748,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67757,7 +67757,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67766,7 +67766,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67775,7 +67775,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67784,7 +67784,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67793,7 +67793,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67802,32 +67802,32 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec22_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec30_dec30_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -67838,7 +67838,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -67847,15 +67847,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -67888,7 +67888,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec30_dec30_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -67905,7 +67905,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec30_dec30_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -67913,7 +67913,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -67930,13 +67930,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec30_dec30_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -68013,13 +68013,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec30_dec30_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -68027,9 +68027,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec30_dec30_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -68037,21 +68037,21 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68060,7 +68060,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68069,7 +68069,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68078,7 +68078,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68087,7 +68087,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68096,7 +68096,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68105,7 +68105,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68114,32 +68114,32 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec30_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec31_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -68150,7 +68150,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -68159,15 +68159,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -68200,7 +68200,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec31_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -68217,7 +68217,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -68225,7 +68225,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -68242,13 +68242,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec31_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -68325,13 +68325,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -68339,9 +68339,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec31_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -68349,21 +68349,21 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68372,7 +68372,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68381,7 +68381,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68390,7 +68390,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68399,7 +68399,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68408,7 +68408,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68417,7 +68417,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68426,32 +68426,32 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec58_dec58_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -68462,7 +68462,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -68471,15 +68471,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -68512,7 +68512,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec58_dec58_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -68529,7 +68529,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec58_dec58_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -68537,7 +68537,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -68554,13 +68554,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec58_dec58_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -68637,13 +68637,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec58_dec58_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -68651,9 +68651,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec58_dec58_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -68661,21 +68661,21 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68684,7 +68684,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68693,7 +68693,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68702,7 +68702,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68711,7 +68711,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68720,7 +68720,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68729,7 +68729,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68738,32 +68738,32 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec58_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec62_dec62_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -68774,7 +68774,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -68783,15 +68783,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -68824,7 +68824,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec62_dec62_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -68841,7 +68841,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec62_dec62_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -68849,7 +68849,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -68866,13 +68866,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec62_dec62_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -68949,13 +68949,13 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec62_dec62_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -68963,9 +68963,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec62_dec62_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -68973,21 +68973,21 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68996,7 +68996,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69005,7 +69005,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69014,7 +69014,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69023,7 +69023,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69032,7 +69032,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69041,7 +69041,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69050,16 +69050,16 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec62_opcode_in; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -69092,7 +69092,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [4:0] form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -69109,7 +69109,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] function_unit; reg [13:0] function_unit; (* enum_base_type = "In1Sel" *) @@ -69118,7 +69118,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] in1_sel; reg [2:0] in1_sel; (* enum_base_type = "In2Sel" *) @@ -69136,14 +69136,14 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] in2_sel; reg [3:0] in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] in3_sel; reg [1:0] in3_sel; (* enum_base_type = "MicrOp" *) @@ -69221,14 +69221,14 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] internal_op; reg [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output is_32b; reg is_32b; (* enum_base_type = "LdstLen" *) @@ -69237,16 +69237,16 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [3:0] ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output lk; reg lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [31:0] \opcode_switch$1 ; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -69254,27 +69254,27 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] out_sel; reg [2:0] out_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] rc_sel; reg [1:0] rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg sgn_ext; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] sh; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69283,7 +69283,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69292,7 +69292,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69301,7 +69301,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69310,7 +69310,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69319,7 +69319,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69328,7 +69328,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69337,17 +69337,17 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] upd; reg [1:0] upd; - assign \$2 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$2 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; dec19 dec19 ( .dec19_SV_Etype(dec19_dec19_SV_Etype), .dec19_SV_Ptype(dec19_dec19_SV_Ptype), @@ -69567,144 +69567,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: form = dec19_dec19_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: form = dec30_dec30_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: form = dec31_dec31_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: form = dec58_dec58_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: form = dec62_dec62_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: form = dec22_dec22_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: form = 5'h03; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: form = 5'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: form = 5'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: form = 5'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: form = 5'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: form = 5'h13; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: form = 5'h13; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: form = 5'h13; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: form = 5'h04; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: form = 5'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: form = 5'h00; endcase @@ -69712,144 +69712,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: asmcode = dec19_dec19_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: asmcode = dec30_dec30_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: asmcode = dec31_dec31_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: asmcode = dec58_dec58_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: asmcode = dec62_dec62_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: asmcode = dec22_dec22_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: asmcode = 8'h07; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: asmcode = 8'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: asmcode = 8'h06; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: asmcode = 8'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: asmcode = 8'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: asmcode = 8'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: asmcode = 8'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: asmcode = 8'h15; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: asmcode = 8'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: asmcode = 8'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: asmcode = 8'h4e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: asmcode = 8'h4f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: asmcode = 8'h58; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: asmcode = 8'h5a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: asmcode = 8'h5e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: asmcode = 8'h5f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: asmcode = 8'h67; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: asmcode = 8'h69; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: asmcode = 8'h80; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: asmcode = 8'h8a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: asmcode = 8'h8b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: asmcode = 8'h98; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: asmcode = 8'h99; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: asmcode = 8'h9a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: asmcode = 8'ha7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: asmcode = 8'haa; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: asmcode = 8'hb3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: asmcode = 8'hb6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: asmcode = 8'hb9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: asmcode = 8'hbc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: asmcode = 8'hc4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: asmcode = 8'hcc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: asmcode = 8'hd0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: asmcode = 8'hd2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: asmcode = 8'hd3; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: asmcode = 8'h13; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: asmcode = 8'h86; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: asmcode = 8'h9d; endcase @@ -69857,144 +69857,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: SV_Etype = dec19_dec19_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SV_Etype = dec30_dec30_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SV_Etype = dec31_dec31_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: SV_Etype = dec58_dec58_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: SV_Etype = dec62_dec62_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: SV_Etype = dec22_dec22_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: SV_Etype = 2'h2; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: SV_Etype = 2'h0; endcase @@ -70002,144 +70002,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: SV_Ptype = dec19_dec19_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: SV_Ptype = dec30_dec30_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: SV_Ptype = dec31_dec31_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: SV_Ptype = dec58_dec58_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: SV_Ptype = dec62_dec62_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: SV_Ptype = dec22_dec22_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: SV_Ptype = 2'h2; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: SV_Ptype = 2'h0; endcase @@ -70147,144 +70147,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: in1_sel = dec19_dec19_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: in1_sel = dec30_dec30_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: in1_sel = dec31_dec31_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: in1_sel = dec58_dec58_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: in1_sel = dec62_dec62_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: in1_sel = dec22_dec22_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: in1_sel = 3'h4; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: in1_sel = 3'h0; endcase @@ -70292,144 +70292,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: in2_sel = dec19_dec19_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: in2_sel = dec30_dec30_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: in2_sel = dec31_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: in2_sel = dec58_dec58_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: in2_sel = dec62_dec62_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: in2_sel = dec22_dec22_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: in2_sel = 4'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: in2_sel = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: in2_sel = 4'h6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: in2_sel = 4'h7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: in2_sel = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: in2_sel = 4'h4; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: in2_sel = 4'h0; endcase @@ -70437,144 +70437,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: in3_sel = dec19_dec19_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: in3_sel = dec30_dec30_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: in3_sel = dec31_dec31_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: in3_sel = dec58_dec58_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: in3_sel = dec62_dec62_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: in3_sel = dec22_dec22_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: in3_sel = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: in3_sel = 2'h0; endcase @@ -70582,144 +70582,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: out_sel = dec19_dec19_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: out_sel = dec30_dec30_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: out_sel = dec31_dec31_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: out_sel = dec58_dec58_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: out_sel = dec62_dec62_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: out_sel = dec22_dec22_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: out_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: out_sel = 3'h2; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: out_sel = 3'h1; endcase @@ -70727,144 +70727,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: cr_in = dec19_dec19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: cr_in = dec30_dec30_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: cr_in = dec31_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: cr_in = dec58_dec58_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: cr_in = dec62_dec62_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: cr_in = dec22_dec22_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: cr_in = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: cr_in = 3'h0; endcase @@ -70872,144 +70872,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: cr_out = dec19_dec19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: cr_out = dec30_dec30_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: cr_out = dec31_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: cr_out = dec58_dec58_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: cr_out = dec62_dec62_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: cr_out = dec22_dec22_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: cr_out = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: cr_out = 3'h0; endcase @@ -71017,144 +71017,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: sv_in1 = dec19_dec19_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: sv_in1 = dec30_dec30_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: sv_in1 = dec31_dec31_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: sv_in1 = dec58_dec58_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: sv_in1 = dec62_dec62_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: sv_in1 = dec22_dec22_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: sv_in1 = 3'h2; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: sv_in1 = 3'h0; endcase @@ -71162,144 +71162,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: sv_in2 = dec19_dec19_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: sv_in2 = dec30_dec30_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: sv_in2 = dec31_dec31_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: sv_in2 = dec58_dec58_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: sv_in2 = dec62_dec62_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: sv_in2 = dec22_dec22_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: sv_in2 = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: sv_in2 = 3'h0; endcase @@ -71307,144 +71307,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: sv_in3 = dec19_dec19_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: sv_in3 = dec30_dec30_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: sv_in3 = dec31_dec31_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: sv_in3 = dec58_dec58_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: sv_in3 = dec62_dec62_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: sv_in3 = dec22_dec22_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: sv_in3 = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: sv_in3 = 3'h0; endcase @@ -71452,144 +71452,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: sv_out = dec19_dec19_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: sv_out = dec30_dec30_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: sv_out = dec31_dec31_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: sv_out = dec58_dec58_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: sv_out = dec62_dec62_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: sv_out = dec22_dec22_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: sv_out = 3'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: sv_out = 3'h0; endcase @@ -71597,144 +71597,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: sv_out2 = dec19_dec19_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: sv_out2 = dec30_dec30_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: sv_out2 = dec31_dec31_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: sv_out2 = dec58_dec58_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: sv_out2 = dec62_dec62_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: sv_out2 = dec22_dec22_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: sv_out2 = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: sv_out2 = 3'h0; endcase @@ -71742,144 +71742,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: sv_cr_in = dec19_dec19_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: sv_cr_in = dec30_dec30_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: sv_cr_in = dec31_dec31_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: sv_cr_in = dec58_dec58_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: sv_cr_in = dec62_dec62_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: sv_cr_in = dec22_dec22_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: sv_cr_in = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: sv_cr_in = 3'h0; endcase @@ -71887,144 +71887,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: sv_cr_out = dec19_dec19_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: sv_cr_out = dec30_dec30_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: sv_cr_out = dec31_dec31_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: sv_cr_out = dec58_dec58_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: sv_cr_out = dec62_dec62_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: sv_cr_out = dec22_dec22_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: sv_cr_out = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: sv_cr_out = 3'h0; endcase @@ -72032,144 +72032,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: ldst_len = dec19_dec19_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: ldst_len = dec30_dec30_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: ldst_len = dec31_dec31_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: ldst_len = dec58_dec58_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: ldst_len = dec62_dec62_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: ldst_len = dec22_dec22_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: ldst_len = 4'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: ldst_len = 4'h0; endcase @@ -72177,144 +72177,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: upd = dec19_dec19_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: upd = dec30_dec30_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: upd = dec31_dec31_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: upd = dec58_dec58_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: upd = dec62_dec62_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: upd = dec22_dec22_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: upd = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: upd = 2'h0; endcase @@ -72322,144 +72322,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: rc_sel = dec19_dec19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: rc_sel = dec30_dec30_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: rc_sel = dec31_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: rc_sel = dec58_dec58_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: rc_sel = dec62_dec62_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: rc_sel = dec22_dec22_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: rc_sel = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: rc_sel = 2'h0; endcase @@ -72467,144 +72467,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: cry_in = dec19_dec19_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: cry_in = dec30_dec30_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: cry_in = dec31_dec31_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: cry_in = dec58_dec58_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: cry_in = dec62_dec62_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: cry_in = dec22_dec22_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: cry_in = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: cry_in = 2'h0; endcase @@ -72612,144 +72612,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: inv_a = dec19_dec19_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: inv_a = dec30_dec30_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: inv_a = dec31_dec31_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: inv_a = dec58_dec58_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: inv_a = dec62_dec62_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: inv_a = dec22_dec22_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: inv_a = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: inv_a = 1'h0; endcase @@ -72757,144 +72757,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: inv_out = dec19_dec19_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: inv_out = dec30_dec30_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: inv_out = dec31_dec31_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: inv_out = dec58_dec58_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: inv_out = dec62_dec62_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: inv_out = dec22_dec22_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: inv_out = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: inv_out = 1'h0; endcase @@ -72902,144 +72902,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: cry_out = dec19_dec19_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: cry_out = dec30_dec30_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: cry_out = dec31_dec31_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: cry_out = dec58_dec58_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: cry_out = dec62_dec62_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: cry_out = dec22_dec22_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: cry_out = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: cry_out = 1'h0; endcase @@ -73047,144 +73047,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: br = dec19_dec19_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: br = dec30_dec30_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: br = dec31_dec31_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: br = dec58_dec58_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: br = dec62_dec62_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: br = dec22_dec22_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: br = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: br = 1'h0; endcase @@ -73192,144 +73192,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: sgn_ext = dec19_dec19_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: sgn_ext = dec30_dec30_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: sgn_ext = dec31_dec31_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: sgn_ext = dec58_dec58_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: sgn_ext = dec62_dec62_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: sgn_ext = dec22_dec22_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: sgn_ext = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: sgn_ext = 1'h0; endcase @@ -73337,144 +73337,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: rsrv = dec19_dec19_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: rsrv = dec30_dec30_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: rsrv = dec31_dec31_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: rsrv = dec58_dec58_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: rsrv = dec62_dec62_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: rsrv = dec22_dec22_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: rsrv = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: rsrv = 1'h0; endcase @@ -73482,144 +73482,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: is_32b = dec19_dec19_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: is_32b = dec30_dec30_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: is_32b = dec31_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: is_32b = dec58_dec58_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: is_32b = dec62_dec62_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: is_32b = dec22_dec22_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: is_32b = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: is_32b = 1'h0; endcase @@ -73627,144 +73627,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: sgn = dec19_dec19_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: sgn = dec30_dec30_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: sgn = dec31_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: sgn = dec58_dec58_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: sgn = dec62_dec62_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: sgn = dec22_dec22_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: sgn = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: sgn = 1'h0; endcase @@ -73772,144 +73772,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: lk = dec19_dec19_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: lk = dec30_dec30_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: lk = dec31_dec31_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: lk = dec58_dec58_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: lk = dec62_dec62_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: lk = dec22_dec22_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: lk = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: lk = 1'h0; endcase @@ -73917,144 +73917,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: sgl_pipe = dec19_dec19_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: sgl_pipe = dec30_dec30_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: sgl_pipe = dec31_dec31_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: sgl_pipe = dec58_dec58_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: sgl_pipe = dec62_dec62_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: sgl_pipe = dec22_dec22_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: sgl_pipe = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: sgl_pipe = 1'h1; endcase @@ -74062,144 +74062,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: function_unit = dec19_dec19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: function_unit = dec30_dec30_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: function_unit = dec31_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: function_unit = dec58_dec58_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: function_unit = dec62_dec62_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: function_unit = dec22_dec22_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: function_unit = 14'h0010; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: function_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: function_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: function_unit = 14'h0000; endcase @@ -74207,144 +74207,144 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h13: internal_op = dec19_dec19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1e: internal_op = dec30_dec30_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1f: internal_op = dec31_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3a: internal_op = dec58_dec58_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h3e: internal_op = dec62_dec62_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h16: internal_op = dec22_dec22_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0c: internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0d: internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0e: internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0f: internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h11: internal_op = 7'h49; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1c: internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1d: internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h12: internal_op = 7'h06; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h10: internal_op = 7'h07; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0b: internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h0a: internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h22: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h23: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2a: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2b: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h28: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h29: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h20: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h21: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h07: internal_op = 7'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h18: internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h19: internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h14: internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h15: internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h17: internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h26: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h27: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2c: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h2d: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h24: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h25: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h08: internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h02: internal_op = 7'h3f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h03: internal_op = 7'h3f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1a: internal_op = 7'h43; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 6'h1b: internal_op = 7'h43; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000000???????????????0100000000?: internal_op = 7'h05; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'd1610612736: internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 32'b000001???????????????0000000011?: internal_op = 7'h44; endcase @@ -74701,20 +74701,20 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_SV_Etype; reg [1:0] dec19_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_SV_Ptype; reg [1:0] dec19_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec19_asmcode; reg [7:0] dec19_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_br; reg dec19_br; (* enum_base_type = "CRInSel" *) @@ -74726,7 +74726,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_cr_in; reg [2:0] dec19_cr_in; (* enum_base_type = "CROutSel" *) @@ -74736,17 +74736,17 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_cr_out; reg [2:0] dec19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_cry_in; reg [1:0] dec19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_cry_out; reg dec19_cry_out; (* enum_base_type = "Form" *) @@ -74780,7 +74780,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec19_form; reg [4:0] dec19_form; (* enum_base_type = "Function" *) @@ -74798,7 +74798,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec19_function_unit; reg [13:0] dec19_function_unit; (* enum_base_type = "In1Sel" *) @@ -74807,7 +74807,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_in1_sel; reg [2:0] dec19_in1_sel; (* enum_base_type = "In2Sel" *) @@ -74825,14 +74825,14 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec19_in2_sel; reg [3:0] dec19_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_in3_sel; reg [1:0] dec19_in3_sel; (* enum_base_type = "MicrOp" *) @@ -74910,16 +74910,16 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec19_internal_op; reg [6:0] dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_inv_a; reg dec19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_inv_out; reg dec19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_is_32b; reg dec19_is_32b; (* enum_base_type = "LdstLen" *) @@ -74928,10 +74928,10 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec19_ldst_len; reg [3:0] dec19_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_lk; reg dec19_lk; (* enum_base_type = "OutSel" *) @@ -74940,26 +74940,26 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_out_sel; reg [2:0] dec19_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_rc_sel; reg [1:0] dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_rsrv; reg dec19_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_sgl_pipe; reg dec19_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_sgn; reg dec19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_sgn_ext; reg dec19_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -74969,7 +74969,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_cr_in; reg [2:0] dec19_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -74979,7 +74979,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_cr_out; reg [2:0] dec19_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -74989,7 +74989,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_in1; reg [2:0] dec19_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -74999,7 +74999,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_in2; reg [2:0] dec19_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -75009,7 +75009,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_in3; reg [2:0] dec19_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -75019,7 +75019,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_out; reg [2:0] dec19_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -75029,7 +75029,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_out2; reg [2:0] dec19_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -75037,61 +75037,61 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_upd; reg [1:0] dec19_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; always @* begin if (\initial ) begin end dec19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_function_unit = 14'h0080; endcase @@ -75099,51 +75099,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_cr_in = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_cr_in = 3'h0; endcase @@ -75151,51 +75151,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_cr_out = 3'h0; endcase @@ -75203,51 +75203,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_sv_in1 = 3'h0; endcase @@ -75255,51 +75255,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_sv_in2 = 3'h0; endcase @@ -75307,51 +75307,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_sv_in3 = 3'h0; endcase @@ -75359,51 +75359,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_sv_out = 3'h0; endcase @@ -75411,51 +75411,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_sv_out2 = 3'h0; endcase @@ -75463,51 +75463,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_sv_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_sv_cr_in = 3'h0; endcase @@ -75515,51 +75515,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_sv_cr_out = 3'h0; endcase @@ -75567,51 +75567,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_ldst_len = 4'h0; endcase @@ -75619,51 +75619,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_internal_op = 7'h2a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_internal_op = 7'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_internal_op = 7'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_internal_op = 7'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_internal_op = 7'h24; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_internal_op = 7'h46; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_internal_op = 7'h46; endcase @@ -75671,51 +75671,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_upd = 2'h0; endcase @@ -75723,51 +75723,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_rc_sel = 2'h0; endcase @@ -75775,51 +75775,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_cry_in = 2'h0; endcase @@ -75827,51 +75827,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_asmcode = 8'h6c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_asmcode = 8'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_asmcode = 8'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_asmcode = 8'h27; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_asmcode = 8'h28; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_asmcode = 8'h29; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_asmcode = 8'h2a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_asmcode = 8'h2b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_asmcode = 8'h2c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_asmcode = 8'h16; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_asmcode = 8'h17; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_asmcode = 8'h18; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_asmcode = 8'h4c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_asmcode = 8'h91; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_asmcode = 8'h48; endcase @@ -75879,51 +75879,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_inv_a = 1'h0; endcase @@ -75931,51 +75931,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_inv_out = 1'h0; endcase @@ -75983,51 +75983,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_cry_out = 1'h0; endcase @@ -76035,51 +76035,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_br = 1'h0; endcase @@ -76087,51 +76087,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_sgn_ext = 1'h0; endcase @@ -76139,51 +76139,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_rsrv = 1'h0; endcase @@ -76191,51 +76191,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_form = 5'h09; endcase @@ -76243,51 +76243,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_is_32b = 1'h0; endcase @@ -76295,51 +76295,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_sgn = 1'h0; endcase @@ -76347,51 +76347,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_lk = 1'h0; endcase @@ -76399,51 +76399,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_sgl_pipe = 1'h0; endcase @@ -76451,51 +76451,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_SV_Etype = 2'h0; endcase @@ -76503,51 +76503,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_SV_Ptype = 2'h0; endcase @@ -76555,51 +76555,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_in1_sel = 3'h3; endcase @@ -76607,51 +76607,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_in2_sel = 4'hc; endcase @@ -76659,51 +76659,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_in3_sel = 2'h0; endcase @@ -76711,51 +76711,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h000: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h101: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h081: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h121: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0e1: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h021: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1c1: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h1a1: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h0c1: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h210: dec19_out_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h010: dec19_out_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h230: dec19_out_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h096: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h012: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 10'h112: dec19_out_sel = 3'h0; endcase @@ -76767,207 +76767,207 @@ endmodule (* generator = "nMigen" *) module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, rego_ok, ea, ea_ok, reg1, reg1_ok, reg2, reg2_ok, reg3, reg3_ok, spro, spro_ok, spr1, spr1_ok, xer_in, xer_out, fast1, fast1_ok, fast2, fast2_ok, fasto1, fasto1_ok, fasto2, fasto2_ok, cr_in1, cr_in1_ok, cr_in2, cr_in2_ok, \cr_in2$1 , \cr_in2_ok$2 , cr_out, cr_out_ok, msr, cia, insn, insn_type, fn_unit, lk, rc, rc_ok, oe, oe_ok, input_carry, traptype, \exc_$signal , \exc_$signal$3 , \exc_$signal$4 , \exc_$signal$5 , \exc_$signal$6 , \exc_$signal$7 , \exc_$signal$8 , \exc_$signal$9 , trapaddr, cr_rd, cr_rd_ok, cr_wr, cr_wr_ok, is_32bit, sv_a_nz, cur_eint); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] \$100 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] \$102 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] \$104 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1217" *) wire \$106 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1219" *) wire \$108 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1221" *) wire \$110 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1225" *) wire \$112 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1248" *) wire \$114 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1249" *) wire \$116 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1250" *) wire \$118 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1251" *) wire \$120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1299" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1300" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1300" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1309" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) wire \$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] \$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] \$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] \$94 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] \$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] \$98 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:101" *) output [7:0] asmcode; reg [7:0] asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:44" *) output [63:0] cia; reg [63:0] cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [6:0] cr_in1; reg [6:0] cr_in1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_in1_ok; reg cr_in1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [6:0] cr_in2; reg [6:0] cr_in2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [6:0] \cr_in2$1 ; reg [6:0] \cr_in2$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_in2_ok; reg cr_in2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \cr_in2_ok$2 ; reg \cr_in2_ok$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [6:0] cr_out; reg [6:0] cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_out_ok; reg cr_out_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [7:0] cr_rd; reg [7:0] cr_rd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_rd_ok; reg cr_rd_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [7:0] cr_wr; reg [7:0] cr_wr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_wr_ok; reg cr_wr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *) input [63:0] cur_dec; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *) input cur_eint; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) input [63:0] cur_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) input [63:0] cur_pc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [7:0] dec_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] dec_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] dec_X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] dec_X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec_a_fast_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_a_fast_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [4:0] dec_a_reg_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_a_reg_a_ok; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -76975,7 +76975,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:110" *) wire [2:0] dec_a_sel_in; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -77091,21 +77091,21 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [9:0] dec_a_spr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_a_spr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:115" *) wire dec_a_sv_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec_b_fast_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_b_fast_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] dec_b_reg_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_b_reg_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -77122,17 +77122,17 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:208" *) wire [3:0] dec_b_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [4:0] dec_c_reg_c; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_c_reg_c_ok; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:314" *) wire [1:0] dec_c_sel_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -77143,25 +77143,25 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_cr_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec_cr_in_cr_bitfield; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec_cr_in_cr_bitfield_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_cr_in_cr_bitfield_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec_cr_in_cr_bitfield_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_cr_in_cr_bitfield_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_cr_in_cr_bitfield_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [7:0] dec_cr_in_cr_fxm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_cr_in_cr_fxm_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:542" *) wire [31:0] dec_cr_in_insn_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -77172,7 +77172,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:541" *) wire [2:0] dec_cr_in_sel_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -77181,19 +77181,19 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec_cr_out_cr_bitfield; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_cr_out_cr_bitfield_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [7:0] dec_cr_out_cr_fxm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_cr_out_cr_fxm_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:617" *) wire [31:0] dec_cr_out_insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:615" *) wire dec_cr_out_rc_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -77202,13 +77202,13 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:616" *) wire [2:0] dec_cr_out_sel_in; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_cry_in; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -77225,7 +77225,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -77233,7 +77233,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -77250,13 +77250,13 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -77333,31 +77333,31 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1244" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1243" *) wire dec_irq_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_is_32b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec_o2_fast_o2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_o2_fast_o2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:415" *) wire dec_o2_lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [4:0] dec_o2_reg_o2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_o2_reg_o2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec_o_fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_o_fast_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [4:0] dec_o_reg_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_o_reg_o_ok; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -77365,7 +77365,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:350" *) wire [2:0] dec_o_sel_in; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -77481,21 +77481,21 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [9:0] dec_o_spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_o_spr_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec_opcode_in; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -77503,85 +77503,85 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_out_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_rc_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) wire [1:0] dec_rc_sel_in; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [6:0] ea; reg [6:0] ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output ea_ok; reg ea_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \exc_$signal ; reg \exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \exc_$signal$3 ; reg \exc_$signal$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \exc_$signal$4 ; reg \exc_$signal$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \exc_$signal$5 ; reg \exc_$signal$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \exc_$signal$6 ; reg \exc_$signal$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \exc_$signal$7 ; reg \exc_$signal$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \exc_$signal$8 ; reg \exc_$signal$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \exc_$signal$9 ; reg \exc_$signal$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1243" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1242" *) wire ext_irq_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] fast1; reg [2:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; reg fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] fast2; reg [2:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast2_ok; reg fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] fasto1; reg [2:0] fasto1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fasto1_ok; reg fasto1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] fasto2; reg [2:0] fasto2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fasto2_ok; reg fasto2_ok; (* enum_base_type = "Function" *) @@ -77599,34 +77599,34 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:49" *) output [13:0] fn_unit; reg [13:0] fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1246" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1245" *) wire illeg_ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) output [1:0] input_carry; reg [1:0] input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) output [31:0] insn; reg [31:0] insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:462" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) wire [31:0] \insn_in$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:111" *) wire [31:0] \insn_in$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:209" *) wire [31:0] \insn_in$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:315" *) wire [31:0] \insn_in$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:351" *) wire [31:0] \insn_in$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:416" *) wire [31:0] \insn_in$89 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -77703,62 +77703,62 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:48" *) output [6:0] insn_type; reg [6:0] insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) output is_32bit; reg is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:841" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:52" *) reg is_priv_insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:840" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) output lk; reg lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:43" *) output [63:0] msr; reg [63:0] msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe_ok; reg oe_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1245" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1244" *) wire priv_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc_ok; reg rc_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [6:0] reg1; reg [6:0] reg1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output reg1_ok; reg reg1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [6:0] reg2; reg [6:0] reg2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output reg2_ok; reg reg2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [6:0] reg3; reg [6:0] reg3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output reg3_ok; reg reg3_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [6:0] rego; reg [6:0] rego; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rego_ok; reg rego_ok; (* enum_base_type = "OutSel" *) @@ -77767,9 +77767,9 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:415" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:414" *) wire [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:835" *) wire [9:0] spr; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -77885,10 +77885,10 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [9:0] spr1; reg [9:0] spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spr1_ok; reg spr1_ok; (* enum_base_type = "SPR" *) @@ -78005,67 +78005,67 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [9:0] spro; reg [9:0] spro; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spro_ok; reg spro_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) input sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:101" *) wire [7:0] tmp_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] tmp_cr_in1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_cr_in1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] tmp_cr_in2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] \tmp_cr_in2$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_cr_in2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \tmp_cr_in2_ok$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] tmp_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_cr_out_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] tmp_ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_ea_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] tmp_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] tmp_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] tmp_fasto1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_fasto1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] tmp_fasto2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_fasto2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] tmp_reg1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_reg1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] tmp_reg2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_reg2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] tmp_reg3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_reg3_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] tmp_rego; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_rego_ok; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -78181,9 +78181,9 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [9:0] tmp_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_spr1_ok; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -78299,35 +78299,35 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [9:0] tmp_spro; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_spro_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:44" *) wire [63:0] tmp_tmp_cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [7:0] tmp_tmp_cr_rd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_tmp_cr_rd_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [7:0] tmp_tmp_cr_wr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_tmp_cr_wr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \tmp_tmp_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \tmp_tmp_exc_$signal$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \tmp_tmp_exc_$signal$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \tmp_tmp_exc_$signal$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \tmp_tmp_exc_$signal$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \tmp_tmp_exc_$signal$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \tmp_tmp_exc_$signal$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \tmp_tmp_exc_$signal$27 ; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -78344,15 +78344,15 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:49" *) reg [13:0] tmp_tmp_fn_unit; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) wire [1:0] tmp_tmp_input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) wire [31:0] tmp_tmp_insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -78429,86 +78429,86 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:48" *) reg [6:0] tmp_tmp_insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) wire tmp_tmp_is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) reg tmp_tmp_lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:43" *) wire [63:0] tmp_tmp_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_tmp_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_tmp_oe_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_tmp_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire tmp_tmp_rc_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) reg [12:0] tmp_tmp_trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:54" *) wire [7:0] tmp_tmp_traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:111" *) reg [2:0] tmp_xer_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:112" *) reg tmp_xer_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) output [12:0] trapaddr; reg [12:0] trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:54" *) output [7:0] traptype; reg [7:0] traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:111" *) output [2:0] xer_in; reg [2:0] xer_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:112" *) output xer_out; reg xer_out; - assign \$100 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield_b; - assign \$102 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield_o; - assign \$104 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_out_cr_bitfield; - assign \$106 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *) 7'h2e; - assign \$108 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *) 7'h0a; - assign \$110 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *) 7'h31; - assign \$112 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *) 7'h3f; - assign \$114 = cur_eint & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" *) cur_msr[15]; - assign \$116 = cur_dec[63] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" *) cur_msr[15]; - assign \$118 = is_priv_insn & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" *) cur_msr[14]; - assign \$120 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" *) 7'h00; - assign \$28 = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" *) 7'h3f; - assign \$30 = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) 7'h49; - assign \$32 = \$28 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) \$30 ; - assign \$34 = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *) 7'h46; - assign \$37 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$39 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$37 ; - assign \$41 = \$39 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$43 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$45 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$43 ; - assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$49 = \$45 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$47 ; - assign \$51 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$53 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$55 = \$51 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$53 ; - assign \$57 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$59 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$61 = \$57 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$59 ; - assign \$63 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$65 = \$61 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$63 ; - assign \$67 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$69 = \$65 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$67 ; - assign \$71 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$73 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$71 ; - assign \$75 = \$73 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$77 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$79 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$77 ; - assign \$81 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$83 = \$79 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$81 ; - assign \$90 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_a_reg_a; - assign \$92 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_c_reg_c; - assign \$94 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_o_reg_o; - assign \$96 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_o2_reg_o2; - assign \$98 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield; + assign \$100 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield_b; + assign \$102 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield_o; + assign \$104 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) dec_cr_out_cr_bitfield; + assign \$106 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1217" *) 7'h2e; + assign \$108 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1219" *) 7'h0a; + assign \$110 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1221" *) 7'h31; + assign \$112 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1225" *) 7'h3f; + assign \$114 = cur_eint & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1248" *) cur_msr[15]; + assign \$116 = cur_dec[63] & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1249" *) cur_msr[15]; + assign \$118 = is_priv_insn & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1250" *) cur_msr[14]; + assign \$120 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1251" *) 7'h00; + assign \$28 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1299" *) 7'h3f; + assign \$30 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1300" *) 7'h49; + assign \$32 = \$28 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1300" *) \$30 ; + assign \$34 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1309" *) 7'h46; + assign \$37 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$39 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$37 ; + assign \$41 = \$39 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$43 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$45 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$43 ; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$49 = \$45 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$47 ; + assign \$51 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) 7'h31; + assign \$53 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) 7'h2e; + assign \$55 = \$51 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) \$53 ; + assign \$57 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h12; + assign \$59 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h13; + assign \$61 = \$57 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$59 ; + assign \$63 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 10'h2d0; + assign \$65 = \$61 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$63 ; + assign \$67 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) 6'h30; + assign \$69 = \$65 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) \$67 ; + assign \$71 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$73 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$71 ; + assign \$75 = \$73 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$77 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$79 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$77 ; + assign \$81 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$83 = \$79 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$81 ; + assign \$90 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) dec_a_reg_a; + assign \$92 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) dec_c_reg_c; + assign \$94 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) dec_o_reg_o; + assign \$96 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) dec_o2_reg_o2; + assign \$98 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield; \dec$171 dec ( .BA(dec_BA), .BB(dec_BB), @@ -78654,15 +78654,15 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$83 , \$75 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: tmp_tmp_fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: tmp_tmp_fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:857" */ default: tmp_tmp_fn_unit = dec_function_unit; endcase @@ -78670,9 +78670,9 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end tmp_tmp_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:897" *) casez (dec_lk) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:897" */ 1'h1: tmp_tmp_lk = dec_LK; endcase @@ -78680,12 +78680,12 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end tmp_tmp_insn_type = dec_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$49 , \$41 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: tmp_tmp_insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: tmp_tmp_insn_type = 7'h00; endcase @@ -78693,15 +78693,15 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end tmp_xer_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1217" *) casez (\$106 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1217" */ 1'h1: tmp_xer_in = 3'h7; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1219" *) casez (\$108 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1219" */ 1'h1: tmp_xer_in = 3'h1; endcase @@ -78709,9 +78709,9 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end tmp_xer_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1221" *) casez (\$110 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1221" */ 1'h1: tmp_xer_out = 1'h1; endcase @@ -78719,9 +78719,9 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end tmp_tmp_trapaddr = 13'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1225" *) casez (\$112 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1225" */ 1'h1: tmp_tmp_trapaddr = 13'h0070; endcase @@ -78729,22 +78729,22 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end is_priv_insn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:53" *) casez (dec_internal_op) /* \nmigen.decoding = "OP_ATTN/5|OP_MFMSR/71|OP_MTMSRD/72|OP_MTMSR/74|OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:55" */ 7'h05, 7'h47, 7'h48, 7'h4a, 7'h46: is_priv_insn = 1'h1; /* \nmigen.decoding = "OP_TLBIE/75" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:58" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:57" */ 7'h4b: is_priv_insn = 1'h1; /* \nmigen.decoding = "OP_MFSPR/46|OP_MTSPR/49" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:58" */ 7'h2e, 7'h31: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:59" *) casez (tmp_tmp_insn[20]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:59" */ 1'h1: is_priv_insn = 1'h1; endcase @@ -78753,14 +78753,14 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1255" *) casez ({ illeg_ok, priv_ok, ext_irq_ok, dec_irq_ok, \dec2_exc_$signal }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1255" */ 5'b????1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1256" *) casez ({ \dec2_exc_$signal$13 , \dec2_exc_$signal$12 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1256" */ 2'b?1: begin { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -78772,12 +78772,12 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r msr = cur_msr; cia = cur_pc; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1259" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1258" */ 2'b1?: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1259" *) casez (\dec2_exc_$signal$14 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1259" */ 1'h1: begin { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -78789,7 +78789,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r msr = cur_msr; cia = cur_pc; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1262" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1261" */ default: begin { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -78803,12 +78803,12 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r cia = cur_pc; end endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1265" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1264" */ default: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1265" *) casez (\dec2_exc_$signal$14 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1265" */ 1'h1: begin { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -78820,7 +78820,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r msr = cur_msr; cia = cur_pc; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1268" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1267" */ default: begin { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -78834,7 +78834,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r end endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1271" */ 5'b???1?: begin { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -78846,7 +78846,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r msr = cur_msr; cia = cur_pc; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1276" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1275" */ 5'b??1??: begin { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -78858,7 +78858,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r msr = cur_msr; cia = cur_pc; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1280" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1279" */ 5'b?1???: begin { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -78870,7 +78870,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r msr = cur_msr; cia = cur_pc; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1287" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1286" */ 5'h1?: begin { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -78882,13 +78882,13 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r msr = cur_msr; cia = cur_pc; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1292" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1291" */ default: { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = { tmp_tmp_is_32bit, tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr, tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd, tmp_tmp_trapaddr, \tmp_tmp_exc_$signal$27 , \tmp_tmp_exc_$signal$26 , \tmp_tmp_exc_$signal$25 , \tmp_tmp_exc_$signal$24 , \tmp_tmp_exc_$signal$23 , \tmp_tmp_exc_$signal$22 , \tmp_tmp_exc_$signal$21 , \tmp_tmp_exc_$signal , tmp_tmp_traptype, tmp_tmp_input_carry, tmp_tmp_oe_ok, tmp_tmp_oe, tmp_tmp_rc_ok, tmp_tmp_rc, tmp_tmp_lk, tmp_tmp_fn_unit, tmp_tmp_insn_type, tmp_tmp_insn, tmp_tmp_cia, tmp_tmp_msr, tmp_cr_out_ok, tmp_cr_out, \tmp_cr_in2_ok$20 , \tmp_cr_in2$19 , tmp_cr_in2_ok, tmp_cr_in2, tmp_cr_in1_ok, tmp_cr_in1, tmp_fasto2_ok, tmp_fasto2, tmp_fasto1_ok, tmp_fasto1, tmp_fast2_ok, tmp_fast2, tmp_fast1_ok, tmp_fast1, tmp_xer_out, tmp_xer_in, tmp_spr1_ok, tmp_spr1, tmp_spro_ok, tmp_spro, tmp_reg3_ok, tmp_reg3, tmp_reg2_ok, tmp_reg2, tmp_reg1_ok, tmp_reg1, tmp_ea_ok, tmp_ea, tmp_rego_ok, tmp_rego, tmp_asmcode }; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1300" *) casez (\$32 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1300" */ 1'h1: begin fasto1 = 3'h3; @@ -78897,9 +78897,9 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r fasto2_ok = 1'h1; end endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1309" *) casez (\$34 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1309" */ 1'h1: begin fast1 = 3'h3; @@ -79001,20 +79001,20 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_SV_Etype; reg [1:0] dec22_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_SV_Ptype; reg [1:0] dec22_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec22_asmcode; reg [7:0] dec22_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_br; reg dec22_br; (* enum_base_type = "CRInSel" *) @@ -79026,7 +79026,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_cr_in; reg [2:0] dec22_cr_in; (* enum_base_type = "CROutSel" *) @@ -79036,17 +79036,17 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_cr_out; reg [2:0] dec22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_cry_in; reg [1:0] dec22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_cry_out; reg dec22_cry_out; (* enum_base_type = "Form" *) @@ -79080,7 +79080,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec22_form; reg [4:0] dec22_form; (* enum_base_type = "Function" *) @@ -79098,7 +79098,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec22_function_unit; reg [13:0] dec22_function_unit; (* enum_base_type = "In1Sel" *) @@ -79107,7 +79107,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_in1_sel; reg [2:0] dec22_in1_sel; (* enum_base_type = "In2Sel" *) @@ -79125,14 +79125,14 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec22_in2_sel; reg [3:0] dec22_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_in3_sel; reg [1:0] dec22_in3_sel; (* enum_base_type = "MicrOp" *) @@ -79210,16 +79210,16 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec22_internal_op; reg [6:0] dec22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_inv_a; reg dec22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_inv_out; reg dec22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_is_32b; reg dec22_is_32b; (* enum_base_type = "LdstLen" *) @@ -79228,10 +79228,10 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec22_ldst_len; reg [3:0] dec22_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_lk; reg dec22_lk; (* enum_base_type = "OutSel" *) @@ -79240,26 +79240,26 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_out_sel; reg [2:0] dec22_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_rc_sel; reg [1:0] dec22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_rsrv; reg dec22_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_sgl_pipe; reg dec22_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_sgn; reg dec22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_sgn_ext; reg dec22_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -79269,7 +79269,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_cr_in; reg [2:0] dec22_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -79279,7 +79279,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_cr_out; reg [2:0] dec22_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -79289,7 +79289,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_in1; reg [2:0] dec22_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -79299,7 +79299,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_in2; reg [2:0] dec22_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -79309,7 +79309,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_in3; reg [2:0] dec22_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -79319,7 +79319,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_out; reg [2:0] dec22_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -79329,7 +79329,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_out2; reg [2:0] dec22_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -79337,19 +79337,19 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_upd; reg [1:0] dec22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [3:0] opcode_switch; always @* begin if (\initial ) begin end dec22_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_function_unit = 14'h2000; endcase @@ -79357,9 +79357,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_cr_in = 3'h0; endcase @@ -79367,9 +79367,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_cr_out = 3'h1; endcase @@ -79377,9 +79377,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_sv_in1 = 3'h0; endcase @@ -79387,9 +79387,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_sv_in2 = 3'h0; endcase @@ -79397,9 +79397,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_sv_in3 = 3'h0; endcase @@ -79407,9 +79407,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_sv_out = 3'h0; endcase @@ -79417,9 +79417,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_sv_out2 = 3'h0; endcase @@ -79427,9 +79427,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_sv_cr_in = 3'h0; endcase @@ -79437,9 +79437,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_sv_cr_out = 3'h0; endcase @@ -79447,9 +79447,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_ldst_len = 4'h0; endcase @@ -79457,9 +79457,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_internal_op = 7'h4c; endcase @@ -79467,9 +79467,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_upd = 2'h0; endcase @@ -79477,9 +79477,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_rc_sel = 2'h2; endcase @@ -79487,9 +79487,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_cry_in = 2'h0; endcase @@ -79497,9 +79497,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_asmcode = 8'h9c; endcase @@ -79507,9 +79507,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_inv_a = 1'h0; endcase @@ -79517,9 +79517,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_inv_out = 1'h0; endcase @@ -79527,9 +79527,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_cry_out = 1'h0; endcase @@ -79537,9 +79537,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_br = 1'h0; endcase @@ -79547,9 +79547,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_sgn_ext = 1'h0; endcase @@ -79557,9 +79557,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_rsrv = 1'h0; endcase @@ -79567,9 +79567,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_form = 5'h1d; endcase @@ -79577,9 +79577,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_is_32b = 1'h0; endcase @@ -79587,9 +79587,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_sgn = 1'h0; endcase @@ -79597,9 +79597,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_lk = 1'h0; endcase @@ -79607,9 +79607,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_sgl_pipe = 1'h0; endcase @@ -79617,9 +79617,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_SV_Etype = 2'h0; endcase @@ -79627,9 +79627,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_SV_Ptype = 2'h0; endcase @@ -79637,9 +79637,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_in1_sel = 3'h2; endcase @@ -79647,9 +79647,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_in2_sel = 4'h0; endcase @@ -79657,9 +79657,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_in3_sel = 2'h0; endcase @@ -79667,9 +79667,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec22_out_sel = 3'h4; endcase @@ -79685,20 +79685,20 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_SV_Etype; reg [1:0] dec30_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_SV_Ptype; reg [1:0] dec30_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec30_asmcode; reg [7:0] dec30_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_br; reg dec30_br; (* enum_base_type = "CRInSel" *) @@ -79710,7 +79710,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_cr_in; reg [2:0] dec30_cr_in; (* enum_base_type = "CROutSel" *) @@ -79720,17 +79720,17 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_cr_out; reg [2:0] dec30_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_cry_in; reg [1:0] dec30_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_cry_out; reg dec30_cry_out; (* enum_base_type = "Form" *) @@ -79764,7 +79764,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec30_form; reg [4:0] dec30_form; (* enum_base_type = "Function" *) @@ -79782,7 +79782,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec30_function_unit; reg [13:0] dec30_function_unit; (* enum_base_type = "In1Sel" *) @@ -79791,7 +79791,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_in1_sel; reg [2:0] dec30_in1_sel; (* enum_base_type = "In2Sel" *) @@ -79809,14 +79809,14 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec30_in2_sel; reg [3:0] dec30_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_in3_sel; reg [1:0] dec30_in3_sel; (* enum_base_type = "MicrOp" *) @@ -79894,16 +79894,16 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec30_internal_op; reg [6:0] dec30_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_inv_a; reg dec30_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_inv_out; reg dec30_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_is_32b; reg dec30_is_32b; (* enum_base_type = "LdstLen" *) @@ -79912,10 +79912,10 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec30_ldst_len; reg [3:0] dec30_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_lk; reg dec30_lk; (* enum_base_type = "OutSel" *) @@ -79924,26 +79924,26 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_out_sel; reg [2:0] dec30_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_rc_sel; reg [1:0] dec30_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_rsrv; reg dec30_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_sgl_pipe; reg dec30_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_sgn; reg dec30_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_sgn_ext; reg dec30_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -79953,7 +79953,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_cr_in; reg [2:0] dec30_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -79963,7 +79963,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_cr_out; reg [2:0] dec30_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -79973,7 +79973,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_in1; reg [2:0] dec30_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -79983,7 +79983,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_in2; reg [2:0] dec30_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -79993,7 +79993,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_in3; reg [2:0] dec30_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -80003,7 +80003,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_out; reg [2:0] dec30_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -80013,7 +80013,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_out2; reg [2:0] dec30_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -80021,46 +80021,46 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_upd; reg [1:0] dec30_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [3:0] opcode_switch; always @* begin if (\initial ) begin end dec30_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_function_unit = 14'h0008; endcase @@ -80068,36 +80068,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_cr_in = 3'h0; endcase @@ -80105,36 +80105,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_cr_out = 3'h1; endcase @@ -80142,36 +80142,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_sv_in1 = 3'h0; endcase @@ -80179,36 +80179,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_sv_in2 = 3'h2; endcase @@ -80216,36 +80216,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_sv_in3 = 3'h3; endcase @@ -80253,36 +80253,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_sv_out = 3'h1; endcase @@ -80290,36 +80290,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_sv_out2 = 3'h0; endcase @@ -80327,36 +80327,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_sv_cr_in = 3'h0; endcase @@ -80364,36 +80364,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_sv_cr_out = 3'h1; endcase @@ -80401,36 +80401,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_ldst_len = 4'h0; endcase @@ -80438,36 +80438,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_internal_op = 7'h3a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_internal_op = 7'h3a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_internal_op = 7'h3a; endcase @@ -80475,36 +80475,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_upd = 2'h0; endcase @@ -80512,36 +80512,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_rc_sel = 2'h2; endcase @@ -80549,36 +80549,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_cry_in = 2'h0; endcase @@ -80586,36 +80586,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_asmcode = 8'h94; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_asmcode = 8'h94; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_asmcode = 8'h95; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_asmcode = 8'h95; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_asmcode = 8'h96; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_asmcode = 8'h96; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_asmcode = 8'h97; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_asmcode = 8'h97; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_asmcode = 8'h92; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_asmcode = 8'h93; endcase @@ -80623,36 +80623,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_inv_a = 1'h0; endcase @@ -80660,36 +80660,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_inv_out = 1'h0; endcase @@ -80697,36 +80697,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_cry_out = 1'h0; endcase @@ -80734,36 +80734,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_br = 1'h0; endcase @@ -80771,36 +80771,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_sgn_ext = 1'h0; endcase @@ -80808,36 +80808,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_rsrv = 1'h0; endcase @@ -80845,36 +80845,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_form = 5'h15; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_form = 5'h15; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_form = 5'h14; endcase @@ -80882,36 +80882,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_is_32b = 1'h0; endcase @@ -80919,36 +80919,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_sgn = 1'h0; endcase @@ -80956,36 +80956,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_lk = 1'h0; endcase @@ -80993,36 +80993,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_sgl_pipe = 1'h0; endcase @@ -81030,36 +81030,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_SV_Etype = 2'h2; endcase @@ -81067,36 +81067,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_SV_Ptype = 2'h1; endcase @@ -81104,36 +81104,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_in1_sel = 3'h0; endcase @@ -81141,36 +81141,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_in2_sel = 4'h1; endcase @@ -81178,36 +81178,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_in3_sel = 2'h1; endcase @@ -81215,36 +81215,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h4: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h5: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h0: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h1: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h2: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h3: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h6: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h7: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h8: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 4'h9: dec30_out_sel = 3'h2; endcase @@ -81260,20 +81260,20 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_SV_Etype; reg [1:0] dec31_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_SV_Ptype; reg [1:0] dec31_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_asmcode; reg [7:0] dec31_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_br; reg dec31_br; (* enum_base_type = "CRInSel" *) @@ -81285,7 +81285,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_cr_in; reg [2:0] dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -81295,34 +81295,34 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_cr_out; reg [2:0] dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_cry_in; reg [1:0] dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_cry_out; reg dec31_cry_out; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub0_dec31_dec_sub0_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub0_dec31_dec_sub0_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub0_dec31_dec_sub0_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -81333,7 +81333,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -81342,15 +81342,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub0_dec31_dec_sub0_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -81383,7 +81383,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub0_dec31_dec_sub0_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -81400,7 +81400,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub0_dec31_dec_sub0_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -81408,7 +81408,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -81425,13 +81425,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub0_dec31_dec_sub0_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub0_dec31_dec_sub0_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -81508,13 +81508,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub0_dec31_dec_sub0_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -81522,9 +81522,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub0_dec31_dec_sub0_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -81532,21 +81532,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub0_dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81555,7 +81555,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81564,7 +81564,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81573,7 +81573,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81582,7 +81582,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81591,7 +81591,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81600,7 +81600,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81609,32 +81609,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub0_dec31_dec_sub0_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub0_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub10_dec31_dec_sub10_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub10_dec31_dec_sub10_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub10_dec31_dec_sub10_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub10_dec31_dec_sub10_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -81645,7 +81645,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -81654,15 +81654,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub10_dec31_dec_sub10_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub10_dec31_dec_sub10_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -81695,7 +81695,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub10_dec31_dec_sub10_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -81712,7 +81712,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub10_dec31_dec_sub10_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -81720,7 +81720,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -81737,13 +81737,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub10_dec31_dec_sub10_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub10_dec31_dec_sub10_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -81820,13 +81820,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub10_dec31_dec_sub10_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub10_dec31_dec_sub10_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub10_dec31_dec_sub10_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub10_dec31_dec_sub10_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -81834,9 +81834,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub10_dec31_dec_sub10_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub10_dec31_dec_sub10_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -81844,21 +81844,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub10_dec31_dec_sub10_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub10_dec31_dec_sub10_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub10_dec31_dec_sub10_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub10_dec31_dec_sub10_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub10_dec31_dec_sub10_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81867,7 +81867,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81876,7 +81876,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81885,7 +81885,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81894,7 +81894,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81903,7 +81903,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81912,7 +81912,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -81921,32 +81921,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub10_dec31_dec_sub10_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub10_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub11_dec31_dec_sub11_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub11_dec31_dec_sub11_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub11_dec31_dec_sub11_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub11_dec31_dec_sub11_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -81957,7 +81957,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -81966,15 +81966,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub11_dec31_dec_sub11_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub11_dec31_dec_sub11_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -82007,7 +82007,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub11_dec31_dec_sub11_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -82024,7 +82024,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub11_dec31_dec_sub11_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -82032,7 +82032,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -82049,13 +82049,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub11_dec31_dec_sub11_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub11_dec31_dec_sub11_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -82132,13 +82132,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub11_dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub11_dec31_dec_sub11_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub11_dec31_dec_sub11_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub11_dec31_dec_sub11_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -82146,9 +82146,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub11_dec31_dec_sub11_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub11_dec31_dec_sub11_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -82156,21 +82156,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub11_dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub11_dec31_dec_sub11_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub11_dec31_dec_sub11_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub11_dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub11_dec31_dec_sub11_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82179,7 +82179,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82188,7 +82188,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82197,7 +82197,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82206,7 +82206,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82215,7 +82215,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82224,7 +82224,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82233,32 +82233,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub11_dec31_dec_sub11_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub11_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub15_dec31_dec_sub15_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub15_dec31_dec_sub15_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub15_dec31_dec_sub15_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub15_dec31_dec_sub15_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -82269,7 +82269,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -82278,15 +82278,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub15_dec31_dec_sub15_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub15_dec31_dec_sub15_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -82319,7 +82319,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub15_dec31_dec_sub15_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -82336,7 +82336,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub15_dec31_dec_sub15_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -82344,7 +82344,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -82361,13 +82361,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub15_dec31_dec_sub15_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub15_dec31_dec_sub15_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -82444,13 +82444,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub15_dec31_dec_sub15_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub15_dec31_dec_sub15_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub15_dec31_dec_sub15_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub15_dec31_dec_sub15_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -82458,9 +82458,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub15_dec31_dec_sub15_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub15_dec31_dec_sub15_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -82468,21 +82468,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub15_dec31_dec_sub15_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub15_dec31_dec_sub15_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub15_dec31_dec_sub15_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub15_dec31_dec_sub15_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub15_dec31_dec_sub15_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82491,7 +82491,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82500,7 +82500,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82509,7 +82509,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82518,7 +82518,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82527,7 +82527,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82536,7 +82536,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82545,32 +82545,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub15_dec31_dec_sub15_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub15_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub16_dec31_dec_sub16_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub16_dec31_dec_sub16_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub16_dec31_dec_sub16_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub16_dec31_dec_sub16_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -82581,7 +82581,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -82590,15 +82590,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub16_dec31_dec_sub16_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub16_dec31_dec_sub16_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -82631,7 +82631,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub16_dec31_dec_sub16_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -82648,7 +82648,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub16_dec31_dec_sub16_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -82656,7 +82656,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -82673,13 +82673,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub16_dec31_dec_sub16_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub16_dec31_dec_sub16_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -82756,13 +82756,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub16_dec31_dec_sub16_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub16_dec31_dec_sub16_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub16_dec31_dec_sub16_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub16_dec31_dec_sub16_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -82770,9 +82770,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub16_dec31_dec_sub16_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub16_dec31_dec_sub16_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -82780,21 +82780,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub16_dec31_dec_sub16_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub16_dec31_dec_sub16_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub16_dec31_dec_sub16_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub16_dec31_dec_sub16_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub16_dec31_dec_sub16_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82803,7 +82803,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82812,7 +82812,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82821,7 +82821,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82830,7 +82830,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82839,7 +82839,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82848,7 +82848,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -82857,32 +82857,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub16_dec31_dec_sub16_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub16_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub18_dec31_dec_sub18_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub18_dec31_dec_sub18_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub18_dec31_dec_sub18_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub18_dec31_dec_sub18_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -82893,7 +82893,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -82902,15 +82902,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub18_dec31_dec_sub18_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub18_dec31_dec_sub18_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -82943,7 +82943,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub18_dec31_dec_sub18_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -82960,7 +82960,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub18_dec31_dec_sub18_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -82968,7 +82968,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -82985,13 +82985,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub18_dec31_dec_sub18_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub18_dec31_dec_sub18_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -83068,13 +83068,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub18_dec31_dec_sub18_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub18_dec31_dec_sub18_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub18_dec31_dec_sub18_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub18_dec31_dec_sub18_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -83082,9 +83082,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub18_dec31_dec_sub18_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub18_dec31_dec_sub18_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -83092,21 +83092,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub18_dec31_dec_sub18_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub18_dec31_dec_sub18_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub18_dec31_dec_sub18_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub18_dec31_dec_sub18_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub18_dec31_dec_sub18_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83115,7 +83115,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83124,7 +83124,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83133,7 +83133,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83142,7 +83142,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83151,7 +83151,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83160,7 +83160,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83169,32 +83169,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub18_dec31_dec_sub18_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub18_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub19_dec31_dec_sub19_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub19_dec31_dec_sub19_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub19_dec31_dec_sub19_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub19_dec31_dec_sub19_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -83205,7 +83205,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -83214,15 +83214,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub19_dec31_dec_sub19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub19_dec31_dec_sub19_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -83255,7 +83255,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub19_dec31_dec_sub19_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -83272,7 +83272,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub19_dec31_dec_sub19_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -83280,7 +83280,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -83297,13 +83297,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub19_dec31_dec_sub19_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub19_dec31_dec_sub19_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -83380,13 +83380,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub19_dec31_dec_sub19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub19_dec31_dec_sub19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub19_dec31_dec_sub19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub19_dec31_dec_sub19_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -83394,9 +83394,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub19_dec31_dec_sub19_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub19_dec31_dec_sub19_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -83404,21 +83404,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub19_dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub19_dec31_dec_sub19_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub19_dec31_dec_sub19_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub19_dec31_dec_sub19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub19_dec31_dec_sub19_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83427,7 +83427,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83436,7 +83436,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83445,7 +83445,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83454,7 +83454,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83463,7 +83463,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83472,7 +83472,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83481,32 +83481,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub19_dec31_dec_sub19_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub19_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub20_dec31_dec_sub20_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub20_dec31_dec_sub20_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub20_dec31_dec_sub20_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub20_dec31_dec_sub20_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -83517,7 +83517,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -83526,15 +83526,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub20_dec31_dec_sub20_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub20_dec31_dec_sub20_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -83567,7 +83567,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub20_dec31_dec_sub20_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -83584,7 +83584,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub20_dec31_dec_sub20_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -83592,7 +83592,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -83609,13 +83609,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub20_dec31_dec_sub20_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub20_dec31_dec_sub20_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -83692,13 +83692,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub20_dec31_dec_sub20_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub20_dec31_dec_sub20_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub20_dec31_dec_sub20_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub20_dec31_dec_sub20_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -83706,9 +83706,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub20_dec31_dec_sub20_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub20_dec31_dec_sub20_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -83716,21 +83716,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub20_dec31_dec_sub20_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub20_dec31_dec_sub20_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub20_dec31_dec_sub20_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub20_dec31_dec_sub20_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub20_dec31_dec_sub20_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83739,7 +83739,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83748,7 +83748,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83757,7 +83757,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83766,7 +83766,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83775,7 +83775,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83784,7 +83784,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -83793,32 +83793,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub20_dec31_dec_sub20_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub20_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub21_dec31_dec_sub21_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub21_dec31_dec_sub21_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub21_dec31_dec_sub21_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub21_dec31_dec_sub21_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -83829,7 +83829,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -83838,15 +83838,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub21_dec31_dec_sub21_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub21_dec31_dec_sub21_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -83879,7 +83879,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub21_dec31_dec_sub21_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -83896,7 +83896,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub21_dec31_dec_sub21_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -83904,7 +83904,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -83921,13 +83921,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub21_dec31_dec_sub21_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub21_dec31_dec_sub21_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -84004,13 +84004,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub21_dec31_dec_sub21_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub21_dec31_dec_sub21_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub21_dec31_dec_sub21_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub21_dec31_dec_sub21_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -84018,9 +84018,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub21_dec31_dec_sub21_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub21_dec31_dec_sub21_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -84028,21 +84028,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub21_dec31_dec_sub21_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub21_dec31_dec_sub21_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub21_dec31_dec_sub21_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub21_dec31_dec_sub21_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub21_dec31_dec_sub21_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84051,7 +84051,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84060,7 +84060,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84069,7 +84069,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84078,7 +84078,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84087,7 +84087,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84096,7 +84096,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84105,32 +84105,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub21_dec31_dec_sub21_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub21_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub22_dec31_dec_sub22_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub22_dec31_dec_sub22_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub22_dec31_dec_sub22_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub22_dec31_dec_sub22_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -84141,7 +84141,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -84150,15 +84150,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub22_dec31_dec_sub22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub22_dec31_dec_sub22_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -84191,7 +84191,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub22_dec31_dec_sub22_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -84208,7 +84208,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub22_dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -84216,7 +84216,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -84233,13 +84233,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub22_dec31_dec_sub22_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub22_dec31_dec_sub22_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -84316,13 +84316,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub22_dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub22_dec31_dec_sub22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub22_dec31_dec_sub22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub22_dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -84330,9 +84330,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub22_dec31_dec_sub22_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub22_dec31_dec_sub22_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -84340,21 +84340,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub22_dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub22_dec31_dec_sub22_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub22_dec31_dec_sub22_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub22_dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub22_dec31_dec_sub22_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84363,7 +84363,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84372,7 +84372,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84381,7 +84381,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84390,7 +84390,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84399,7 +84399,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84408,7 +84408,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84417,32 +84417,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub22_dec31_dec_sub22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub22_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub23_dec31_dec_sub23_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub23_dec31_dec_sub23_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub23_dec31_dec_sub23_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub23_dec31_dec_sub23_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -84453,7 +84453,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -84462,15 +84462,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub23_dec31_dec_sub23_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub23_dec31_dec_sub23_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -84503,7 +84503,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub23_dec31_dec_sub23_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -84520,7 +84520,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub23_dec31_dec_sub23_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -84528,7 +84528,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -84545,13 +84545,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub23_dec31_dec_sub23_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub23_dec31_dec_sub23_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -84628,13 +84628,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub23_dec31_dec_sub23_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub23_dec31_dec_sub23_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub23_dec31_dec_sub23_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub23_dec31_dec_sub23_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -84642,9 +84642,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub23_dec31_dec_sub23_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub23_dec31_dec_sub23_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -84652,21 +84652,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub23_dec31_dec_sub23_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub23_dec31_dec_sub23_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub23_dec31_dec_sub23_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub23_dec31_dec_sub23_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub23_dec31_dec_sub23_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84675,7 +84675,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84684,7 +84684,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84693,7 +84693,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84702,7 +84702,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84711,7 +84711,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84720,7 +84720,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84729,32 +84729,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub23_dec31_dec_sub23_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub23_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub24_dec31_dec_sub24_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub24_dec31_dec_sub24_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub24_dec31_dec_sub24_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub24_dec31_dec_sub24_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -84765,7 +84765,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -84774,15 +84774,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub24_dec31_dec_sub24_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub24_dec31_dec_sub24_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -84815,7 +84815,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub24_dec31_dec_sub24_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -84832,7 +84832,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub24_dec31_dec_sub24_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -84840,7 +84840,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -84857,13 +84857,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub24_dec31_dec_sub24_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub24_dec31_dec_sub24_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -84940,13 +84940,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub24_dec31_dec_sub24_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub24_dec31_dec_sub24_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub24_dec31_dec_sub24_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub24_dec31_dec_sub24_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -84954,9 +84954,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub24_dec31_dec_sub24_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub24_dec31_dec_sub24_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -84964,21 +84964,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub24_dec31_dec_sub24_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub24_dec31_dec_sub24_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub24_dec31_dec_sub24_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub24_dec31_dec_sub24_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub24_dec31_dec_sub24_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84987,7 +84987,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -84996,7 +84996,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85005,7 +85005,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85014,7 +85014,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85023,7 +85023,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85032,7 +85032,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85041,32 +85041,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub24_dec31_dec_sub24_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub24_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub26_dec31_dec_sub26_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub26_dec31_dec_sub26_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub26_dec31_dec_sub26_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub26_dec31_dec_sub26_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -85077,7 +85077,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -85086,15 +85086,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub26_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub26_dec31_dec_sub26_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -85127,7 +85127,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub26_dec31_dec_sub26_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -85144,7 +85144,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub26_dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -85152,7 +85152,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -85169,13 +85169,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub26_dec31_dec_sub26_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub26_dec31_dec_sub26_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -85252,13 +85252,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub26_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub26_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub26_dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub26_dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -85266,9 +85266,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub26_dec31_dec_sub26_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub26_dec31_dec_sub26_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -85276,21 +85276,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub26_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub26_dec31_dec_sub26_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub26_dec31_dec_sub26_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub26_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub26_dec31_dec_sub26_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85299,7 +85299,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85308,7 +85308,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85317,7 +85317,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85326,7 +85326,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85335,7 +85335,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85344,7 +85344,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85353,32 +85353,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub26_dec31_dec_sub26_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub26_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub27_dec31_dec_sub27_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub27_dec31_dec_sub27_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub27_dec31_dec_sub27_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub27_dec31_dec_sub27_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -85389,7 +85389,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -85398,15 +85398,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub27_dec31_dec_sub27_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub27_dec31_dec_sub27_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -85439,7 +85439,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub27_dec31_dec_sub27_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -85456,7 +85456,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub27_dec31_dec_sub27_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -85464,7 +85464,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -85481,13 +85481,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub27_dec31_dec_sub27_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub27_dec31_dec_sub27_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -85564,13 +85564,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub27_dec31_dec_sub27_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub27_dec31_dec_sub27_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub27_dec31_dec_sub27_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub27_dec31_dec_sub27_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -85578,9 +85578,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub27_dec31_dec_sub27_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub27_dec31_dec_sub27_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -85588,21 +85588,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub27_dec31_dec_sub27_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub27_dec31_dec_sub27_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub27_dec31_dec_sub27_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub27_dec31_dec_sub27_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub27_dec31_dec_sub27_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85611,7 +85611,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85620,7 +85620,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85629,7 +85629,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85638,7 +85638,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85647,7 +85647,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85656,7 +85656,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85665,32 +85665,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub27_dec31_dec_sub27_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub27_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub28_dec31_dec_sub28_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub28_dec31_dec_sub28_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub28_dec31_dec_sub28_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub28_dec31_dec_sub28_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -85701,7 +85701,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -85710,15 +85710,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub28_dec31_dec_sub28_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub28_dec31_dec_sub28_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -85751,7 +85751,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub28_dec31_dec_sub28_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -85768,7 +85768,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub28_dec31_dec_sub28_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -85776,7 +85776,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -85793,13 +85793,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub28_dec31_dec_sub28_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub28_dec31_dec_sub28_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -85876,13 +85876,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub28_dec31_dec_sub28_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub28_dec31_dec_sub28_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub28_dec31_dec_sub28_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub28_dec31_dec_sub28_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -85890,9 +85890,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub28_dec31_dec_sub28_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub28_dec31_dec_sub28_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -85900,21 +85900,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub28_dec31_dec_sub28_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub28_dec31_dec_sub28_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub28_dec31_dec_sub28_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub28_dec31_dec_sub28_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub28_dec31_dec_sub28_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85923,7 +85923,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85932,7 +85932,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85941,7 +85941,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85950,7 +85950,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85959,7 +85959,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85968,7 +85968,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -85977,32 +85977,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub28_dec31_dec_sub28_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub28_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub4_dec31_dec_sub4_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub4_dec31_dec_sub4_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub4_dec31_dec_sub4_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub4_dec31_dec_sub4_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -86013,7 +86013,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -86022,15 +86022,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub4_dec31_dec_sub4_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub4_dec31_dec_sub4_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -86063,7 +86063,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub4_dec31_dec_sub4_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -86080,7 +86080,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub4_dec31_dec_sub4_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -86088,7 +86088,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -86105,13 +86105,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub4_dec31_dec_sub4_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub4_dec31_dec_sub4_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -86188,13 +86188,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub4_dec31_dec_sub4_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub4_dec31_dec_sub4_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub4_dec31_dec_sub4_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub4_dec31_dec_sub4_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -86202,9 +86202,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub4_dec31_dec_sub4_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub4_dec31_dec_sub4_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -86212,21 +86212,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub4_dec31_dec_sub4_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub4_dec31_dec_sub4_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub4_dec31_dec_sub4_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub4_dec31_dec_sub4_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub4_dec31_dec_sub4_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86235,7 +86235,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86244,7 +86244,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86253,7 +86253,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86262,7 +86262,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86271,7 +86271,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86280,7 +86280,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86289,32 +86289,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub4_dec31_dec_sub4_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub4_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub8_dec31_dec_sub8_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub8_dec31_dec_sub8_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub8_dec31_dec_sub8_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub8_dec31_dec_sub8_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -86325,7 +86325,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -86334,15 +86334,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub8_dec31_dec_sub8_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub8_dec31_dec_sub8_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -86375,7 +86375,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub8_dec31_dec_sub8_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -86392,7 +86392,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub8_dec31_dec_sub8_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -86400,7 +86400,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -86417,13 +86417,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub8_dec31_dec_sub8_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub8_dec31_dec_sub8_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -86500,13 +86500,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub8_dec31_dec_sub8_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub8_dec31_dec_sub8_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub8_dec31_dec_sub8_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub8_dec31_dec_sub8_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -86514,9 +86514,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub8_dec31_dec_sub8_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub8_dec31_dec_sub8_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -86524,21 +86524,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub8_dec31_dec_sub8_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub8_dec31_dec_sub8_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub8_dec31_dec_sub8_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub8_dec31_dec_sub8_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub8_dec31_dec_sub8_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86547,7 +86547,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86556,7 +86556,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86565,7 +86565,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86574,7 +86574,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86583,7 +86583,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86592,7 +86592,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86601,32 +86601,32 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub8_dec31_dec_sub8_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub8_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub9_dec31_dec_sub9_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub9_dec31_dec_sub9_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub9_dec31_dec_sub9_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -86637,7 +86637,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -86646,15 +86646,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub9_dec31_dec_sub9_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -86687,7 +86687,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub9_dec31_dec_sub9_form; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -86704,7 +86704,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec31_dec_sub9_dec31_dec_sub9_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -86712,7 +86712,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -86729,13 +86729,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub9_dec31_dec_sub9_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub9_dec31_dec_sub9_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -86812,13 +86812,13 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub9_dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -86826,9 +86826,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub9_dec31_dec_sub9_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -86836,21 +86836,21 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub9_dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86859,7 +86859,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86868,7 +86868,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86877,7 +86877,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86886,7 +86886,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86895,7 +86895,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86904,7 +86904,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86913,16 +86913,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub9_dec31_dec_sub9_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec31_dec_sub9_opcode_in; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -86955,7 +86955,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_form; reg [4:0] dec31_form; (* enum_base_type = "Function" *) @@ -86973,7 +86973,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_function_unit; reg [13:0] dec31_function_unit; (* enum_base_type = "In1Sel" *) @@ -86982,7 +86982,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_in1_sel; reg [2:0] dec31_in1_sel; (* enum_base_type = "In2Sel" *) @@ -87000,14 +87000,14 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_in2_sel; reg [3:0] dec31_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_in3_sel; reg [1:0] dec31_in3_sel; (* enum_base_type = "MicrOp" *) @@ -87085,16 +87085,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_internal_op; reg [6:0] dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_inv_a; reg dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_inv_out; reg dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_is_32b; reg dec31_is_32b; (* enum_base_type = "LdstLen" *) @@ -87103,10 +87103,10 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_ldst_len; reg [3:0] dec31_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_lk; reg dec31_lk; (* enum_base_type = "OutSel" *) @@ -87115,26 +87115,26 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_out_sel; reg [2:0] dec31_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_rc_sel; reg [1:0] dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_rsrv; reg dec31_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_sgl_pipe; reg dec31_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_sgn; reg dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_sgn_ext; reg dec31_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -87144,7 +87144,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_cr_in; reg [2:0] dec31_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -87154,7 +87154,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_cr_out; reg [2:0] dec31_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -87164,7 +87164,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_in1; reg [2:0] dec31_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -87174,7 +87174,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_in2; reg [2:0] dec31_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -87184,7 +87184,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_in3; reg [2:0] dec31_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -87194,7 +87194,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_out; reg [2:0] dec31_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -87204,7 +87204,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_out2; reg [2:0] dec31_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -87212,14 +87212,14 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_upd; reg [1:0] dec31_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:349" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [9:0] opcode_switch; dec31_dec_sub0 dec31_dec_sub0 ( .dec31_dec_sub0_SV_Etype(dec31_dec_sub0_dec31_dec_sub0_SV_Etype), @@ -87872,60 +87872,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_function_unit = dec31_dec_sub10_dec31_dec_sub10_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_function_unit = dec31_dec_sub28_dec31_dec_sub28_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_function_unit = dec31_dec_sub0_dec31_dec_sub0_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_function_unit = dec31_dec_sub26_dec31_dec_sub26_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_function_unit = dec31_dec_sub19_dec31_dec_sub19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_function_unit = dec31_dec_sub22_dec31_dec_sub22_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_function_unit = dec31_dec_sub9_dec31_dec_sub9_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_function_unit = dec31_dec_sub11_dec31_dec_sub11_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_function_unit = dec31_dec_sub27_dec31_dec_sub27_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_function_unit = dec31_dec_sub15_dec31_dec_sub15_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_function_unit = dec31_dec_sub20_dec31_dec_sub20_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_function_unit = dec31_dec_sub21_dec31_dec_sub21_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_function_unit = dec31_dec_sub23_dec31_dec_sub23_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_function_unit = dec31_dec_sub16_dec31_dec_sub16_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_function_unit = dec31_dec_sub18_dec31_dec_sub18_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_function_unit = dec31_dec_sub8_dec31_dec_sub8_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_function_unit = dec31_dec_sub24_dec31_dec_sub24_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_function_unit = dec31_dec_sub4_dec31_dec_sub4_function_unit; endcase @@ -87933,60 +87933,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_internal_op = dec31_dec_sub10_dec31_dec_sub10_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_internal_op = dec31_dec_sub28_dec31_dec_sub28_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_internal_op = dec31_dec_sub0_dec31_dec_sub0_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_internal_op = dec31_dec_sub26_dec31_dec_sub26_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_internal_op = dec31_dec_sub19_dec31_dec_sub19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_internal_op = dec31_dec_sub22_dec31_dec_sub22_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_internal_op = dec31_dec_sub9_dec31_dec_sub9_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_internal_op = dec31_dec_sub11_dec31_dec_sub11_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_internal_op = dec31_dec_sub27_dec31_dec_sub27_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_internal_op = dec31_dec_sub15_dec31_dec_sub15_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_internal_op = dec31_dec_sub20_dec31_dec_sub20_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_internal_op = dec31_dec_sub21_dec31_dec_sub21_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_internal_op = dec31_dec_sub23_dec31_dec_sub23_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_internal_op = dec31_dec_sub16_dec31_dec_sub16_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_internal_op = dec31_dec_sub18_dec31_dec_sub18_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_internal_op = dec31_dec_sub8_dec31_dec_sub8_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_internal_op = dec31_dec_sub24_dec31_dec_sub24_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_internal_op = dec31_dec_sub4_dec31_dec_sub4_internal_op; endcase @@ -87994,60 +87994,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_form = dec31_dec_sub10_dec31_dec_sub10_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_form = dec31_dec_sub28_dec31_dec_sub28_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_form = dec31_dec_sub0_dec31_dec_sub0_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_form = dec31_dec_sub26_dec31_dec_sub26_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_form = dec31_dec_sub19_dec31_dec_sub19_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_form = dec31_dec_sub22_dec31_dec_sub22_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_form = dec31_dec_sub9_dec31_dec_sub9_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_form = dec31_dec_sub11_dec31_dec_sub11_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_form = dec31_dec_sub27_dec31_dec_sub27_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_form = dec31_dec_sub15_dec31_dec_sub15_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_form = dec31_dec_sub20_dec31_dec_sub20_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_form = dec31_dec_sub21_dec31_dec_sub21_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_form = dec31_dec_sub23_dec31_dec_sub23_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_form = dec31_dec_sub16_dec31_dec_sub16_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_form = dec31_dec_sub18_dec31_dec_sub18_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_form = dec31_dec_sub8_dec31_dec_sub8_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_form = dec31_dec_sub24_dec31_dec_sub24_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_form = dec31_dec_sub4_dec31_dec_sub4_form; endcase @@ -88055,60 +88055,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_asmcode = dec31_dec_sub10_dec31_dec_sub10_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_asmcode = dec31_dec_sub28_dec31_dec_sub28_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_asmcode = dec31_dec_sub0_dec31_dec_sub0_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_asmcode = dec31_dec_sub26_dec31_dec_sub26_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_asmcode = dec31_dec_sub19_dec31_dec_sub19_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_asmcode = dec31_dec_sub22_dec31_dec_sub22_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_asmcode = dec31_dec_sub9_dec31_dec_sub9_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_asmcode = dec31_dec_sub11_dec31_dec_sub11_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_asmcode = dec31_dec_sub27_dec31_dec_sub27_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_asmcode = dec31_dec_sub15_dec31_dec_sub15_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_asmcode = dec31_dec_sub20_dec31_dec_sub20_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_asmcode = dec31_dec_sub21_dec31_dec_sub21_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_asmcode = dec31_dec_sub23_dec31_dec_sub23_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_asmcode = dec31_dec_sub16_dec31_dec_sub16_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_asmcode = dec31_dec_sub18_dec31_dec_sub18_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_asmcode = dec31_dec_sub8_dec31_dec_sub8_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_asmcode = dec31_dec_sub24_dec31_dec_sub24_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_asmcode = dec31_dec_sub4_dec31_dec_sub4_asmcode; endcase @@ -88116,60 +88116,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_SV_Etype = dec31_dec_sub10_dec31_dec_sub10_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_SV_Etype = dec31_dec_sub28_dec31_dec_sub28_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_SV_Etype = dec31_dec_sub0_dec31_dec_sub0_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_SV_Etype = dec31_dec_sub26_dec31_dec_sub26_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_SV_Etype = dec31_dec_sub19_dec31_dec_sub19_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_SV_Etype = dec31_dec_sub22_dec31_dec_sub22_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_SV_Etype = dec31_dec_sub9_dec31_dec_sub9_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_SV_Etype = dec31_dec_sub11_dec31_dec_sub11_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_SV_Etype = dec31_dec_sub27_dec31_dec_sub27_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_SV_Etype = dec31_dec_sub15_dec31_dec_sub15_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_SV_Etype = dec31_dec_sub20_dec31_dec_sub20_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_SV_Etype = dec31_dec_sub21_dec31_dec_sub21_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_SV_Etype = dec31_dec_sub23_dec31_dec_sub23_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_SV_Etype = dec31_dec_sub16_dec31_dec_sub16_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_SV_Etype = dec31_dec_sub18_dec31_dec_sub18_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_SV_Etype = dec31_dec_sub8_dec31_dec_sub8_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_SV_Etype = dec31_dec_sub24_dec31_dec_sub24_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_SV_Etype = dec31_dec_sub4_dec31_dec_sub4_SV_Etype; endcase @@ -88177,60 +88177,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_SV_Ptype = dec31_dec_sub10_dec31_dec_sub10_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_SV_Ptype = dec31_dec_sub28_dec31_dec_sub28_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_SV_Ptype = dec31_dec_sub0_dec31_dec_sub0_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_SV_Ptype = dec31_dec_sub26_dec31_dec_sub26_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_SV_Ptype = dec31_dec_sub19_dec31_dec_sub19_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_SV_Ptype = dec31_dec_sub22_dec31_dec_sub22_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_SV_Ptype = dec31_dec_sub9_dec31_dec_sub9_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_SV_Ptype = dec31_dec_sub11_dec31_dec_sub11_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_SV_Ptype = dec31_dec_sub27_dec31_dec_sub27_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_SV_Ptype = dec31_dec_sub15_dec31_dec_sub15_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_SV_Ptype = dec31_dec_sub20_dec31_dec_sub20_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_SV_Ptype = dec31_dec_sub21_dec31_dec_sub21_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_SV_Ptype = dec31_dec_sub23_dec31_dec_sub23_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_SV_Ptype = dec31_dec_sub16_dec31_dec_sub16_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_SV_Ptype = dec31_dec_sub18_dec31_dec_sub18_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_SV_Ptype = dec31_dec_sub8_dec31_dec_sub8_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_SV_Ptype = dec31_dec_sub24_dec31_dec_sub24_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_SV_Ptype = dec31_dec_sub4_dec31_dec_sub4_SV_Ptype; endcase @@ -88238,60 +88238,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_in1_sel = dec31_dec_sub10_dec31_dec_sub10_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_in1_sel = dec31_dec_sub28_dec31_dec_sub28_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_in1_sel = dec31_dec_sub0_dec31_dec_sub0_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_in1_sel = dec31_dec_sub26_dec31_dec_sub26_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_in1_sel = dec31_dec_sub19_dec31_dec_sub19_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_in1_sel = dec31_dec_sub22_dec31_dec_sub22_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_in1_sel = dec31_dec_sub9_dec31_dec_sub9_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_in1_sel = dec31_dec_sub11_dec31_dec_sub11_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_in1_sel = dec31_dec_sub27_dec31_dec_sub27_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_in1_sel = dec31_dec_sub15_dec31_dec_sub15_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_in1_sel = dec31_dec_sub20_dec31_dec_sub20_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_in1_sel = dec31_dec_sub21_dec31_dec_sub21_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_in1_sel = dec31_dec_sub23_dec31_dec_sub23_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_in1_sel = dec31_dec_sub16_dec31_dec_sub16_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_in1_sel = dec31_dec_sub18_dec31_dec_sub18_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_in1_sel = dec31_dec_sub8_dec31_dec_sub8_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_in1_sel = dec31_dec_sub24_dec31_dec_sub24_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_in1_sel = dec31_dec_sub4_dec31_dec_sub4_in1_sel; endcase @@ -88299,60 +88299,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_in2_sel = dec31_dec_sub10_dec31_dec_sub10_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_in2_sel = dec31_dec_sub28_dec31_dec_sub28_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_in2_sel = dec31_dec_sub0_dec31_dec_sub0_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_in2_sel = dec31_dec_sub26_dec31_dec_sub26_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_in2_sel = dec31_dec_sub19_dec31_dec_sub19_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_in2_sel = dec31_dec_sub22_dec31_dec_sub22_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_in2_sel = dec31_dec_sub9_dec31_dec_sub9_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_in2_sel = dec31_dec_sub11_dec31_dec_sub11_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_in2_sel = dec31_dec_sub27_dec31_dec_sub27_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_in2_sel = dec31_dec_sub15_dec31_dec_sub15_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_in2_sel = dec31_dec_sub20_dec31_dec_sub20_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_in2_sel = dec31_dec_sub21_dec31_dec_sub21_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_in2_sel = dec31_dec_sub23_dec31_dec_sub23_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_in2_sel = dec31_dec_sub16_dec31_dec_sub16_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_in2_sel = dec31_dec_sub18_dec31_dec_sub18_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_in2_sel = dec31_dec_sub8_dec31_dec_sub8_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_in2_sel = dec31_dec_sub24_dec31_dec_sub24_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_in2_sel = dec31_dec_sub4_dec31_dec_sub4_in2_sel; endcase @@ -88360,60 +88360,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_in3_sel = dec31_dec_sub10_dec31_dec_sub10_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_in3_sel = dec31_dec_sub28_dec31_dec_sub28_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_in3_sel = dec31_dec_sub0_dec31_dec_sub0_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_in3_sel = dec31_dec_sub26_dec31_dec_sub26_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_in3_sel = dec31_dec_sub19_dec31_dec_sub19_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_in3_sel = dec31_dec_sub22_dec31_dec_sub22_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_in3_sel = dec31_dec_sub9_dec31_dec_sub9_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_in3_sel = dec31_dec_sub11_dec31_dec_sub11_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_in3_sel = dec31_dec_sub27_dec31_dec_sub27_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_in3_sel = dec31_dec_sub15_dec31_dec_sub15_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_in3_sel = dec31_dec_sub20_dec31_dec_sub20_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_in3_sel = dec31_dec_sub21_dec31_dec_sub21_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_in3_sel = dec31_dec_sub23_dec31_dec_sub23_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_in3_sel = dec31_dec_sub16_dec31_dec_sub16_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_in3_sel = dec31_dec_sub18_dec31_dec_sub18_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_in3_sel = dec31_dec_sub8_dec31_dec_sub8_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_in3_sel = dec31_dec_sub24_dec31_dec_sub24_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_in3_sel = dec31_dec_sub4_dec31_dec_sub4_in3_sel; endcase @@ -88421,60 +88421,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_out_sel = dec31_dec_sub10_dec31_dec_sub10_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_out_sel = dec31_dec_sub28_dec31_dec_sub28_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_out_sel = dec31_dec_sub0_dec31_dec_sub0_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_out_sel = dec31_dec_sub26_dec31_dec_sub26_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_out_sel = dec31_dec_sub19_dec31_dec_sub19_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_out_sel = dec31_dec_sub22_dec31_dec_sub22_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_out_sel = dec31_dec_sub9_dec31_dec_sub9_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_out_sel = dec31_dec_sub11_dec31_dec_sub11_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_out_sel = dec31_dec_sub27_dec31_dec_sub27_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_out_sel = dec31_dec_sub15_dec31_dec_sub15_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_out_sel = dec31_dec_sub20_dec31_dec_sub20_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_out_sel = dec31_dec_sub21_dec31_dec_sub21_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_out_sel = dec31_dec_sub23_dec31_dec_sub23_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_out_sel = dec31_dec_sub16_dec31_dec_sub16_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_out_sel = dec31_dec_sub18_dec31_dec_sub18_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_out_sel = dec31_dec_sub8_dec31_dec_sub8_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_out_sel = dec31_dec_sub24_dec31_dec_sub24_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_out_sel = dec31_dec_sub4_dec31_dec_sub4_out_sel; endcase @@ -88482,60 +88482,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_cr_in = dec31_dec_sub10_dec31_dec_sub10_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_cr_in = dec31_dec_sub28_dec31_dec_sub28_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_cr_in = dec31_dec_sub0_dec31_dec_sub0_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_cr_in = dec31_dec_sub26_dec31_dec_sub26_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_cr_in = dec31_dec_sub19_dec31_dec_sub19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_cr_in = dec31_dec_sub22_dec31_dec_sub22_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_cr_in = dec31_dec_sub9_dec31_dec_sub9_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_cr_in = dec31_dec_sub11_dec31_dec_sub11_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_cr_in = dec31_dec_sub27_dec31_dec_sub27_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_cr_in = dec31_dec_sub15_dec31_dec_sub15_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_cr_in = dec31_dec_sub20_dec31_dec_sub20_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_cr_in = dec31_dec_sub21_dec31_dec_sub21_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_cr_in = dec31_dec_sub23_dec31_dec_sub23_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_cr_in = dec31_dec_sub16_dec31_dec_sub16_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_cr_in = dec31_dec_sub18_dec31_dec_sub18_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_cr_in = dec31_dec_sub8_dec31_dec_sub8_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_cr_in = dec31_dec_sub24_dec31_dec_sub24_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_cr_in = dec31_dec_sub4_dec31_dec_sub4_cr_in; endcase @@ -88543,60 +88543,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_cr_out = dec31_dec_sub10_dec31_dec_sub10_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_cr_out = dec31_dec_sub28_dec31_dec_sub28_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_cr_out = dec31_dec_sub0_dec31_dec_sub0_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_cr_out = dec31_dec_sub26_dec31_dec_sub26_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_cr_out = dec31_dec_sub19_dec31_dec_sub19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_cr_out = dec31_dec_sub22_dec31_dec_sub22_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_cr_out = dec31_dec_sub9_dec31_dec_sub9_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_cr_out = dec31_dec_sub11_dec31_dec_sub11_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_cr_out = dec31_dec_sub27_dec31_dec_sub27_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_cr_out = dec31_dec_sub15_dec31_dec_sub15_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_cr_out = dec31_dec_sub20_dec31_dec_sub20_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_cr_out = dec31_dec_sub21_dec31_dec_sub21_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_cr_out = dec31_dec_sub23_dec31_dec_sub23_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_cr_out = dec31_dec_sub16_dec31_dec_sub16_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_cr_out = dec31_dec_sub18_dec31_dec_sub18_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_cr_out = dec31_dec_sub8_dec31_dec_sub8_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_cr_out = dec31_dec_sub24_dec31_dec_sub24_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_cr_out = dec31_dec_sub4_dec31_dec_sub4_cr_out; endcase @@ -88604,60 +88604,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_sv_in1 = dec31_dec_sub10_dec31_dec_sub10_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_sv_in1 = dec31_dec_sub28_dec31_dec_sub28_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_sv_in1 = dec31_dec_sub0_dec31_dec_sub0_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_sv_in1 = dec31_dec_sub26_dec31_dec_sub26_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_sv_in1 = dec31_dec_sub19_dec31_dec_sub19_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_sv_in1 = dec31_dec_sub22_dec31_dec_sub22_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_sv_in1 = dec31_dec_sub9_dec31_dec_sub9_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_sv_in1 = dec31_dec_sub11_dec31_dec_sub11_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_sv_in1 = dec31_dec_sub27_dec31_dec_sub27_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_sv_in1 = dec31_dec_sub15_dec31_dec_sub15_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_sv_in1 = dec31_dec_sub20_dec31_dec_sub20_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_sv_in1 = dec31_dec_sub21_dec31_dec_sub21_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_sv_in1 = dec31_dec_sub23_dec31_dec_sub23_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_sv_in1 = dec31_dec_sub16_dec31_dec_sub16_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_sv_in1 = dec31_dec_sub18_dec31_dec_sub18_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_sv_in1 = dec31_dec_sub8_dec31_dec_sub8_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_sv_in1 = dec31_dec_sub24_dec31_dec_sub24_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_sv_in1 = dec31_dec_sub4_dec31_dec_sub4_sv_in1; endcase @@ -88665,60 +88665,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_sv_in2 = dec31_dec_sub10_dec31_dec_sub10_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_sv_in2 = dec31_dec_sub28_dec31_dec_sub28_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_sv_in2 = dec31_dec_sub0_dec31_dec_sub0_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_sv_in2 = dec31_dec_sub26_dec31_dec_sub26_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_sv_in2 = dec31_dec_sub19_dec31_dec_sub19_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_sv_in2 = dec31_dec_sub22_dec31_dec_sub22_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_sv_in2 = dec31_dec_sub9_dec31_dec_sub9_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_sv_in2 = dec31_dec_sub11_dec31_dec_sub11_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_sv_in2 = dec31_dec_sub27_dec31_dec_sub27_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_sv_in2 = dec31_dec_sub15_dec31_dec_sub15_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_sv_in2 = dec31_dec_sub20_dec31_dec_sub20_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_sv_in2 = dec31_dec_sub21_dec31_dec_sub21_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_sv_in2 = dec31_dec_sub23_dec31_dec_sub23_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_sv_in2 = dec31_dec_sub16_dec31_dec_sub16_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_sv_in2 = dec31_dec_sub18_dec31_dec_sub18_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_sv_in2 = dec31_dec_sub8_dec31_dec_sub8_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_sv_in2 = dec31_dec_sub24_dec31_dec_sub24_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_sv_in2 = dec31_dec_sub4_dec31_dec_sub4_sv_in2; endcase @@ -88726,60 +88726,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_sv_in3 = dec31_dec_sub10_dec31_dec_sub10_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_sv_in3 = dec31_dec_sub28_dec31_dec_sub28_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_sv_in3 = dec31_dec_sub0_dec31_dec_sub0_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_sv_in3 = dec31_dec_sub26_dec31_dec_sub26_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_sv_in3 = dec31_dec_sub19_dec31_dec_sub19_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_sv_in3 = dec31_dec_sub22_dec31_dec_sub22_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_sv_in3 = dec31_dec_sub9_dec31_dec_sub9_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_sv_in3 = dec31_dec_sub11_dec31_dec_sub11_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_sv_in3 = dec31_dec_sub27_dec31_dec_sub27_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_sv_in3 = dec31_dec_sub15_dec31_dec_sub15_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_sv_in3 = dec31_dec_sub20_dec31_dec_sub20_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_sv_in3 = dec31_dec_sub21_dec31_dec_sub21_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_sv_in3 = dec31_dec_sub23_dec31_dec_sub23_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_sv_in3 = dec31_dec_sub16_dec31_dec_sub16_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_sv_in3 = dec31_dec_sub18_dec31_dec_sub18_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_sv_in3 = dec31_dec_sub8_dec31_dec_sub8_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_sv_in3 = dec31_dec_sub24_dec31_dec_sub24_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_sv_in3 = dec31_dec_sub4_dec31_dec_sub4_sv_in3; endcase @@ -88787,60 +88787,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_sv_out = dec31_dec_sub10_dec31_dec_sub10_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_sv_out = dec31_dec_sub28_dec31_dec_sub28_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_sv_out = dec31_dec_sub0_dec31_dec_sub0_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_sv_out = dec31_dec_sub26_dec31_dec_sub26_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_sv_out = dec31_dec_sub19_dec31_dec_sub19_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_sv_out = dec31_dec_sub22_dec31_dec_sub22_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_sv_out = dec31_dec_sub9_dec31_dec_sub9_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_sv_out = dec31_dec_sub11_dec31_dec_sub11_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_sv_out = dec31_dec_sub27_dec31_dec_sub27_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_sv_out = dec31_dec_sub15_dec31_dec_sub15_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_sv_out = dec31_dec_sub20_dec31_dec_sub20_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_sv_out = dec31_dec_sub21_dec31_dec_sub21_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_sv_out = dec31_dec_sub23_dec31_dec_sub23_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_sv_out = dec31_dec_sub16_dec31_dec_sub16_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_sv_out = dec31_dec_sub18_dec31_dec_sub18_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_sv_out = dec31_dec_sub8_dec31_dec_sub8_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_sv_out = dec31_dec_sub24_dec31_dec_sub24_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_sv_out = dec31_dec_sub4_dec31_dec_sub4_sv_out; endcase @@ -88848,60 +88848,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_sv_out2 = dec31_dec_sub10_dec31_dec_sub10_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_sv_out2 = dec31_dec_sub28_dec31_dec_sub28_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_sv_out2 = dec31_dec_sub0_dec31_dec_sub0_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_sv_out2 = dec31_dec_sub26_dec31_dec_sub26_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_sv_out2 = dec31_dec_sub19_dec31_dec_sub19_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_sv_out2 = dec31_dec_sub22_dec31_dec_sub22_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_sv_out2 = dec31_dec_sub9_dec31_dec_sub9_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_sv_out2 = dec31_dec_sub11_dec31_dec_sub11_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_sv_out2 = dec31_dec_sub27_dec31_dec_sub27_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_sv_out2 = dec31_dec_sub15_dec31_dec_sub15_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_sv_out2 = dec31_dec_sub20_dec31_dec_sub20_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_sv_out2 = dec31_dec_sub21_dec31_dec_sub21_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_sv_out2 = dec31_dec_sub23_dec31_dec_sub23_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_sv_out2 = dec31_dec_sub16_dec31_dec_sub16_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_sv_out2 = dec31_dec_sub18_dec31_dec_sub18_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_sv_out2 = dec31_dec_sub8_dec31_dec_sub8_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_sv_out2 = dec31_dec_sub24_dec31_dec_sub24_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_sv_out2 = dec31_dec_sub4_dec31_dec_sub4_sv_out2; endcase @@ -88909,60 +88909,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_sv_cr_in = dec31_dec_sub10_dec31_dec_sub10_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_sv_cr_in = dec31_dec_sub28_dec31_dec_sub28_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_sv_cr_in = dec31_dec_sub0_dec31_dec_sub0_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_sv_cr_in = dec31_dec_sub26_dec31_dec_sub26_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_sv_cr_in = dec31_dec_sub19_dec31_dec_sub19_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_sv_cr_in = dec31_dec_sub22_dec31_dec_sub22_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_sv_cr_in = dec31_dec_sub9_dec31_dec_sub9_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_sv_cr_in = dec31_dec_sub11_dec31_dec_sub11_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_sv_cr_in = dec31_dec_sub27_dec31_dec_sub27_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_sv_cr_in = dec31_dec_sub15_dec31_dec_sub15_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_sv_cr_in = dec31_dec_sub20_dec31_dec_sub20_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_sv_cr_in = dec31_dec_sub21_dec31_dec_sub21_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_sv_cr_in = dec31_dec_sub23_dec31_dec_sub23_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_sv_cr_in = dec31_dec_sub16_dec31_dec_sub16_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_sv_cr_in = dec31_dec_sub18_dec31_dec_sub18_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_sv_cr_in = dec31_dec_sub8_dec31_dec_sub8_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_sv_cr_in = dec31_dec_sub24_dec31_dec_sub24_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_sv_cr_in = dec31_dec_sub4_dec31_dec_sub4_sv_cr_in; endcase @@ -88970,60 +88970,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_sv_cr_out = dec31_dec_sub10_dec31_dec_sub10_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_sv_cr_out = dec31_dec_sub28_dec31_dec_sub28_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_sv_cr_out = dec31_dec_sub0_dec31_dec_sub0_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_sv_cr_out = dec31_dec_sub26_dec31_dec_sub26_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_sv_cr_out = dec31_dec_sub19_dec31_dec_sub19_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_sv_cr_out = dec31_dec_sub22_dec31_dec_sub22_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_sv_cr_out = dec31_dec_sub9_dec31_dec_sub9_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_sv_cr_out = dec31_dec_sub11_dec31_dec_sub11_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_sv_cr_out = dec31_dec_sub27_dec31_dec_sub27_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_sv_cr_out = dec31_dec_sub15_dec31_dec_sub15_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_sv_cr_out = dec31_dec_sub20_dec31_dec_sub20_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_sv_cr_out = dec31_dec_sub21_dec31_dec_sub21_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_sv_cr_out = dec31_dec_sub23_dec31_dec_sub23_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_sv_cr_out = dec31_dec_sub16_dec31_dec_sub16_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_sv_cr_out = dec31_dec_sub18_dec31_dec_sub18_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_sv_cr_out = dec31_dec_sub8_dec31_dec_sub8_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_sv_cr_out = dec31_dec_sub24_dec31_dec_sub24_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_sv_cr_out = dec31_dec_sub4_dec31_dec_sub4_sv_cr_out; endcase @@ -89031,60 +89031,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_ldst_len = dec31_dec_sub10_dec31_dec_sub10_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_ldst_len = dec31_dec_sub28_dec31_dec_sub28_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_ldst_len = dec31_dec_sub0_dec31_dec_sub0_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_ldst_len = dec31_dec_sub26_dec31_dec_sub26_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_ldst_len = dec31_dec_sub19_dec31_dec_sub19_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_ldst_len = dec31_dec_sub22_dec31_dec_sub22_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_ldst_len = dec31_dec_sub9_dec31_dec_sub9_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_ldst_len = dec31_dec_sub11_dec31_dec_sub11_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_ldst_len = dec31_dec_sub27_dec31_dec_sub27_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_ldst_len = dec31_dec_sub15_dec31_dec_sub15_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_ldst_len = dec31_dec_sub20_dec31_dec_sub20_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_ldst_len = dec31_dec_sub21_dec31_dec_sub21_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_ldst_len = dec31_dec_sub23_dec31_dec_sub23_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_ldst_len = dec31_dec_sub16_dec31_dec_sub16_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_ldst_len = dec31_dec_sub18_dec31_dec_sub18_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_ldst_len = dec31_dec_sub8_dec31_dec_sub8_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_ldst_len = dec31_dec_sub24_dec31_dec_sub24_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_ldst_len = dec31_dec_sub4_dec31_dec_sub4_ldst_len; endcase @@ -89092,60 +89092,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_upd = dec31_dec_sub10_dec31_dec_sub10_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_upd = dec31_dec_sub28_dec31_dec_sub28_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_upd = dec31_dec_sub0_dec31_dec_sub0_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_upd = dec31_dec_sub26_dec31_dec_sub26_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_upd = dec31_dec_sub19_dec31_dec_sub19_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_upd = dec31_dec_sub22_dec31_dec_sub22_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_upd = dec31_dec_sub9_dec31_dec_sub9_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_upd = dec31_dec_sub11_dec31_dec_sub11_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_upd = dec31_dec_sub27_dec31_dec_sub27_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_upd = dec31_dec_sub15_dec31_dec_sub15_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_upd = dec31_dec_sub20_dec31_dec_sub20_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_upd = dec31_dec_sub21_dec31_dec_sub21_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_upd = dec31_dec_sub23_dec31_dec_sub23_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_upd = dec31_dec_sub16_dec31_dec_sub16_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_upd = dec31_dec_sub18_dec31_dec_sub18_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_upd = dec31_dec_sub8_dec31_dec_sub8_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_upd = dec31_dec_sub24_dec31_dec_sub24_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_upd = dec31_dec_sub4_dec31_dec_sub4_upd; endcase @@ -89153,60 +89153,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_rc_sel = dec31_dec_sub10_dec31_dec_sub10_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_rc_sel = dec31_dec_sub28_dec31_dec_sub28_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_rc_sel = dec31_dec_sub0_dec31_dec_sub0_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_rc_sel = dec31_dec_sub26_dec31_dec_sub26_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_rc_sel = dec31_dec_sub19_dec31_dec_sub19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_rc_sel = dec31_dec_sub22_dec31_dec_sub22_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_rc_sel = dec31_dec_sub9_dec31_dec_sub9_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_rc_sel = dec31_dec_sub11_dec31_dec_sub11_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_rc_sel = dec31_dec_sub27_dec31_dec_sub27_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_rc_sel = dec31_dec_sub15_dec31_dec_sub15_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_rc_sel = dec31_dec_sub20_dec31_dec_sub20_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_rc_sel = dec31_dec_sub21_dec31_dec_sub21_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_rc_sel = dec31_dec_sub23_dec31_dec_sub23_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_rc_sel = dec31_dec_sub16_dec31_dec_sub16_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_rc_sel = dec31_dec_sub18_dec31_dec_sub18_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_rc_sel = dec31_dec_sub8_dec31_dec_sub8_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_rc_sel = dec31_dec_sub24_dec31_dec_sub24_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_rc_sel = dec31_dec_sub4_dec31_dec_sub4_rc_sel; endcase @@ -89214,60 +89214,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_cry_in = dec31_dec_sub10_dec31_dec_sub10_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_cry_in = dec31_dec_sub28_dec31_dec_sub28_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_cry_in = dec31_dec_sub0_dec31_dec_sub0_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_cry_in = dec31_dec_sub26_dec31_dec_sub26_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_cry_in = dec31_dec_sub19_dec31_dec_sub19_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_cry_in = dec31_dec_sub22_dec31_dec_sub22_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_cry_in = dec31_dec_sub9_dec31_dec_sub9_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_cry_in = dec31_dec_sub11_dec31_dec_sub11_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_cry_in = dec31_dec_sub27_dec31_dec_sub27_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_cry_in = dec31_dec_sub15_dec31_dec_sub15_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_cry_in = dec31_dec_sub20_dec31_dec_sub20_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_cry_in = dec31_dec_sub21_dec31_dec_sub21_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_cry_in = dec31_dec_sub23_dec31_dec_sub23_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_cry_in = dec31_dec_sub16_dec31_dec_sub16_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_cry_in = dec31_dec_sub18_dec31_dec_sub18_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_cry_in = dec31_dec_sub8_dec31_dec_sub8_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_cry_in = dec31_dec_sub24_dec31_dec_sub24_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_cry_in = dec31_dec_sub4_dec31_dec_sub4_cry_in; endcase @@ -89275,60 +89275,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_inv_a = dec31_dec_sub10_dec31_dec_sub10_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_inv_a = dec31_dec_sub28_dec31_dec_sub28_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_inv_a = dec31_dec_sub0_dec31_dec_sub0_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_inv_a = dec31_dec_sub26_dec31_dec_sub26_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_inv_a = dec31_dec_sub19_dec31_dec_sub19_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_inv_a = dec31_dec_sub22_dec31_dec_sub22_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_inv_a = dec31_dec_sub9_dec31_dec_sub9_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_inv_a = dec31_dec_sub11_dec31_dec_sub11_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_inv_a = dec31_dec_sub27_dec31_dec_sub27_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_inv_a = dec31_dec_sub15_dec31_dec_sub15_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_inv_a = dec31_dec_sub20_dec31_dec_sub20_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_inv_a = dec31_dec_sub21_dec31_dec_sub21_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_inv_a = dec31_dec_sub23_dec31_dec_sub23_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_inv_a = dec31_dec_sub16_dec31_dec_sub16_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_inv_a = dec31_dec_sub18_dec31_dec_sub18_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_inv_a = dec31_dec_sub8_dec31_dec_sub8_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_inv_a = dec31_dec_sub24_dec31_dec_sub24_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_inv_a = dec31_dec_sub4_dec31_dec_sub4_inv_a; endcase @@ -89336,60 +89336,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_inv_out = dec31_dec_sub10_dec31_dec_sub10_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_inv_out = dec31_dec_sub28_dec31_dec_sub28_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_inv_out = dec31_dec_sub0_dec31_dec_sub0_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_inv_out = dec31_dec_sub26_dec31_dec_sub26_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_inv_out = dec31_dec_sub19_dec31_dec_sub19_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_inv_out = dec31_dec_sub22_dec31_dec_sub22_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_inv_out = dec31_dec_sub9_dec31_dec_sub9_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_inv_out = dec31_dec_sub11_dec31_dec_sub11_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_inv_out = dec31_dec_sub27_dec31_dec_sub27_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_inv_out = dec31_dec_sub15_dec31_dec_sub15_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_inv_out = dec31_dec_sub20_dec31_dec_sub20_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_inv_out = dec31_dec_sub21_dec31_dec_sub21_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_inv_out = dec31_dec_sub23_dec31_dec_sub23_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_inv_out = dec31_dec_sub16_dec31_dec_sub16_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_inv_out = dec31_dec_sub18_dec31_dec_sub18_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_inv_out = dec31_dec_sub8_dec31_dec_sub8_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_inv_out = dec31_dec_sub24_dec31_dec_sub24_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_inv_out = dec31_dec_sub4_dec31_dec_sub4_inv_out; endcase @@ -89397,60 +89397,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_cry_out = dec31_dec_sub10_dec31_dec_sub10_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_cry_out = dec31_dec_sub28_dec31_dec_sub28_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_cry_out = dec31_dec_sub0_dec31_dec_sub0_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_cry_out = dec31_dec_sub26_dec31_dec_sub26_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_cry_out = dec31_dec_sub19_dec31_dec_sub19_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_cry_out = dec31_dec_sub22_dec31_dec_sub22_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_cry_out = dec31_dec_sub9_dec31_dec_sub9_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_cry_out = dec31_dec_sub11_dec31_dec_sub11_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_cry_out = dec31_dec_sub27_dec31_dec_sub27_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_cry_out = dec31_dec_sub15_dec31_dec_sub15_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_cry_out = dec31_dec_sub20_dec31_dec_sub20_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_cry_out = dec31_dec_sub21_dec31_dec_sub21_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_cry_out = dec31_dec_sub23_dec31_dec_sub23_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_cry_out = dec31_dec_sub16_dec31_dec_sub16_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_cry_out = dec31_dec_sub18_dec31_dec_sub18_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_cry_out = dec31_dec_sub8_dec31_dec_sub8_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_cry_out = dec31_dec_sub24_dec31_dec_sub24_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_cry_out = dec31_dec_sub4_dec31_dec_sub4_cry_out; endcase @@ -89458,60 +89458,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_br = dec31_dec_sub10_dec31_dec_sub10_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_br = dec31_dec_sub28_dec31_dec_sub28_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_br = dec31_dec_sub0_dec31_dec_sub0_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_br = dec31_dec_sub26_dec31_dec_sub26_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_br = dec31_dec_sub19_dec31_dec_sub19_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_br = dec31_dec_sub22_dec31_dec_sub22_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_br = dec31_dec_sub9_dec31_dec_sub9_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_br = dec31_dec_sub11_dec31_dec_sub11_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_br = dec31_dec_sub27_dec31_dec_sub27_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_br = dec31_dec_sub15_dec31_dec_sub15_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_br = dec31_dec_sub20_dec31_dec_sub20_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_br = dec31_dec_sub21_dec31_dec_sub21_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_br = dec31_dec_sub23_dec31_dec_sub23_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_br = dec31_dec_sub16_dec31_dec_sub16_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_br = dec31_dec_sub18_dec31_dec_sub18_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_br = dec31_dec_sub8_dec31_dec_sub8_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_br = dec31_dec_sub24_dec31_dec_sub24_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_br = dec31_dec_sub4_dec31_dec_sub4_br; endcase @@ -89519,60 +89519,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_sgn_ext = dec31_dec_sub10_dec31_dec_sub10_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_sgn_ext = dec31_dec_sub28_dec31_dec_sub28_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_sgn_ext = dec31_dec_sub0_dec31_dec_sub0_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_sgn_ext = dec31_dec_sub26_dec31_dec_sub26_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_sgn_ext = dec31_dec_sub19_dec31_dec_sub19_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_sgn_ext = dec31_dec_sub22_dec31_dec_sub22_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_sgn_ext = dec31_dec_sub9_dec31_dec_sub9_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_sgn_ext = dec31_dec_sub11_dec31_dec_sub11_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_sgn_ext = dec31_dec_sub27_dec31_dec_sub27_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_sgn_ext = dec31_dec_sub15_dec31_dec_sub15_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_sgn_ext = dec31_dec_sub20_dec31_dec_sub20_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_sgn_ext = dec31_dec_sub21_dec31_dec_sub21_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_sgn_ext = dec31_dec_sub23_dec31_dec_sub23_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_sgn_ext = dec31_dec_sub16_dec31_dec_sub16_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_sgn_ext = dec31_dec_sub18_dec31_dec_sub18_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_sgn_ext = dec31_dec_sub8_dec31_dec_sub8_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_sgn_ext = dec31_dec_sub24_dec31_dec_sub24_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_sgn_ext = dec31_dec_sub4_dec31_dec_sub4_sgn_ext; endcase @@ -89580,60 +89580,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_rsrv = dec31_dec_sub10_dec31_dec_sub10_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_rsrv = dec31_dec_sub28_dec31_dec_sub28_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_rsrv = dec31_dec_sub0_dec31_dec_sub0_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_rsrv = dec31_dec_sub26_dec31_dec_sub26_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_rsrv = dec31_dec_sub19_dec31_dec_sub19_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_rsrv = dec31_dec_sub22_dec31_dec_sub22_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_rsrv = dec31_dec_sub9_dec31_dec_sub9_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_rsrv = dec31_dec_sub11_dec31_dec_sub11_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_rsrv = dec31_dec_sub27_dec31_dec_sub27_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_rsrv = dec31_dec_sub15_dec31_dec_sub15_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_rsrv = dec31_dec_sub20_dec31_dec_sub20_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_rsrv = dec31_dec_sub21_dec31_dec_sub21_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_rsrv = dec31_dec_sub23_dec31_dec_sub23_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_rsrv = dec31_dec_sub16_dec31_dec_sub16_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_rsrv = dec31_dec_sub18_dec31_dec_sub18_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_rsrv = dec31_dec_sub8_dec31_dec_sub8_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_rsrv = dec31_dec_sub24_dec31_dec_sub24_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_rsrv = dec31_dec_sub4_dec31_dec_sub4_rsrv; endcase @@ -89641,60 +89641,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_is_32b = dec31_dec_sub10_dec31_dec_sub10_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_is_32b = dec31_dec_sub28_dec31_dec_sub28_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_is_32b = dec31_dec_sub0_dec31_dec_sub0_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_is_32b = dec31_dec_sub26_dec31_dec_sub26_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_is_32b = dec31_dec_sub19_dec31_dec_sub19_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_is_32b = dec31_dec_sub22_dec31_dec_sub22_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_is_32b = dec31_dec_sub9_dec31_dec_sub9_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_is_32b = dec31_dec_sub11_dec31_dec_sub11_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_is_32b = dec31_dec_sub27_dec31_dec_sub27_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_is_32b = dec31_dec_sub15_dec31_dec_sub15_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_is_32b = dec31_dec_sub20_dec31_dec_sub20_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_is_32b = dec31_dec_sub21_dec31_dec_sub21_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_is_32b = dec31_dec_sub23_dec31_dec_sub23_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_is_32b = dec31_dec_sub16_dec31_dec_sub16_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_is_32b = dec31_dec_sub18_dec31_dec_sub18_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_is_32b = dec31_dec_sub8_dec31_dec_sub8_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_is_32b = dec31_dec_sub24_dec31_dec_sub24_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_is_32b = dec31_dec_sub4_dec31_dec_sub4_is_32b; endcase @@ -89702,60 +89702,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_sgn = dec31_dec_sub10_dec31_dec_sub10_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_sgn = dec31_dec_sub28_dec31_dec_sub28_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_sgn = dec31_dec_sub0_dec31_dec_sub0_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_sgn = dec31_dec_sub26_dec31_dec_sub26_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_sgn = dec31_dec_sub19_dec31_dec_sub19_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_sgn = dec31_dec_sub22_dec31_dec_sub22_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_sgn = dec31_dec_sub9_dec31_dec_sub9_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_sgn = dec31_dec_sub11_dec31_dec_sub11_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_sgn = dec31_dec_sub27_dec31_dec_sub27_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_sgn = dec31_dec_sub15_dec31_dec_sub15_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_sgn = dec31_dec_sub20_dec31_dec_sub20_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_sgn = dec31_dec_sub21_dec31_dec_sub21_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_sgn = dec31_dec_sub23_dec31_dec_sub23_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_sgn = dec31_dec_sub16_dec31_dec_sub16_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_sgn = dec31_dec_sub18_dec31_dec_sub18_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_sgn = dec31_dec_sub8_dec31_dec_sub8_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_sgn = dec31_dec_sub24_dec31_dec_sub24_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_sgn = dec31_dec_sub4_dec31_dec_sub4_sgn; endcase @@ -89763,60 +89763,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_lk = dec31_dec_sub10_dec31_dec_sub10_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_lk = dec31_dec_sub28_dec31_dec_sub28_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_lk = dec31_dec_sub0_dec31_dec_sub0_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_lk = dec31_dec_sub26_dec31_dec_sub26_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_lk = dec31_dec_sub19_dec31_dec_sub19_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_lk = dec31_dec_sub22_dec31_dec_sub22_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_lk = dec31_dec_sub9_dec31_dec_sub9_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_lk = dec31_dec_sub11_dec31_dec_sub11_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_lk = dec31_dec_sub27_dec31_dec_sub27_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_lk = dec31_dec_sub15_dec31_dec_sub15_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_lk = dec31_dec_sub20_dec31_dec_sub20_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_lk = dec31_dec_sub21_dec31_dec_sub21_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_lk = dec31_dec_sub23_dec31_dec_sub23_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_lk = dec31_dec_sub16_dec31_dec_sub16_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_lk = dec31_dec_sub18_dec31_dec_sub18_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_lk = dec31_dec_sub8_dec31_dec_sub8_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_lk = dec31_dec_sub24_dec31_dec_sub24_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_lk = dec31_dec_sub4_dec31_dec_sub4_lk; endcase @@ -89824,60 +89824,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_sgl_pipe = dec31_dec_sub10_dec31_dec_sub10_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_sgl_pipe = dec31_dec_sub28_dec31_dec_sub28_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_sgl_pipe = dec31_dec_sub0_dec31_dec_sub0_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_sgl_pipe = dec31_dec_sub26_dec31_dec_sub26_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_sgl_pipe = dec31_dec_sub19_dec31_dec_sub19_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_sgl_pipe = dec31_dec_sub22_dec31_dec_sub22_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_sgl_pipe = dec31_dec_sub9_dec31_dec_sub9_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_sgl_pipe = dec31_dec_sub11_dec31_dec_sub11_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_sgl_pipe = dec31_dec_sub27_dec31_dec_sub27_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_sgl_pipe = dec31_dec_sub15_dec31_dec_sub15_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_sgl_pipe = dec31_dec_sub20_dec31_dec_sub20_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_sgl_pipe = dec31_dec_sub21_dec31_dec_sub21_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_sgl_pipe = dec31_dec_sub23_dec31_dec_sub23_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_sgl_pipe = dec31_dec_sub16_dec31_dec_sub16_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_sgl_pipe = dec31_dec_sub18_dec31_dec_sub18_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_sgl_pipe = dec31_dec_sub8_dec31_dec_sub8_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_sgl_pipe = dec31_dec_sub24_dec31_dec_sub24_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_sgl_pipe = dec31_dec_sub4_dec31_dec_sub4_sgl_pipe; endcase @@ -89912,20 +89912,20 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_SV_Etype; reg [1:0] dec31_dec_sub0_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_SV_Ptype; reg [1:0] dec31_dec_sub0_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub0_asmcode; reg [7:0] dec31_dec_sub0_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_br; reg dec31_dec_sub0_br; (* enum_base_type = "CRInSel" *) @@ -89937,7 +89937,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_cr_in; reg [2:0] dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) @@ -89947,17 +89947,17 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_cr_out; reg [2:0] dec31_dec_sub0_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_cry_in; reg [1:0] dec31_dec_sub0_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_cry_out; reg dec31_dec_sub0_cry_out; (* enum_base_type = "Form" *) @@ -89991,7 +89991,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub0_form; reg [4:0] dec31_dec_sub0_form; (* enum_base_type = "Function" *) @@ -90009,7 +90009,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub0_function_unit; reg [13:0] dec31_dec_sub0_function_unit; (* enum_base_type = "In1Sel" *) @@ -90018,7 +90018,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_in1_sel; reg [2:0] dec31_dec_sub0_in1_sel; (* enum_base_type = "In2Sel" *) @@ -90036,14 +90036,14 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub0_in2_sel; reg [3:0] dec31_dec_sub0_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_in3_sel; reg [1:0] dec31_dec_sub0_in3_sel; (* enum_base_type = "MicrOp" *) @@ -90121,16 +90121,16 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub0_internal_op; reg [6:0] dec31_dec_sub0_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_inv_a; reg dec31_dec_sub0_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_inv_out; reg dec31_dec_sub0_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_is_32b; reg dec31_dec_sub0_is_32b; (* enum_base_type = "LdstLen" *) @@ -90139,10 +90139,10 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub0_ldst_len; reg [3:0] dec31_dec_sub0_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_lk; reg dec31_dec_sub0_lk; (* enum_base_type = "OutSel" *) @@ -90151,26 +90151,26 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_out_sel; reg [2:0] dec31_dec_sub0_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_rc_sel; reg [1:0] dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_rsrv; reg dec31_dec_sub0_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_sgl_pipe; reg dec31_dec_sub0_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_sgn; reg dec31_dec_sub0_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_sgn_ext; reg dec31_dec_sub0_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -90180,7 +90180,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_cr_in; reg [2:0] dec31_dec_sub0_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -90190,7 +90190,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_cr_out; reg [2:0] dec31_dec_sub0_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -90200,7 +90200,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_in1; reg [2:0] dec31_dec_sub0_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -90210,7 +90210,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_in2; reg [2:0] dec31_dec_sub0_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -90220,7 +90220,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_in3; reg [2:0] dec31_dec_sub0_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -90230,7 +90230,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_out; reg [2:0] dec31_dec_sub0_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -90240,7 +90240,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_out2; reg [2:0] dec31_dec_sub0_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -90248,28 +90248,28 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_upd; reg [1:0] dec31_dec_sub0_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub0_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_function_unit = 14'h0040; endcase @@ -90277,18 +90277,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_cr_in = 3'h3; endcase @@ -90296,18 +90296,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_cr_out = 3'h0; endcase @@ -90315,18 +90315,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_sv_in1 = 3'h0; endcase @@ -90334,18 +90334,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_sv_in2 = 3'h0; endcase @@ -90353,18 +90353,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_sv_in3 = 3'h0; endcase @@ -90372,18 +90372,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_sv_out = 3'h1; endcase @@ -90391,18 +90391,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_sv_out2 = 3'h0; endcase @@ -90410,18 +90410,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_sv_cr_in = 3'h2; endcase @@ -90429,18 +90429,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_sv_cr_out = 3'h0; endcase @@ -90448,18 +90448,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_ldst_len = 4'h0; endcase @@ -90467,18 +90467,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_internal_op = 7'h0c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_internal_op = 7'h3b; endcase @@ -90486,18 +90486,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_upd = 2'h0; endcase @@ -90505,18 +90505,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_rc_sel = 2'h0; endcase @@ -90524,18 +90524,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_cry_in = 2'h0; endcase @@ -90543,18 +90543,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_asmcode = 8'h1a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_asmcode = 8'h1c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_asmcode = 8'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_asmcode = 8'h9b; endcase @@ -90562,18 +90562,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_inv_a = 1'h0; endcase @@ -90581,18 +90581,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_inv_out = 1'h0; endcase @@ -90600,18 +90600,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_cry_out = 1'h0; endcase @@ -90619,18 +90619,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_br = 1'h0; endcase @@ -90638,18 +90638,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_sgn_ext = 1'h0; endcase @@ -90657,18 +90657,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_rsrv = 1'h0; endcase @@ -90676,18 +90676,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_form = 5'h18; endcase @@ -90695,18 +90695,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_is_32b = 1'h0; endcase @@ -90714,18 +90714,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_sgn = 1'h0; endcase @@ -90733,18 +90733,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_lk = 1'h0; endcase @@ -90752,18 +90752,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_sgl_pipe = 1'h0; endcase @@ -90771,18 +90771,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_SV_Etype = 2'h2; endcase @@ -90790,18 +90790,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_SV_Ptype = 2'h2; endcase @@ -90809,18 +90809,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_in1_sel = 3'h0; endcase @@ -90828,18 +90828,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_in2_sel = 4'h0; endcase @@ -90847,18 +90847,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_in3_sel = 2'h0; endcase @@ -90866,18 +90866,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub0_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub0_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub0_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub0_out_sel = 3'h1; endcase @@ -90893,20 +90893,20 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_SV_Etype; reg [1:0] dec31_dec_sub10_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_SV_Ptype; reg [1:0] dec31_dec_sub10_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub10_asmcode; reg [7:0] dec31_dec_sub10_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_br; reg dec31_dec_sub10_br; (* enum_base_type = "CRInSel" *) @@ -90918,7 +90918,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_cr_in; reg [2:0] dec31_dec_sub10_cr_in; (* enum_base_type = "CROutSel" *) @@ -90928,17 +90928,17 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_cr_out; reg [2:0] dec31_dec_sub10_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_cry_in; reg [1:0] dec31_dec_sub10_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_cry_out; reg dec31_dec_sub10_cry_out; (* enum_base_type = "Form" *) @@ -90972,7 +90972,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub10_form; reg [4:0] dec31_dec_sub10_form; (* enum_base_type = "Function" *) @@ -90990,7 +90990,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub10_function_unit; reg [13:0] dec31_dec_sub10_function_unit; (* enum_base_type = "In1Sel" *) @@ -90999,7 +90999,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_in1_sel; reg [2:0] dec31_dec_sub10_in1_sel; (* enum_base_type = "In2Sel" *) @@ -91017,14 +91017,14 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub10_in2_sel; reg [3:0] dec31_dec_sub10_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_in3_sel; reg [1:0] dec31_dec_sub10_in3_sel; (* enum_base_type = "MicrOp" *) @@ -91102,16 +91102,16 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub10_internal_op; reg [6:0] dec31_dec_sub10_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_inv_a; reg dec31_dec_sub10_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_inv_out; reg dec31_dec_sub10_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_is_32b; reg dec31_dec_sub10_is_32b; (* enum_base_type = "LdstLen" *) @@ -91120,10 +91120,10 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub10_ldst_len; reg [3:0] dec31_dec_sub10_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_lk; reg dec31_dec_sub10_lk; (* enum_base_type = "OutSel" *) @@ -91132,26 +91132,26 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_out_sel; reg [2:0] dec31_dec_sub10_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_rc_sel; reg [1:0] dec31_dec_sub10_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_rsrv; reg dec31_dec_sub10_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_sgl_pipe; reg dec31_dec_sub10_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_sgn; reg dec31_dec_sub10_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_sgn_ext; reg dec31_dec_sub10_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -91161,7 +91161,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_cr_in; reg [2:0] dec31_dec_sub10_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -91171,7 +91171,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_cr_out; reg [2:0] dec31_dec_sub10_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -91181,7 +91181,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_in1; reg [2:0] dec31_dec_sub10_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -91191,7 +91191,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_in2; reg [2:0] dec31_dec_sub10_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -91201,7 +91201,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_in3; reg [2:0] dec31_dec_sub10_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -91211,7 +91211,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_out; reg [2:0] dec31_dec_sub10_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -91221,7 +91221,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_out2; reg [2:0] dec31_dec_sub10_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -91229,46 +91229,46 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_upd; reg [1:0] dec31_dec_sub10_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub10_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_function_unit = 14'h0002; endcase @@ -91276,36 +91276,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_cr_in = 3'h0; endcase @@ -91313,36 +91313,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_cr_out = 3'h1; endcase @@ -91350,36 +91350,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_sv_in1 = 3'h2; endcase @@ -91387,36 +91387,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_sv_in2 = 3'h0; endcase @@ -91424,36 +91424,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_sv_in3 = 3'h0; endcase @@ -91461,36 +91461,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_sv_out = 3'h1; endcase @@ -91498,36 +91498,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_sv_out2 = 3'h0; endcase @@ -91535,36 +91535,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_sv_cr_in = 3'h0; endcase @@ -91572,36 +91572,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_sv_cr_out = 3'h1; endcase @@ -91609,36 +91609,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_ldst_len = 4'h0; endcase @@ -91646,36 +91646,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_internal_op = 7'h02; endcase @@ -91683,36 +91683,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_upd = 2'h0; endcase @@ -91720,36 +91720,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_rc_sel = 2'h2; endcase @@ -91757,36 +91757,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_cry_in = 2'h2; endcase @@ -91794,36 +91794,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_asmcode = 8'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_asmcode = 8'h0c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_asmcode = 8'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_asmcode = 8'h03; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_asmcode = 8'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_asmcode = 8'h05; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_asmcode = 8'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_asmcode = 8'h0b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_asmcode = 8'h0d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_asmcode = 8'h0e; endcase @@ -91831,36 +91831,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_inv_a = 1'h0; endcase @@ -91868,36 +91868,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_inv_out = 1'h0; endcase @@ -91905,36 +91905,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_cry_out = 1'h1; endcase @@ -91942,36 +91942,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_br = 1'h0; endcase @@ -91979,36 +91979,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_sgn_ext = 1'h0; endcase @@ -92016,36 +92016,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_rsrv = 1'h0; endcase @@ -92053,36 +92053,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_form = 5'h11; endcase @@ -92090,36 +92090,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_is_32b = 1'h0; endcase @@ -92127,36 +92127,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_sgn = 1'h0; endcase @@ -92164,36 +92164,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_lk = 1'h0; endcase @@ -92201,36 +92201,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_sgl_pipe = 1'h0; endcase @@ -92238,36 +92238,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_SV_Etype = 2'h2; endcase @@ -92275,36 +92275,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_SV_Ptype = 2'h2; endcase @@ -92312,36 +92312,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_in1_sel = 3'h1; endcase @@ -92349,36 +92349,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_in2_sel = 4'h0; endcase @@ -92386,36 +92386,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_in3_sel = 2'h0; endcase @@ -92423,36 +92423,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub10_out_sel = 3'h1; endcase @@ -92468,20 +92468,20 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_SV_Etype; reg [1:0] dec31_dec_sub11_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_SV_Ptype; reg [1:0] dec31_dec_sub11_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub11_asmcode; reg [7:0] dec31_dec_sub11_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_br; reg dec31_dec_sub11_br; (* enum_base_type = "CRInSel" *) @@ -92493,7 +92493,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_cr_in; reg [2:0] dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) @@ -92503,17 +92503,17 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_cr_out; reg [2:0] dec31_dec_sub11_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_cry_in; reg [1:0] dec31_dec_sub11_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_cry_out; reg dec31_dec_sub11_cry_out; (* enum_base_type = "Form" *) @@ -92547,7 +92547,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub11_form; reg [4:0] dec31_dec_sub11_form; (* enum_base_type = "Function" *) @@ -92565,7 +92565,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub11_function_unit; reg [13:0] dec31_dec_sub11_function_unit; (* enum_base_type = "In1Sel" *) @@ -92574,7 +92574,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_in1_sel; reg [2:0] dec31_dec_sub11_in1_sel; (* enum_base_type = "In2Sel" *) @@ -92592,14 +92592,14 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub11_in2_sel; reg [3:0] dec31_dec_sub11_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_in3_sel; reg [1:0] dec31_dec_sub11_in3_sel; (* enum_base_type = "MicrOp" *) @@ -92677,16 +92677,16 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub11_internal_op; reg [6:0] dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_inv_a; reg dec31_dec_sub11_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_inv_out; reg dec31_dec_sub11_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_is_32b; reg dec31_dec_sub11_is_32b; (* enum_base_type = "LdstLen" *) @@ -92695,10 +92695,10 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub11_ldst_len; reg [3:0] dec31_dec_sub11_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_lk; reg dec31_dec_sub11_lk; (* enum_base_type = "OutSel" *) @@ -92707,26 +92707,26 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_out_sel; reg [2:0] dec31_dec_sub11_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_rc_sel; reg [1:0] dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_rsrv; reg dec31_dec_sub11_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_sgl_pipe; reg dec31_dec_sub11_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_sgn; reg dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_sgn_ext; reg dec31_dec_sub11_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -92736,7 +92736,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_cr_in; reg [2:0] dec31_dec_sub11_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -92746,7 +92746,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_cr_out; reg [2:0] dec31_dec_sub11_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -92756,7 +92756,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_in1; reg [2:0] dec31_dec_sub11_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -92766,7 +92766,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_in2; reg [2:0] dec31_dec_sub11_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -92776,7 +92776,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_in3; reg [2:0] dec31_dec_sub11_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -92786,7 +92786,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_out; reg [2:0] dec31_dec_sub11_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -92796,7 +92796,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_out2; reg [2:0] dec31_dec_sub11_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -92804,64 +92804,64 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_upd; reg [1:0] dec31_dec_sub11_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub11_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_function_unit = 14'h0100; endcase @@ -92869,54 +92869,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_cr_in = 3'h0; endcase @@ -92924,54 +92924,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_cr_out = 3'h1; endcase @@ -92979,54 +92979,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_sv_in1 = 3'h2; endcase @@ -93034,54 +93034,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_sv_in2 = 3'h3; endcase @@ -93089,54 +93089,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_sv_in3 = 3'h0; endcase @@ -93144,54 +93144,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_sv_out = 3'h1; endcase @@ -93199,54 +93199,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_sv_out2 = 3'h0; endcase @@ -93254,54 +93254,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_sv_cr_in = 3'h0; endcase @@ -93309,54 +93309,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_sv_cr_out = 3'h1; endcase @@ -93364,54 +93364,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_ldst_len = 4'h0; endcase @@ -93419,54 +93419,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_internal_op = 7'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_internal_op = 7'h32; endcase @@ -93474,54 +93474,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_upd = 2'h0; endcase @@ -93529,54 +93529,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_rc_sel = 2'h2; endcase @@ -93584,54 +93584,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_cry_in = 2'h0; endcase @@ -93639,54 +93639,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_asmcode = 8'h3e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_asmcode = 8'h3f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_asmcode = 8'h3c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_asmcode = 8'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_asmcode = 8'h41; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_asmcode = 8'h42; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_asmcode = 8'h3b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_asmcode = 8'h40; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_asmcode = 8'h75; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_asmcode = 8'h73; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_asmcode = 8'h7c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_asmcode = 8'h7d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_asmcode = 8'h7c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_asmcode = 8'h7d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_asmcode = 8'h81; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_asmcode = 8'h82; endcase @@ -93694,54 +93694,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_inv_a = 1'h0; endcase @@ -93749,54 +93749,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_inv_out = 1'h0; endcase @@ -93804,54 +93804,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_cry_out = 1'h0; endcase @@ -93859,54 +93859,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_br = 1'h0; endcase @@ -93914,54 +93914,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_sgn_ext = 1'h0; endcase @@ -93969,54 +93969,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_rsrv = 1'h0; endcase @@ -94024,54 +94024,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_form = 5'h11; endcase @@ -94079,54 +94079,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_is_32b = 1'h1; endcase @@ -94134,54 +94134,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_sgn = 1'h1; endcase @@ -94189,54 +94189,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_lk = 1'h0; endcase @@ -94244,54 +94244,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_sgl_pipe = 1'h0; endcase @@ -94299,54 +94299,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_SV_Etype = 2'h2; endcase @@ -94354,54 +94354,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_SV_Ptype = 2'h1; endcase @@ -94409,54 +94409,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_in1_sel = 3'h1; endcase @@ -94464,54 +94464,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_in2_sel = 4'h1; endcase @@ -94519,54 +94519,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_in3_sel = 2'h0; endcase @@ -94574,54 +94574,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub11_out_sel = 3'h1; endcase @@ -94637,20 +94637,20 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_SV_Etype; reg [1:0] dec31_dec_sub15_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_SV_Ptype; reg [1:0] dec31_dec_sub15_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub15_asmcode; reg [7:0] dec31_dec_sub15_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_br; reg dec31_dec_sub15_br; (* enum_base_type = "CRInSel" *) @@ -94662,7 +94662,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_cr_in; reg [2:0] dec31_dec_sub15_cr_in; (* enum_base_type = "CROutSel" *) @@ -94672,17 +94672,17 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_cr_out; reg [2:0] dec31_dec_sub15_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_cry_in; reg [1:0] dec31_dec_sub15_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_cry_out; reg dec31_dec_sub15_cry_out; (* enum_base_type = "Form" *) @@ -94716,7 +94716,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub15_form; reg [4:0] dec31_dec_sub15_form; (* enum_base_type = "Function" *) @@ -94734,7 +94734,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub15_function_unit; reg [13:0] dec31_dec_sub15_function_unit; (* enum_base_type = "In1Sel" *) @@ -94743,7 +94743,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_in1_sel; reg [2:0] dec31_dec_sub15_in1_sel; (* enum_base_type = "In2Sel" *) @@ -94761,14 +94761,14 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub15_in2_sel; reg [3:0] dec31_dec_sub15_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_in3_sel; reg [1:0] dec31_dec_sub15_in3_sel; (* enum_base_type = "MicrOp" *) @@ -94846,16 +94846,16 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub15_internal_op; reg [6:0] dec31_dec_sub15_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_inv_a; reg dec31_dec_sub15_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_inv_out; reg dec31_dec_sub15_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_is_32b; reg dec31_dec_sub15_is_32b; (* enum_base_type = "LdstLen" *) @@ -94864,10 +94864,10 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub15_ldst_len; reg [3:0] dec31_dec_sub15_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_lk; reg dec31_dec_sub15_lk; (* enum_base_type = "OutSel" *) @@ -94876,26 +94876,26 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_out_sel; reg [2:0] dec31_dec_sub15_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_rc_sel; reg [1:0] dec31_dec_sub15_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_rsrv; reg dec31_dec_sub15_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_sgl_pipe; reg dec31_dec_sub15_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_sgn; reg dec31_dec_sub15_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_sgn_ext; reg dec31_dec_sub15_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -94905,7 +94905,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_cr_in; reg [2:0] dec31_dec_sub15_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -94915,7 +94915,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_cr_out; reg [2:0] dec31_dec_sub15_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -94925,7 +94925,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_in1; reg [2:0] dec31_dec_sub15_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -94935,7 +94935,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_in2; reg [2:0] dec31_dec_sub15_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -94945,7 +94945,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_in3; reg [2:0] dec31_dec_sub15_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -94955,7 +94955,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_out; reg [2:0] dec31_dec_sub15_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -94965,7 +94965,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_out2; reg [2:0] dec31_dec_sub15_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -94973,112 +94973,112 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_upd; reg [1:0] dec31_dec_sub15_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_function_unit = 14'h0040; endcase @@ -95086,102 +95086,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_cr_in = 3'h5; endcase @@ -95189,102 +95189,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_cr_out = 3'h0; endcase @@ -95292,102 +95292,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_sv_in1 = 3'h2; endcase @@ -95395,102 +95395,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_sv_in2 = 3'h3; endcase @@ -95498,102 +95498,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_sv_in3 = 3'h0; endcase @@ -95601,102 +95601,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_sv_out = 3'h1; endcase @@ -95704,102 +95704,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_sv_out2 = 3'h0; endcase @@ -95807,102 +95807,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_sv_cr_in = 3'h4; endcase @@ -95910,102 +95910,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_sv_cr_out = 3'h0; endcase @@ -96013,102 +96013,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_ldst_len = 4'h0; endcase @@ -96116,102 +96116,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_internal_op = 7'h23; endcase @@ -96219,102 +96219,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_upd = 2'h0; endcase @@ -96322,102 +96322,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_rc_sel = 2'h0; endcase @@ -96425,102 +96425,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_cry_in = 2'h0; endcase @@ -96528,102 +96528,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_asmcode = 8'h4b; endcase @@ -96631,102 +96631,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_inv_a = 1'h0; endcase @@ -96734,102 +96734,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_inv_out = 1'h0; endcase @@ -96837,102 +96837,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_cry_out = 1'h0; endcase @@ -96940,102 +96940,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_br = 1'h0; endcase @@ -97043,102 +97043,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_sgn_ext = 1'h0; endcase @@ -97146,102 +97146,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_rsrv = 1'h0; endcase @@ -97249,102 +97249,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_form = 5'h12; endcase @@ -97352,102 +97352,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_is_32b = 1'h0; endcase @@ -97455,102 +97455,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_sgn = 1'h0; endcase @@ -97558,102 +97558,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_lk = 1'h0; endcase @@ -97661,102 +97661,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_sgl_pipe = 1'h1; endcase @@ -97764,102 +97764,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_SV_Etype = 2'h1; endcase @@ -97867,102 +97867,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_SV_Ptype = 2'h1; endcase @@ -97970,102 +97970,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_in1_sel = 3'h2; endcase @@ -98073,102 +98073,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_in2_sel = 4'h1; endcase @@ -98176,102 +98176,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_in3_sel = 2'h0; endcase @@ -98279,102 +98279,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub15_out_sel = 3'h1; endcase @@ -98390,20 +98390,20 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_SV_Etype; reg [1:0] dec31_dec_sub16_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_SV_Ptype; reg [1:0] dec31_dec_sub16_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub16_asmcode; reg [7:0] dec31_dec_sub16_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_br; reg dec31_dec_sub16_br; (* enum_base_type = "CRInSel" *) @@ -98415,7 +98415,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_cr_in; reg [2:0] dec31_dec_sub16_cr_in; (* enum_base_type = "CROutSel" *) @@ -98425,17 +98425,17 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_cr_out; reg [2:0] dec31_dec_sub16_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_cry_in; reg [1:0] dec31_dec_sub16_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_cry_out; reg dec31_dec_sub16_cry_out; (* enum_base_type = "Form" *) @@ -98469,7 +98469,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub16_form; reg [4:0] dec31_dec_sub16_form; (* enum_base_type = "Function" *) @@ -98487,7 +98487,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub16_function_unit; reg [13:0] dec31_dec_sub16_function_unit; (* enum_base_type = "In1Sel" *) @@ -98496,7 +98496,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_in1_sel; reg [2:0] dec31_dec_sub16_in1_sel; (* enum_base_type = "In2Sel" *) @@ -98514,14 +98514,14 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub16_in2_sel; reg [3:0] dec31_dec_sub16_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_in3_sel; reg [1:0] dec31_dec_sub16_in3_sel; (* enum_base_type = "MicrOp" *) @@ -98599,16 +98599,16 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub16_internal_op; reg [6:0] dec31_dec_sub16_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_inv_a; reg dec31_dec_sub16_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_inv_out; reg dec31_dec_sub16_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_is_32b; reg dec31_dec_sub16_is_32b; (* enum_base_type = "LdstLen" *) @@ -98617,10 +98617,10 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub16_ldst_len; reg [3:0] dec31_dec_sub16_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_lk; reg dec31_dec_sub16_lk; (* enum_base_type = "OutSel" *) @@ -98629,26 +98629,26 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_out_sel; reg [2:0] dec31_dec_sub16_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_rc_sel; reg [1:0] dec31_dec_sub16_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_rsrv; reg dec31_dec_sub16_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_sgl_pipe; reg dec31_dec_sub16_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_sgn; reg dec31_dec_sub16_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_sgn_ext; reg dec31_dec_sub16_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -98658,7 +98658,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_cr_in; reg [2:0] dec31_dec_sub16_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -98668,7 +98668,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_cr_out; reg [2:0] dec31_dec_sub16_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -98678,7 +98678,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_in1; reg [2:0] dec31_dec_sub16_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -98688,7 +98688,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_in2; reg [2:0] dec31_dec_sub16_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -98698,7 +98698,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_in3; reg [2:0] dec31_dec_sub16_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -98708,7 +98708,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_out; reg [2:0] dec31_dec_sub16_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -98718,7 +98718,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_out2; reg [2:0] dec31_dec_sub16_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -98726,19 +98726,19 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_upd; reg [1:0] dec31_dec_sub16_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub16_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_function_unit = 14'h0040; endcase @@ -98746,9 +98746,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_cr_in = 3'h6; endcase @@ -98756,9 +98756,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_cr_out = 3'h4; endcase @@ -98766,9 +98766,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_sv_in1 = 3'h2; endcase @@ -98776,9 +98776,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_sv_in2 = 3'h0; endcase @@ -98786,9 +98786,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_sv_in3 = 3'h0; endcase @@ -98796,9 +98796,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_sv_out = 3'h0; endcase @@ -98806,9 +98806,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_sv_out2 = 3'h0; endcase @@ -98816,9 +98816,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_sv_cr_in = 3'h0; endcase @@ -98826,9 +98826,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_sv_cr_out = 3'h0; endcase @@ -98836,9 +98836,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_ldst_len = 4'h0; endcase @@ -98846,9 +98846,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_internal_op = 7'h30; endcase @@ -98856,9 +98856,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_upd = 2'h0; endcase @@ -98866,9 +98866,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_rc_sel = 2'h0; endcase @@ -98876,9 +98876,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_cry_in = 2'h0; endcase @@ -98886,9 +98886,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_asmcode = 8'h76; endcase @@ -98896,9 +98896,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_inv_a = 1'h0; endcase @@ -98906,9 +98906,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_inv_out = 1'h0; endcase @@ -98916,9 +98916,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_cry_out = 1'h0; endcase @@ -98926,9 +98926,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_br = 1'h0; endcase @@ -98936,9 +98936,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_sgn_ext = 1'h0; endcase @@ -98946,9 +98946,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_rsrv = 1'h0; endcase @@ -98956,9 +98956,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_form = 5'h0a; endcase @@ -98966,9 +98966,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_is_32b = 1'h0; endcase @@ -98976,9 +98976,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_sgn = 1'h0; endcase @@ -98986,9 +98986,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_lk = 1'h0; endcase @@ -98996,9 +98996,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_sgl_pipe = 1'h0; endcase @@ -99006,9 +99006,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_SV_Etype = 2'h1; endcase @@ -99016,9 +99016,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_SV_Ptype = 2'h2; endcase @@ -99026,9 +99026,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_in1_sel = 3'h4; endcase @@ -99036,9 +99036,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_in2_sel = 4'h0; endcase @@ -99046,9 +99046,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_in3_sel = 2'h0; endcase @@ -99056,9 +99056,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub16_out_sel = 3'h0; endcase @@ -99074,20 +99074,20 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_SV_Etype; reg [1:0] dec31_dec_sub18_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_SV_Ptype; reg [1:0] dec31_dec_sub18_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub18_asmcode; reg [7:0] dec31_dec_sub18_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_br; reg dec31_dec_sub18_br; (* enum_base_type = "CRInSel" *) @@ -99099,7 +99099,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_cr_in; reg [2:0] dec31_dec_sub18_cr_in; (* enum_base_type = "CROutSel" *) @@ -99109,17 +99109,17 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_cr_out; reg [2:0] dec31_dec_sub18_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_cry_in; reg [1:0] dec31_dec_sub18_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_cry_out; reg dec31_dec_sub18_cry_out; (* enum_base_type = "Form" *) @@ -99153,7 +99153,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub18_form; reg [4:0] dec31_dec_sub18_form; (* enum_base_type = "Function" *) @@ -99171,7 +99171,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub18_function_unit; reg [13:0] dec31_dec_sub18_function_unit; (* enum_base_type = "In1Sel" *) @@ -99180,7 +99180,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_in1_sel; reg [2:0] dec31_dec_sub18_in1_sel; (* enum_base_type = "In2Sel" *) @@ -99198,14 +99198,14 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub18_in2_sel; reg [3:0] dec31_dec_sub18_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_in3_sel; reg [1:0] dec31_dec_sub18_in3_sel; (* enum_base_type = "MicrOp" *) @@ -99283,16 +99283,16 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub18_internal_op; reg [6:0] dec31_dec_sub18_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_inv_a; reg dec31_dec_sub18_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_inv_out; reg dec31_dec_sub18_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_is_32b; reg dec31_dec_sub18_is_32b; (* enum_base_type = "LdstLen" *) @@ -99301,10 +99301,10 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub18_ldst_len; reg [3:0] dec31_dec_sub18_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_lk; reg dec31_dec_sub18_lk; (* enum_base_type = "OutSel" *) @@ -99313,26 +99313,26 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_out_sel; reg [2:0] dec31_dec_sub18_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_rc_sel; reg [1:0] dec31_dec_sub18_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_rsrv; reg dec31_dec_sub18_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_sgl_pipe; reg dec31_dec_sub18_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_sgn; reg dec31_dec_sub18_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_sgn_ext; reg dec31_dec_sub18_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -99342,7 +99342,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_cr_in; reg [2:0] dec31_dec_sub18_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -99352,7 +99352,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_cr_out; reg [2:0] dec31_dec_sub18_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -99362,7 +99362,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_in1; reg [2:0] dec31_dec_sub18_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -99372,7 +99372,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_in2; reg [2:0] dec31_dec_sub18_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -99382,7 +99382,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_in3; reg [2:0] dec31_dec_sub18_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -99392,7 +99392,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_out; reg [2:0] dec31_dec_sub18_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -99402,7 +99402,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_out2; reg [2:0] dec31_dec_sub18_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -99410,31 +99410,31 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_upd; reg [1:0] dec31_dec_sub18_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub18_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_function_unit = 14'h0800; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_function_unit = 14'h0800; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_function_unit = 14'h0800; endcase @@ -99442,21 +99442,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_cr_in = 3'h0; endcase @@ -99464,21 +99464,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_cr_out = 3'h0; endcase @@ -99486,21 +99486,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_sv_in1 = 3'h0; endcase @@ -99508,21 +99508,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_sv_in2 = 3'h0; endcase @@ -99530,21 +99530,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_sv_in3 = 3'h0; endcase @@ -99552,21 +99552,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_sv_out = 3'h0; endcase @@ -99574,21 +99574,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_sv_out2 = 3'h0; endcase @@ -99596,21 +99596,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_sv_cr_in = 3'h0; endcase @@ -99618,21 +99618,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_sv_cr_out = 3'h0; endcase @@ -99640,21 +99640,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_ldst_len = 4'h0; endcase @@ -99662,21 +99662,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_internal_op = 7'h48; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_internal_op = 7'h4a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_internal_op = 7'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_internal_op = 7'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_internal_op = 7'h4b; endcase @@ -99684,21 +99684,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_upd = 2'h0; endcase @@ -99706,21 +99706,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_rc_sel = 2'h0; endcase @@ -99728,21 +99728,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_cry_in = 2'h0; endcase @@ -99750,21 +99750,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_asmcode = 8'h78; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_asmcode = 8'h77; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_asmcode = 8'h9e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_asmcode = 8'hcd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_asmcode = 8'hce; endcase @@ -99772,21 +99772,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_inv_a = 1'h0; endcase @@ -99794,21 +99794,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_inv_out = 1'h0; endcase @@ -99816,21 +99816,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_cry_out = 1'h0; endcase @@ -99838,21 +99838,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_br = 1'h0; endcase @@ -99860,21 +99860,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_sgn_ext = 1'h0; endcase @@ -99882,21 +99882,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_rsrv = 1'h0; endcase @@ -99904,21 +99904,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_form = 5'h08; endcase @@ -99926,21 +99926,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_is_32b = 1'h0; endcase @@ -99948,21 +99948,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_sgn = 1'h0; endcase @@ -99970,21 +99970,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_lk = 1'h0; endcase @@ -99992,21 +99992,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_sgl_pipe = 1'h0; endcase @@ -100014,21 +100014,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_SV_Etype = 2'h0; endcase @@ -100036,21 +100036,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_SV_Ptype = 2'h0; endcase @@ -100058,21 +100058,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_in1_sel = 3'h0; endcase @@ -100080,21 +100080,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_in2_sel = 4'h1; endcase @@ -100102,21 +100102,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_in3_sel = 2'h0; endcase @@ -100124,21 +100124,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub18_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub18_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub18_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub18_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub18_out_sel = 3'h0; endcase @@ -100154,20 +100154,20 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_SV_Etype; reg [1:0] dec31_dec_sub19_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_SV_Ptype; reg [1:0] dec31_dec_sub19_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub19_asmcode; reg [7:0] dec31_dec_sub19_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_br; reg dec31_dec_sub19_br; (* enum_base_type = "CRInSel" *) @@ -100179,7 +100179,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_cr_in; reg [2:0] dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) @@ -100189,17 +100189,17 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_cr_out; reg [2:0] dec31_dec_sub19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_cry_in; reg [1:0] dec31_dec_sub19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_cry_out; reg dec31_dec_sub19_cry_out; (* enum_base_type = "Form" *) @@ -100233,7 +100233,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub19_form; reg [4:0] dec31_dec_sub19_form; (* enum_base_type = "Function" *) @@ -100251,7 +100251,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub19_function_unit; reg [13:0] dec31_dec_sub19_function_unit; (* enum_base_type = "In1Sel" *) @@ -100260,7 +100260,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_in1_sel; reg [2:0] dec31_dec_sub19_in1_sel; (* enum_base_type = "In2Sel" *) @@ -100278,14 +100278,14 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub19_in2_sel; reg [3:0] dec31_dec_sub19_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_in3_sel; reg [1:0] dec31_dec_sub19_in3_sel; (* enum_base_type = "MicrOp" *) @@ -100363,16 +100363,16 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub19_internal_op; reg [6:0] dec31_dec_sub19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_inv_a; reg dec31_dec_sub19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_inv_out; reg dec31_dec_sub19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_is_32b; reg dec31_dec_sub19_is_32b; (* enum_base_type = "LdstLen" *) @@ -100381,10 +100381,10 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub19_ldst_len; reg [3:0] dec31_dec_sub19_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_lk; reg dec31_dec_sub19_lk; (* enum_base_type = "OutSel" *) @@ -100393,26 +100393,26 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_out_sel; reg [2:0] dec31_dec_sub19_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_rc_sel; reg [1:0] dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_rsrv; reg dec31_dec_sub19_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_sgl_pipe; reg dec31_dec_sub19_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_sgn; reg dec31_dec_sub19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_sgn_ext; reg dec31_dec_sub19_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -100422,7 +100422,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_cr_in; reg [2:0] dec31_dec_sub19_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -100432,7 +100432,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_cr_out; reg [2:0] dec31_dec_sub19_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -100442,7 +100442,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_in1; reg [2:0] dec31_dec_sub19_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -100452,7 +100452,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_in2; reg [2:0] dec31_dec_sub19_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -100462,7 +100462,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_in3; reg [2:0] dec31_dec_sub19_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -100472,7 +100472,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_out; reg [2:0] dec31_dec_sub19_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -100482,7 +100482,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_out2; reg [2:0] dec31_dec_sub19_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -100490,28 +100490,28 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_upd; reg [1:0] dec31_dec_sub19_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_function_unit = 14'h0400; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_function_unit = 14'h0400; endcase @@ -100519,18 +100519,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_cr_in = 3'h6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_cr_in = 3'h0; endcase @@ -100538,18 +100538,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_cr_out = 3'h0; endcase @@ -100557,18 +100557,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_sv_in1 = 3'h2; endcase @@ -100576,18 +100576,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_sv_in2 = 3'h0; endcase @@ -100595,18 +100595,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_sv_in3 = 3'h0; endcase @@ -100614,18 +100614,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_sv_out = 3'h1; endcase @@ -100633,18 +100633,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_sv_out2 = 3'h0; endcase @@ -100652,18 +100652,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_sv_cr_in = 3'h0; endcase @@ -100671,18 +100671,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_sv_cr_out = 3'h0; endcase @@ -100690,18 +100690,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_ldst_len = 4'h0; endcase @@ -100709,18 +100709,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_internal_op = 7'h2d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_internal_op = 7'h47; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_internal_op = 7'h2e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_internal_op = 7'h31; endcase @@ -100728,18 +100728,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_upd = 2'h0; endcase @@ -100747,18 +100747,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_rc_sel = 2'h0; endcase @@ -100766,18 +100766,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_cry_in = 2'h0; endcase @@ -100785,18 +100785,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_asmcode = 8'h6f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_asmcode = 8'h70; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_asmcode = 8'h71; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_asmcode = 8'h79; endcase @@ -100804,18 +100804,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_inv_a = 1'h0; endcase @@ -100823,18 +100823,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_inv_out = 1'h0; endcase @@ -100842,18 +100842,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_cry_out = 1'h0; endcase @@ -100861,18 +100861,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_br = 1'h0; endcase @@ -100880,18 +100880,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_sgn_ext = 1'h0; endcase @@ -100899,18 +100899,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_rsrv = 1'h0; endcase @@ -100918,18 +100918,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_form = 5'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_form = 5'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_form = 5'h0a; endcase @@ -100937,18 +100937,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_is_32b = 1'h0; endcase @@ -100956,18 +100956,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_sgn = 1'h0; endcase @@ -100975,18 +100975,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_lk = 1'h0; endcase @@ -100994,18 +100994,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_sgl_pipe = 1'h0; endcase @@ -101013,18 +101013,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_SV_Etype = 2'h2; endcase @@ -101032,18 +101032,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_SV_Ptype = 2'h2; endcase @@ -101051,18 +101051,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_in1_sel = 3'h4; endcase @@ -101070,18 +101070,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_in2_sel = 4'h0; endcase @@ -101089,18 +101089,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_in3_sel = 2'h0; endcase @@ -101108,18 +101108,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub19_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub19_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub19_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub19_out_sel = 3'h3; endcase @@ -101135,20 +101135,20 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_SV_Etype; reg [1:0] dec31_dec_sub20_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_SV_Ptype; reg [1:0] dec31_dec_sub20_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub20_asmcode; reg [7:0] dec31_dec_sub20_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_br; reg dec31_dec_sub20_br; (* enum_base_type = "CRInSel" *) @@ -101160,7 +101160,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_cr_in; reg [2:0] dec31_dec_sub20_cr_in; (* enum_base_type = "CROutSel" *) @@ -101170,17 +101170,17 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_cr_out; reg [2:0] dec31_dec_sub20_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_cry_in; reg [1:0] dec31_dec_sub20_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_cry_out; reg dec31_dec_sub20_cry_out; (* enum_base_type = "Form" *) @@ -101214,7 +101214,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub20_form; reg [4:0] dec31_dec_sub20_form; (* enum_base_type = "Function" *) @@ -101232,7 +101232,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub20_function_unit; reg [13:0] dec31_dec_sub20_function_unit; (* enum_base_type = "In1Sel" *) @@ -101241,7 +101241,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_in1_sel; reg [2:0] dec31_dec_sub20_in1_sel; (* enum_base_type = "In2Sel" *) @@ -101259,14 +101259,14 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub20_in2_sel; reg [3:0] dec31_dec_sub20_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_in3_sel; reg [1:0] dec31_dec_sub20_in3_sel; (* enum_base_type = "MicrOp" *) @@ -101344,16 +101344,16 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub20_internal_op; reg [6:0] dec31_dec_sub20_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_inv_a; reg dec31_dec_sub20_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_inv_out; reg dec31_dec_sub20_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_is_32b; reg dec31_dec_sub20_is_32b; (* enum_base_type = "LdstLen" *) @@ -101362,10 +101362,10 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub20_ldst_len; reg [3:0] dec31_dec_sub20_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_lk; reg dec31_dec_sub20_lk; (* enum_base_type = "OutSel" *) @@ -101374,26 +101374,26 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_out_sel; reg [2:0] dec31_dec_sub20_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_rc_sel; reg [1:0] dec31_dec_sub20_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_rsrv; reg dec31_dec_sub20_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_sgl_pipe; reg dec31_dec_sub20_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_sgn; reg dec31_dec_sub20_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_sgn_ext; reg dec31_dec_sub20_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -101403,7 +101403,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_cr_in; reg [2:0] dec31_dec_sub20_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -101413,7 +101413,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_cr_out; reg [2:0] dec31_dec_sub20_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -101423,7 +101423,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_in1; reg [2:0] dec31_dec_sub20_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -101433,7 +101433,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_in2; reg [2:0] dec31_dec_sub20_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -101443,7 +101443,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_in3; reg [2:0] dec31_dec_sub20_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -101453,7 +101453,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_out; reg [2:0] dec31_dec_sub20_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -101463,7 +101463,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_out2; reg [2:0] dec31_dec_sub20_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -101471,34 +101471,34 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_upd; reg [1:0] dec31_dec_sub20_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub20_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_function_unit = 14'h0004; endcase @@ -101506,24 +101506,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_cr_in = 3'h0; endcase @@ -101531,24 +101531,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_cr_out = 3'h0; endcase @@ -101556,24 +101556,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_sv_in1 = 3'h2; endcase @@ -101581,24 +101581,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_sv_in2 = 3'h3; endcase @@ -101606,24 +101606,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_sv_in3 = 3'h1; endcase @@ -101631,24 +101631,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_sv_out = 3'h0; endcase @@ -101656,24 +101656,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_sv_out2 = 3'h0; endcase @@ -101681,24 +101681,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_sv_cr_in = 3'h0; endcase @@ -101706,24 +101706,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_sv_cr_out = 3'h0; endcase @@ -101731,24 +101731,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_ldst_len = 4'h8; endcase @@ -101756,24 +101756,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_internal_op = 7'h26; endcase @@ -101781,24 +101781,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_upd = 2'h0; endcase @@ -101806,24 +101806,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_rc_sel = 2'h0; endcase @@ -101831,24 +101831,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_cry_in = 2'h0; endcase @@ -101856,24 +101856,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_asmcode = 8'h4d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_asmcode = 8'h53; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_asmcode = 8'h54; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_asmcode = 8'h59; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_asmcode = 8'h63; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_asmcode = 8'hae; endcase @@ -101881,24 +101881,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_inv_a = 1'h0; endcase @@ -101906,24 +101906,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_inv_out = 1'h0; endcase @@ -101931,24 +101931,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_cry_out = 1'h0; endcase @@ -101956,24 +101956,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_br = 1'h1; endcase @@ -101981,24 +101981,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_sgn_ext = 1'h0; endcase @@ -102006,24 +102006,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_rsrv = 1'h0; endcase @@ -102031,24 +102031,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_form = 5'h08; endcase @@ -102056,24 +102056,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_is_32b = 1'h0; endcase @@ -102081,24 +102081,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_sgn = 1'h0; endcase @@ -102106,24 +102106,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_lk = 1'h0; endcase @@ -102131,24 +102131,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_sgl_pipe = 1'h1; endcase @@ -102156,24 +102156,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_SV_Etype = 2'h1; endcase @@ -102181,24 +102181,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_SV_Ptype = 2'h2; endcase @@ -102206,24 +102206,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_in1_sel = 3'h2; endcase @@ -102231,24 +102231,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_in2_sel = 4'h1; endcase @@ -102256,24 +102256,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_in3_sel = 2'h1; endcase @@ -102281,24 +102281,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub20_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub20_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub20_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub20_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub20_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub20_out_sel = 3'h0; endcase @@ -102314,20 +102314,20 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_SV_Etype; reg [1:0] dec31_dec_sub21_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_SV_Ptype; reg [1:0] dec31_dec_sub21_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub21_asmcode; reg [7:0] dec31_dec_sub21_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_br; reg dec31_dec_sub21_br; (* enum_base_type = "CRInSel" *) @@ -102339,7 +102339,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_cr_in; reg [2:0] dec31_dec_sub21_cr_in; (* enum_base_type = "CROutSel" *) @@ -102349,17 +102349,17 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_cr_out; reg [2:0] dec31_dec_sub21_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_cry_in; reg [1:0] dec31_dec_sub21_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_cry_out; reg dec31_dec_sub21_cry_out; (* enum_base_type = "Form" *) @@ -102393,7 +102393,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub21_form; reg [4:0] dec31_dec_sub21_form; (* enum_base_type = "Function" *) @@ -102411,7 +102411,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub21_function_unit; reg [13:0] dec31_dec_sub21_function_unit; (* enum_base_type = "In1Sel" *) @@ -102420,7 +102420,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_in1_sel; reg [2:0] dec31_dec_sub21_in1_sel; (* enum_base_type = "In2Sel" *) @@ -102438,14 +102438,14 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub21_in2_sel; reg [3:0] dec31_dec_sub21_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_in3_sel; reg [1:0] dec31_dec_sub21_in3_sel; (* enum_base_type = "MicrOp" *) @@ -102523,16 +102523,16 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub21_internal_op; reg [6:0] dec31_dec_sub21_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_inv_a; reg dec31_dec_sub21_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_inv_out; reg dec31_dec_sub21_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_is_32b; reg dec31_dec_sub21_is_32b; (* enum_base_type = "LdstLen" *) @@ -102541,10 +102541,10 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub21_ldst_len; reg [3:0] dec31_dec_sub21_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_lk; reg dec31_dec_sub21_lk; (* enum_base_type = "OutSel" *) @@ -102553,26 +102553,26 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_out_sel; reg [2:0] dec31_dec_sub21_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_rc_sel; reg [1:0] dec31_dec_sub21_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_rsrv; reg dec31_dec_sub21_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_sgl_pipe; reg dec31_dec_sub21_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_sgn; reg dec31_dec_sub21_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_sgn_ext; reg dec31_dec_sub21_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -102582,7 +102582,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_cr_in; reg [2:0] dec31_dec_sub21_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -102592,7 +102592,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_cr_out; reg [2:0] dec31_dec_sub21_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -102602,7 +102602,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_in1; reg [2:0] dec31_dec_sub21_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -102612,7 +102612,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_in2; reg [2:0] dec31_dec_sub21_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -102622,7 +102622,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_in3; reg [2:0] dec31_dec_sub21_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -102632,7 +102632,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_out; reg [2:0] dec31_dec_sub21_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -102642,7 +102642,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_out2; reg [2:0] dec31_dec_sub21_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -102650,58 +102650,58 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_upd; reg [1:0] dec31_dec_sub21_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub21_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_function_unit = 14'h0004; endcase @@ -102709,48 +102709,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_cr_in = 3'h0; endcase @@ -102758,48 +102758,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_cr_out = 3'h0; endcase @@ -102807,48 +102807,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_sv_in1 = 3'h2; endcase @@ -102856,48 +102856,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_sv_in2 = 3'h3; endcase @@ -102905,48 +102905,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_sv_in3 = 3'h1; endcase @@ -102954,48 +102954,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_sv_out = 3'h0; endcase @@ -103003,48 +103003,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_sv_out2 = 3'h0; endcase @@ -103052,48 +103052,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_sv_cr_in = 3'h0; endcase @@ -103101,48 +103101,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_sv_cr_out = 3'h0; endcase @@ -103150,48 +103150,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_ldst_len = 4'h4; endcase @@ -103199,48 +103199,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_internal_op = 7'h26; endcase @@ -103248,48 +103248,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_upd = 2'h2; endcase @@ -103297,48 +103297,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_rc_sel = 2'h0; endcase @@ -103346,48 +103346,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_cry_in = 2'h0; endcase @@ -103395,48 +103395,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_inv_a = 1'h0; endcase @@ -103444,48 +103444,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_inv_out = 1'h0; endcase @@ -103493,48 +103493,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_cry_out = 1'h0; endcase @@ -103542,48 +103542,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_br = 1'h0; endcase @@ -103591,48 +103591,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_sgn_ext = 1'h0; endcase @@ -103640,48 +103640,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_rsrv = 1'h0; endcase @@ -103689,48 +103689,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_is_32b = 1'h0; endcase @@ -103738,48 +103738,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_form = 5'h08; endcase @@ -103787,48 +103787,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_sgn = 1'h0; endcase @@ -103836,48 +103836,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_lk = 1'h0; endcase @@ -103885,48 +103885,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_sgl_pipe = 1'h1; endcase @@ -103934,42 +103934,42 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_asmcode = 8'h56; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_asmcode = 8'h57; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_asmcode = 8'h64; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_asmcode = 8'h65; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_asmcode = 8'h68; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_asmcode = 8'ha8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_asmcode = 8'hb1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_asmcode = 8'hb2; endcase @@ -103977,48 +103977,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_SV_Etype = 2'h1; endcase @@ -104026,48 +104026,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_SV_Ptype = 2'h2; endcase @@ -104075,48 +104075,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_in1_sel = 3'h2; endcase @@ -104124,48 +104124,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_in2_sel = 4'h1; endcase @@ -104173,48 +104173,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_in3_sel = 2'h1; endcase @@ -104222,48 +104222,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1a: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub21_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub21_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub21_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub21_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub21_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub21_out_sel = 3'h0; endcase @@ -104279,20 +104279,20 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_SV_Etype; reg [1:0] dec31_dec_sub22_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_SV_Ptype; reg [1:0] dec31_dec_sub22_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub22_asmcode; reg [7:0] dec31_dec_sub22_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_br; reg dec31_dec_sub22_br; (* enum_base_type = "CRInSel" *) @@ -104304,7 +104304,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_cr_in; reg [2:0] dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) @@ -104314,17 +104314,17 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_cr_out; reg [2:0] dec31_dec_sub22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_cry_in; reg [1:0] dec31_dec_sub22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_cry_out; reg dec31_dec_sub22_cry_out; (* enum_base_type = "Form" *) @@ -104358,7 +104358,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub22_form; reg [4:0] dec31_dec_sub22_form; (* enum_base_type = "Function" *) @@ -104376,7 +104376,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub22_function_unit; reg [13:0] dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) @@ -104385,7 +104385,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_in1_sel; reg [2:0] dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) @@ -104403,14 +104403,14 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub22_in2_sel; reg [3:0] dec31_dec_sub22_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_in3_sel; reg [1:0] dec31_dec_sub22_in3_sel; (* enum_base_type = "MicrOp" *) @@ -104488,16 +104488,16 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub22_internal_op; reg [6:0] dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_inv_a; reg dec31_dec_sub22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_inv_out; reg dec31_dec_sub22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_is_32b; reg dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) @@ -104506,10 +104506,10 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub22_ldst_len; reg [3:0] dec31_dec_sub22_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_lk; reg dec31_dec_sub22_lk; (* enum_base_type = "OutSel" *) @@ -104518,26 +104518,26 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_out_sel; reg [2:0] dec31_dec_sub22_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_rc_sel; reg [1:0] dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_rsrv; reg dec31_dec_sub22_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_sgl_pipe; reg dec31_dec_sub22_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_sgn; reg dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_sgn_ext; reg dec31_dec_sub22_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -104547,7 +104547,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_cr_in; reg [2:0] dec31_dec_sub22_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -104557,7 +104557,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_cr_out; reg [2:0] dec31_dec_sub22_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -104567,7 +104567,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_in1; reg [2:0] dec31_dec_sub22_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -104577,7 +104577,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_in2; reg [2:0] dec31_dec_sub22_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -104587,7 +104587,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_in3; reg [2:0] dec31_dec_sub22_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -104597,7 +104597,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_out; reg [2:0] dec31_dec_sub22_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -104607,7 +104607,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_out2; reg [2:0] dec31_dec_sub22_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -104615,64 +104615,64 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_upd; reg [1:0] dec31_dec_sub22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub22_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_function_unit = 14'h0800; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_function_unit = 14'h0002; endcase @@ -104680,54 +104680,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_cr_in = 3'h0; endcase @@ -104735,54 +104735,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_cr_out = 3'h0; endcase @@ -104790,54 +104790,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_sv_in1 = 3'h0; endcase @@ -104845,54 +104845,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_sv_in2 = 3'h0; endcase @@ -104900,54 +104900,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_sv_in3 = 3'h0; endcase @@ -104955,54 +104955,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_sv_out = 3'h0; endcase @@ -105010,54 +105010,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_sv_out2 = 3'h0; endcase @@ -105065,54 +105065,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_sv_cr_in = 3'h0; endcase @@ -105120,54 +105120,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_sv_cr_out = 3'h0; endcase @@ -105175,54 +105175,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_ldst_len = 4'h0; endcase @@ -105230,54 +105230,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_internal_op = 7'h1c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_internal_op = 7'h21; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_internal_op = 7'h01; endcase @@ -105285,54 +105285,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_upd = 2'h0; endcase @@ -105340,54 +105340,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_rc_sel = 2'h0; endcase @@ -105395,54 +105395,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_cry_in = 2'h0; endcase @@ -105450,54 +105450,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_asmcode = 8'h2e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_asmcode = 8'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_asmcode = 8'h30; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_asmcode = 8'h31; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_asmcode = 8'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_asmcode = 8'h49; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_asmcode = 8'h4a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_asmcode = 8'h5d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_asmcode = 8'h66; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_asmcode = 8'ha9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_asmcode = 8'haf; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_asmcode = 8'hb4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_asmcode = 8'hb5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_asmcode = 8'hba; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_asmcode = 8'hbb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_asmcode = 8'hca; endcase @@ -105505,54 +105505,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_inv_a = 1'h0; endcase @@ -105560,54 +105560,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_inv_out = 1'h0; endcase @@ -105615,54 +105615,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_cry_out = 1'h0; endcase @@ -105670,54 +105670,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_br = 1'h0; endcase @@ -105725,54 +105725,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_sgn_ext = 1'h0; endcase @@ -105780,54 +105780,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_rsrv = 1'h0; endcase @@ -105835,54 +105835,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_form = 5'h08; endcase @@ -105890,54 +105890,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_is_32b = 1'h0; endcase @@ -105945,54 +105945,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_sgn = 1'h0; endcase @@ -106000,54 +106000,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_lk = 1'h0; endcase @@ -106055,54 +106055,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_sgl_pipe = 1'h1; endcase @@ -106110,54 +106110,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_SV_Etype = 2'h0; endcase @@ -106165,54 +106165,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_SV_Ptype = 2'h0; endcase @@ -106220,54 +106220,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_in1_sel = 3'h0; endcase @@ -106275,54 +106275,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_in2_sel = 4'h0; endcase @@ -106330,54 +106330,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_in3_sel = 2'h0; endcase @@ -106385,54 +106385,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub22_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub22_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h15: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub22_out_sel = 3'h0; endcase @@ -106448,20 +106448,20 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_SV_Etype; reg [1:0] dec31_dec_sub23_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_SV_Ptype; reg [1:0] dec31_dec_sub23_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub23_asmcode; reg [7:0] dec31_dec_sub23_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_br; reg dec31_dec_sub23_br; (* enum_base_type = "CRInSel" *) @@ -106473,7 +106473,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_cr_in; reg [2:0] dec31_dec_sub23_cr_in; (* enum_base_type = "CROutSel" *) @@ -106483,17 +106483,17 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_cr_out; reg [2:0] dec31_dec_sub23_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_cry_in; reg [1:0] dec31_dec_sub23_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_cry_out; reg dec31_dec_sub23_cry_out; (* enum_base_type = "Form" *) @@ -106527,7 +106527,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub23_form; reg [4:0] dec31_dec_sub23_form; (* enum_base_type = "Function" *) @@ -106545,7 +106545,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub23_function_unit; reg [13:0] dec31_dec_sub23_function_unit; (* enum_base_type = "In1Sel" *) @@ -106554,7 +106554,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_in1_sel; reg [2:0] dec31_dec_sub23_in1_sel; (* enum_base_type = "In2Sel" *) @@ -106572,14 +106572,14 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub23_in2_sel; reg [3:0] dec31_dec_sub23_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_in3_sel; reg [1:0] dec31_dec_sub23_in3_sel; (* enum_base_type = "MicrOp" *) @@ -106657,16 +106657,16 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub23_internal_op; reg [6:0] dec31_dec_sub23_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_inv_a; reg dec31_dec_sub23_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_inv_out; reg dec31_dec_sub23_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_is_32b; reg dec31_dec_sub23_is_32b; (* enum_base_type = "LdstLen" *) @@ -106675,10 +106675,10 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub23_ldst_len; reg [3:0] dec31_dec_sub23_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_lk; reg dec31_dec_sub23_lk; (* enum_base_type = "OutSel" *) @@ -106687,26 +106687,26 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_out_sel; reg [2:0] dec31_dec_sub23_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_rc_sel; reg [1:0] dec31_dec_sub23_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_rsrv; reg dec31_dec_sub23_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_sgl_pipe; reg dec31_dec_sub23_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_sgn; reg dec31_dec_sub23_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_sgn_ext; reg dec31_dec_sub23_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -106716,7 +106716,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_cr_in; reg [2:0] dec31_dec_sub23_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -106726,7 +106726,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_cr_out; reg [2:0] dec31_dec_sub23_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -106736,7 +106736,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_in1; reg [2:0] dec31_dec_sub23_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -106746,7 +106746,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_in2; reg [2:0] dec31_dec_sub23_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -106756,7 +106756,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_in3; reg [2:0] dec31_dec_sub23_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -106766,7 +106766,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_out; reg [2:0] dec31_dec_sub23_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -106776,7 +106776,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_out2; reg [2:0] dec31_dec_sub23_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -106784,58 +106784,58 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_upd; reg [1:0] dec31_dec_sub23_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub23_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_function_unit = 14'h0004; endcase @@ -106843,48 +106843,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_cr_in = 3'h0; endcase @@ -106892,48 +106892,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_cr_out = 3'h0; endcase @@ -106941,48 +106941,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_sv_in1 = 3'h2; endcase @@ -106990,48 +106990,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_sv_in2 = 3'h3; endcase @@ -107039,48 +107039,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_sv_in3 = 3'h1; endcase @@ -107088,48 +107088,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_sv_out = 3'h0; endcase @@ -107137,48 +107137,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_sv_out2 = 3'h0; endcase @@ -107186,48 +107186,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_sv_cr_in = 3'h0; endcase @@ -107235,48 +107235,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_sv_cr_out = 3'h0; endcase @@ -107284,48 +107284,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_ldst_len = 4'h4; endcase @@ -107333,48 +107333,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_internal_op = 7'h26; endcase @@ -107382,48 +107382,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_upd = 2'h0; endcase @@ -107431,48 +107431,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_rc_sel = 2'h0; endcase @@ -107480,48 +107480,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_cry_in = 2'h0; endcase @@ -107529,48 +107529,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_asmcode = 8'h50; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_asmcode = 8'h51; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_asmcode = 8'h5b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_asmcode = 8'h5c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_asmcode = 8'h60; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_asmcode = 8'h61; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_asmcode = 8'h6a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_asmcode = 8'h6b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_asmcode = 8'hab; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_asmcode = 8'hac; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_asmcode = 8'hb7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_asmcode = 8'hb8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_asmcode = 8'hbd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_asmcode = 8'hbe; endcase @@ -107578,48 +107578,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_inv_a = 1'h0; endcase @@ -107627,48 +107627,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_inv_out = 1'h0; endcase @@ -107676,48 +107676,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_cry_out = 1'h0; endcase @@ -107725,48 +107725,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_br = 1'h0; endcase @@ -107774,48 +107774,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_sgn_ext = 1'h0; endcase @@ -107823,48 +107823,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_rsrv = 1'h0; endcase @@ -107872,48 +107872,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_form = 5'h08; endcase @@ -107921,48 +107921,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_is_32b = 1'h0; endcase @@ -107970,48 +107970,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_sgn = 1'h0; endcase @@ -108019,48 +108019,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_lk = 1'h0; endcase @@ -108068,48 +108068,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_sgl_pipe = 1'h1; endcase @@ -108117,48 +108117,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_SV_Etype = 2'h1; endcase @@ -108166,48 +108166,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_SV_Ptype = 2'h2; endcase @@ -108215,48 +108215,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_in1_sel = 3'h2; endcase @@ -108264,48 +108264,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_in2_sel = 4'h1; endcase @@ -108313,48 +108313,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_in3_sel = 2'h1; endcase @@ -108362,48 +108362,48 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0a: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub23_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub23_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub23_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub23_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub23_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub23_out_sel = 3'h0; endcase @@ -108419,20 +108419,20 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_SV_Etype; reg [1:0] dec31_dec_sub24_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_SV_Ptype; reg [1:0] dec31_dec_sub24_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub24_asmcode; reg [7:0] dec31_dec_sub24_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_br; reg dec31_dec_sub24_br; (* enum_base_type = "CRInSel" *) @@ -108444,7 +108444,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_cr_in; reg [2:0] dec31_dec_sub24_cr_in; (* enum_base_type = "CROutSel" *) @@ -108454,17 +108454,17 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_cr_out; reg [2:0] dec31_dec_sub24_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_cry_in; reg [1:0] dec31_dec_sub24_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_cry_out; reg dec31_dec_sub24_cry_out; (* enum_base_type = "Form" *) @@ -108498,7 +108498,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub24_form; reg [4:0] dec31_dec_sub24_form; (* enum_base_type = "Function" *) @@ -108516,7 +108516,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub24_function_unit; reg [13:0] dec31_dec_sub24_function_unit; (* enum_base_type = "In1Sel" *) @@ -108525,7 +108525,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_in1_sel; reg [2:0] dec31_dec_sub24_in1_sel; (* enum_base_type = "In2Sel" *) @@ -108543,14 +108543,14 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub24_in2_sel; reg [3:0] dec31_dec_sub24_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_in3_sel; reg [1:0] dec31_dec_sub24_in3_sel; (* enum_base_type = "MicrOp" *) @@ -108628,16 +108628,16 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub24_internal_op; reg [6:0] dec31_dec_sub24_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_inv_a; reg dec31_dec_sub24_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_inv_out; reg dec31_dec_sub24_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_is_32b; reg dec31_dec_sub24_is_32b; (* enum_base_type = "LdstLen" *) @@ -108646,10 +108646,10 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub24_ldst_len; reg [3:0] dec31_dec_sub24_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_lk; reg dec31_dec_sub24_lk; (* enum_base_type = "OutSel" *) @@ -108658,26 +108658,26 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_out_sel; reg [2:0] dec31_dec_sub24_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_rc_sel; reg [1:0] dec31_dec_sub24_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_rsrv; reg dec31_dec_sub24_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_sgl_pipe; reg dec31_dec_sub24_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_sgn; reg dec31_dec_sub24_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_sgn_ext; reg dec31_dec_sub24_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -108687,7 +108687,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_cr_in; reg [2:0] dec31_dec_sub24_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -108697,7 +108697,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_cr_out; reg [2:0] dec31_dec_sub24_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -108707,7 +108707,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_in1; reg [2:0] dec31_dec_sub24_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -108717,7 +108717,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_in2; reg [2:0] dec31_dec_sub24_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -108727,7 +108727,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_in3; reg [2:0] dec31_dec_sub24_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -108737,7 +108737,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_out; reg [2:0] dec31_dec_sub24_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -108747,7 +108747,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_out2; reg [2:0] dec31_dec_sub24_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -108755,28 +108755,28 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_upd; reg [1:0] dec31_dec_sub24_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub24_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_function_unit = 14'h0008; endcase @@ -108784,18 +108784,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_cr_in = 3'h0; endcase @@ -108803,18 +108803,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_cr_out = 3'h1; endcase @@ -108822,18 +108822,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_sv_in1 = 3'h0; endcase @@ -108841,18 +108841,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_sv_in2 = 3'h2; endcase @@ -108860,18 +108860,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_sv_in3 = 3'h3; endcase @@ -108879,18 +108879,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_sv_out = 3'h1; endcase @@ -108898,18 +108898,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_sv_out2 = 3'h0; endcase @@ -108917,18 +108917,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_sv_cr_in = 3'h0; endcase @@ -108936,18 +108936,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_sv_cr_out = 3'h1; endcase @@ -108955,18 +108955,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_ldst_len = 4'h0; endcase @@ -108974,18 +108974,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_internal_op = 7'h3c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_internal_op = 7'h3d; endcase @@ -108993,18 +108993,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_upd = 2'h0; endcase @@ -109012,18 +109012,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_rc_sel = 2'h2; endcase @@ -109031,18 +109031,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_cry_in = 2'h0; endcase @@ -109050,18 +109050,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_asmcode = 8'ha0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_asmcode = 8'ha3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_asmcode = 8'ha4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_asmcode = 8'ha6; endcase @@ -109069,18 +109069,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_inv_a = 1'h0; endcase @@ -109088,18 +109088,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_inv_out = 1'h0; endcase @@ -109107,18 +109107,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_cry_out = 1'h0; endcase @@ -109126,18 +109126,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_br = 1'h0; endcase @@ -109145,18 +109145,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_sgn_ext = 1'h0; endcase @@ -109164,18 +109164,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_rsrv = 1'h0; endcase @@ -109183,18 +109183,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_form = 5'h08; endcase @@ -109202,18 +109202,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_is_32b = 1'h1; endcase @@ -109221,18 +109221,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_sgn = 1'h0; endcase @@ -109240,18 +109240,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_lk = 1'h0; endcase @@ -109259,18 +109259,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_sgl_pipe = 1'h0; endcase @@ -109278,18 +109278,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_SV_Etype = 2'h2; endcase @@ -109297,18 +109297,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_SV_Ptype = 2'h1; endcase @@ -109316,18 +109316,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_in1_sel = 3'h0; endcase @@ -109335,18 +109335,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_in2_sel = 4'h1; endcase @@ -109354,18 +109354,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_in3_sel = 2'h1; endcase @@ -109373,18 +109373,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub24_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub24_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub24_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub24_out_sel = 3'h2; endcase @@ -109400,20 +109400,20 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_SV_Etype; reg [1:0] dec31_dec_sub26_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_SV_Ptype; reg [1:0] dec31_dec_sub26_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub26_asmcode; reg [7:0] dec31_dec_sub26_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_br; reg dec31_dec_sub26_br; (* enum_base_type = "CRInSel" *) @@ -109425,7 +109425,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_cr_in; reg [2:0] dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) @@ -109435,17 +109435,17 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_cr_out; reg [2:0] dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_cry_in; reg [1:0] dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_cry_out; reg dec31_dec_sub26_cry_out; (* enum_base_type = "Form" *) @@ -109479,7 +109479,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub26_form; reg [4:0] dec31_dec_sub26_form; (* enum_base_type = "Function" *) @@ -109497,7 +109497,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub26_function_unit; reg [13:0] dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) @@ -109506,7 +109506,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_in1_sel; reg [2:0] dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) @@ -109524,14 +109524,14 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub26_in2_sel; reg [3:0] dec31_dec_sub26_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_in3_sel; reg [1:0] dec31_dec_sub26_in3_sel; (* enum_base_type = "MicrOp" *) @@ -109609,16 +109609,16 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub26_internal_op; reg [6:0] dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_inv_a; reg dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_inv_out; reg dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_is_32b; reg dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) @@ -109627,10 +109627,10 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub26_ldst_len; reg [3:0] dec31_dec_sub26_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_lk; reg dec31_dec_sub26_lk; (* enum_base_type = "OutSel" *) @@ -109639,26 +109639,26 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_out_sel; reg [2:0] dec31_dec_sub26_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_rc_sel; reg [1:0] dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_rsrv; reg dec31_dec_sub26_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_sgl_pipe; reg dec31_dec_sub26_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_sgn; reg dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_sgn_ext; reg dec31_dec_sub26_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -109668,7 +109668,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_cr_in; reg [2:0] dec31_dec_sub26_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -109678,7 +109678,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_cr_out; reg [2:0] dec31_dec_sub26_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -109688,7 +109688,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_in1; reg [2:0] dec31_dec_sub26_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -109698,7 +109698,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_in2; reg [2:0] dec31_dec_sub26_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -109708,7 +109708,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_in3; reg [2:0] dec31_dec_sub26_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -109718,7 +109718,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_out; reg [2:0] dec31_dec_sub26_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -109728,7 +109728,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_out2; reg [2:0] dec31_dec_sub26_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -109736,61 +109736,61 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_upd; reg [1:0] dec31_dec_sub26_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub26_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_function_unit = 14'h0008; endcase @@ -109798,51 +109798,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_cr_in = 3'h0; endcase @@ -109850,51 +109850,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_cr_out = 3'h1; endcase @@ -109902,51 +109902,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_sv_in1 = 3'h0; endcase @@ -109954,51 +109954,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_sv_in2 = 3'h0; endcase @@ -110006,51 +110006,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_sv_in3 = 3'h2; endcase @@ -110058,51 +110058,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_sv_out = 3'h1; endcase @@ -110110,51 +110110,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_sv_out2 = 3'h0; endcase @@ -110162,51 +110162,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_sv_cr_in = 3'h0; endcase @@ -110214,51 +110214,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_sv_cr_out = 3'h1; endcase @@ -110266,51 +110266,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_ldst_len = 4'h0; endcase @@ -110318,51 +110318,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_internal_op = 7'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_internal_op = 7'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_internal_op = 7'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_internal_op = 7'h20; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_internal_op = 7'h37; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_internal_op = 7'h37; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_internal_op = 7'h3d; endcase @@ -110370,51 +110370,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_upd = 2'h0; endcase @@ -110422,51 +110422,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_rc_sel = 2'h2; endcase @@ -110474,51 +110474,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_cry_in = 2'h0; endcase @@ -110526,51 +110526,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_asmcode = 8'h21; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_asmcode = 8'h22; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_asmcode = 8'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_asmcode = 8'h24; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_asmcode = 8'h44; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_asmcode = 8'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_asmcode = 8'h46; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_asmcode = 8'h47; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_asmcode = 8'h8c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_asmcode = 8'h8d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_asmcode = 8'h8e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_asmcode = 8'h8f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_asmcode = 8'h90; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_asmcode = 8'ha1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_asmcode = 8'ha2; endcase @@ -110578,51 +110578,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_inv_a = 1'h0; endcase @@ -110630,51 +110630,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_inv_out = 1'h0; endcase @@ -110682,51 +110682,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_cry_out = 1'h1; endcase @@ -110734,51 +110734,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_br = 1'h0; endcase @@ -110786,51 +110786,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_sgn_ext = 1'h0; endcase @@ -110838,51 +110838,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_rsrv = 1'h0; endcase @@ -110890,51 +110890,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_form = 5'h10; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_form = 5'h10; endcase @@ -110942,51 +110942,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_is_32b = 1'h0; endcase @@ -110994,51 +110994,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_sgn = 1'h1; endcase @@ -111046,51 +111046,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_lk = 1'h0; endcase @@ -111098,51 +111098,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_sgl_pipe = 1'h0; endcase @@ -111150,51 +111150,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_SV_Etype = 2'h2; endcase @@ -111202,51 +111202,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_SV_Ptype = 2'h2; endcase @@ -111254,51 +111254,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_in1_sel = 3'h0; endcase @@ -111306,51 +111306,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_in2_sel = 4'ha; endcase @@ -111358,51 +111358,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_in3_sel = 2'h1; endcase @@ -111410,51 +111410,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0b: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h05: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub26_out_sel = 3'h2; endcase @@ -111470,20 +111470,20 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_SV_Etype; reg [1:0] dec31_dec_sub27_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_SV_Ptype; reg [1:0] dec31_dec_sub27_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub27_asmcode; reg [7:0] dec31_dec_sub27_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_br; reg dec31_dec_sub27_br; (* enum_base_type = "CRInSel" *) @@ -111495,7 +111495,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_cr_in; reg [2:0] dec31_dec_sub27_cr_in; (* enum_base_type = "CROutSel" *) @@ -111505,17 +111505,17 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_cr_out; reg [2:0] dec31_dec_sub27_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_cry_in; reg [1:0] dec31_dec_sub27_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_cry_out; reg dec31_dec_sub27_cry_out; (* enum_base_type = "Form" *) @@ -111549,7 +111549,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub27_form; reg [4:0] dec31_dec_sub27_form; (* enum_base_type = "Function" *) @@ -111567,7 +111567,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub27_function_unit; reg [13:0] dec31_dec_sub27_function_unit; (* enum_base_type = "In1Sel" *) @@ -111576,7 +111576,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_in1_sel; reg [2:0] dec31_dec_sub27_in1_sel; (* enum_base_type = "In2Sel" *) @@ -111594,14 +111594,14 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub27_in2_sel; reg [3:0] dec31_dec_sub27_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_in3_sel; reg [1:0] dec31_dec_sub27_in3_sel; (* enum_base_type = "MicrOp" *) @@ -111679,16 +111679,16 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub27_internal_op; reg [6:0] dec31_dec_sub27_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_inv_a; reg dec31_dec_sub27_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_inv_out; reg dec31_dec_sub27_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_is_32b; reg dec31_dec_sub27_is_32b; (* enum_base_type = "LdstLen" *) @@ -111697,10 +111697,10 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub27_ldst_len; reg [3:0] dec31_dec_sub27_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_lk; reg dec31_dec_sub27_lk; (* enum_base_type = "OutSel" *) @@ -111709,26 +111709,26 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_out_sel; reg [2:0] dec31_dec_sub27_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_rc_sel; reg [1:0] dec31_dec_sub27_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_rsrv; reg dec31_dec_sub27_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_sgl_pipe; reg dec31_dec_sub27_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_sgn; reg dec31_dec_sub27_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_sgn_ext; reg dec31_dec_sub27_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -111738,7 +111738,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_cr_in; reg [2:0] dec31_dec_sub27_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -111748,7 +111748,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_cr_out; reg [2:0] dec31_dec_sub27_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -111758,7 +111758,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_in1; reg [2:0] dec31_dec_sub27_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -111768,7 +111768,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_in2; reg [2:0] dec31_dec_sub27_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -111778,7 +111778,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_in3; reg [2:0] dec31_dec_sub27_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -111788,7 +111788,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_out; reg [2:0] dec31_dec_sub27_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -111798,7 +111798,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_out2; reg [2:0] dec31_dec_sub27_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -111806,28 +111806,28 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_upd; reg [1:0] dec31_dec_sub27_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub27_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_function_unit = 14'h0008; endcase @@ -111835,18 +111835,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_cr_in = 3'h0; endcase @@ -111854,18 +111854,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_cr_out = 3'h1; endcase @@ -111873,18 +111873,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_sv_in1 = 3'h0; endcase @@ -111892,18 +111892,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_sv_in2 = 3'h2; endcase @@ -111911,18 +111911,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_sv_in3 = 3'h3; endcase @@ -111930,18 +111930,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_sv_out = 3'h1; endcase @@ -111949,18 +111949,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_sv_out2 = 3'h0; endcase @@ -111968,18 +111968,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_sv_cr_in = 3'h0; endcase @@ -111987,18 +111987,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_sv_cr_out = 3'h1; endcase @@ -112006,18 +112006,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_ldst_len = 4'h0; endcase @@ -112025,18 +112025,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_internal_op = 7'h20; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_internal_op = 7'h3c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_internal_op = 7'h3d; endcase @@ -112044,18 +112044,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_upd = 2'h0; endcase @@ -112063,18 +112063,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_rc_sel = 2'h2; endcase @@ -112082,18 +112082,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_cry_in = 2'h0; endcase @@ -112101,18 +112101,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_asmcode = 8'h47; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_asmcode = 8'h9f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_asmcode = 8'ha2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_asmcode = 8'ha5; endcase @@ -112120,18 +112120,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_inv_a = 1'h0; endcase @@ -112139,18 +112139,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_inv_out = 1'h0; endcase @@ -112158,18 +112158,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_cry_out = 1'h0; endcase @@ -112177,18 +112177,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_br = 1'h0; endcase @@ -112196,18 +112196,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_sgn_ext = 1'h0; endcase @@ -112215,18 +112215,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_rsrv = 1'h0; endcase @@ -112234,18 +112234,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_form = 5'h10; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_form = 5'h10; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_form = 5'h08; endcase @@ -112253,18 +112253,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_is_32b = 1'h0; endcase @@ -112272,18 +112272,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_sgn = 1'h0; endcase @@ -112291,18 +112291,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_lk = 1'h0; endcase @@ -112310,18 +112310,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_sgl_pipe = 1'h0; endcase @@ -112329,18 +112329,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_SV_Etype = 2'h2; endcase @@ -112348,18 +112348,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_SV_Ptype = 2'h1; endcase @@ -112367,18 +112367,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_in1_sel = 3'h0; endcase @@ -112386,18 +112386,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_in2_sel = 4'h1; endcase @@ -112405,18 +112405,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_in3_sel = 2'h1; endcase @@ -112424,18 +112424,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1b: dec31_dec_sub27_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub27_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h19: dec31_dec_sub27_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub27_out_sel = 3'h2; endcase @@ -112451,20 +112451,20 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_SV_Etype; reg [1:0] dec31_dec_sub28_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_SV_Ptype; reg [1:0] dec31_dec_sub28_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub28_asmcode; reg [7:0] dec31_dec_sub28_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_br; reg dec31_dec_sub28_br; (* enum_base_type = "CRInSel" *) @@ -112476,7 +112476,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_cr_in; reg [2:0] dec31_dec_sub28_cr_in; (* enum_base_type = "CROutSel" *) @@ -112486,17 +112486,17 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_cr_out; reg [2:0] dec31_dec_sub28_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_cry_in; reg [1:0] dec31_dec_sub28_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_cry_out; reg dec31_dec_sub28_cry_out; (* enum_base_type = "Form" *) @@ -112530,7 +112530,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub28_form; reg [4:0] dec31_dec_sub28_form; (* enum_base_type = "Function" *) @@ -112548,7 +112548,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub28_function_unit; reg [13:0] dec31_dec_sub28_function_unit; (* enum_base_type = "In1Sel" *) @@ -112557,7 +112557,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_in1_sel; reg [2:0] dec31_dec_sub28_in1_sel; (* enum_base_type = "In2Sel" *) @@ -112575,14 +112575,14 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub28_in2_sel; reg [3:0] dec31_dec_sub28_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_in3_sel; reg [1:0] dec31_dec_sub28_in3_sel; (* enum_base_type = "MicrOp" *) @@ -112660,16 +112660,16 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub28_internal_op; reg [6:0] dec31_dec_sub28_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_inv_a; reg dec31_dec_sub28_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_inv_out; reg dec31_dec_sub28_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_is_32b; reg dec31_dec_sub28_is_32b; (* enum_base_type = "LdstLen" *) @@ -112678,10 +112678,10 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub28_ldst_len; reg [3:0] dec31_dec_sub28_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_lk; reg dec31_dec_sub28_lk; (* enum_base_type = "OutSel" *) @@ -112690,26 +112690,26 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_out_sel; reg [2:0] dec31_dec_sub28_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_rc_sel; reg [1:0] dec31_dec_sub28_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_rsrv; reg dec31_dec_sub28_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_sgl_pipe; reg dec31_dec_sub28_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_sgn; reg dec31_dec_sub28_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_sgn_ext; reg dec31_dec_sub28_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -112719,7 +112719,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_cr_in; reg [2:0] dec31_dec_sub28_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -112729,7 +112729,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_cr_out; reg [2:0] dec31_dec_sub28_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -112739,7 +112739,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_in1; reg [2:0] dec31_dec_sub28_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -112749,7 +112749,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_in2; reg [2:0] dec31_dec_sub28_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -112759,7 +112759,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_in3; reg [2:0] dec31_dec_sub28_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -112769,7 +112769,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_out; reg [2:0] dec31_dec_sub28_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -112779,7 +112779,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_out2; reg [2:0] dec31_dec_sub28_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -112787,46 +112787,46 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_upd; reg [1:0] dec31_dec_sub28_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub28_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_function_unit = 14'h0010; endcase @@ -112834,36 +112834,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_cr_in = 3'h0; endcase @@ -112871,36 +112871,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_cr_out = 3'h1; endcase @@ -112908,36 +112908,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_sv_in1 = 3'h3; endcase @@ -112945,36 +112945,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_sv_in2 = 3'h2; endcase @@ -112982,36 +112982,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_sv_in3 = 3'h0; endcase @@ -113019,36 +113019,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_sv_out = 3'h1; endcase @@ -113056,36 +113056,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_sv_out2 = 3'h0; endcase @@ -113093,36 +113093,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_sv_cr_in = 3'h0; endcase @@ -113130,36 +113130,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_sv_cr_out = 3'h1; endcase @@ -113167,36 +113167,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_ldst_len = 4'h0; endcase @@ -113204,36 +113204,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_internal_op = 7'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_internal_op = 7'h0b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_internal_op = 7'h43; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_internal_op = 7'h43; endcase @@ -113241,36 +113241,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_upd = 2'h0; endcase @@ -113278,36 +113278,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_rc_sel = 2'h2; endcase @@ -113315,36 +113315,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_cry_in = 2'h0; endcase @@ -113352,36 +113352,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_asmcode = 8'h0f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_asmcode = 8'h10; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_asmcode = 8'h19; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_asmcode = 8'h1b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_asmcode = 8'h43; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_asmcode = 8'h83; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_asmcode = 8'h87; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_asmcode = 8'h88; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_asmcode = 8'h89; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_asmcode = 8'hd1; endcase @@ -113389,36 +113389,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_inv_a = 1'h0; endcase @@ -113426,36 +113426,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_inv_out = 1'h0; endcase @@ -113463,36 +113463,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_cry_out = 1'h0; endcase @@ -113500,36 +113500,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_br = 1'h0; endcase @@ -113537,36 +113537,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_sgn_ext = 1'h0; endcase @@ -113574,36 +113574,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_rsrv = 1'h0; endcase @@ -113611,36 +113611,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_form = 5'h08; endcase @@ -113648,36 +113648,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_is_32b = 1'h0; endcase @@ -113685,36 +113685,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_sgn = 1'h0; endcase @@ -113722,36 +113722,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_lk = 1'h0; endcase @@ -113759,36 +113759,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_sgl_pipe = 1'h0; endcase @@ -113796,36 +113796,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_SV_Etype = 2'h2; endcase @@ -113833,36 +113833,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_SV_Ptype = 2'h1; endcase @@ -113870,36 +113870,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_in1_sel = 3'h4; endcase @@ -113907,36 +113907,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_in2_sel = 4'h1; endcase @@ -113944,36 +113944,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_in3_sel = 2'h0; endcase @@ -113981,36 +113981,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h09: dec31_dec_sub28_out_sel = 3'h2; endcase @@ -114026,20 +114026,20 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_SV_Etype; reg [1:0] dec31_dec_sub4_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_SV_Ptype; reg [1:0] dec31_dec_sub4_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub4_asmcode; reg [7:0] dec31_dec_sub4_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_br; reg dec31_dec_sub4_br; (* enum_base_type = "CRInSel" *) @@ -114051,7 +114051,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_cr_in; reg [2:0] dec31_dec_sub4_cr_in; (* enum_base_type = "CROutSel" *) @@ -114061,17 +114061,17 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_cr_out; reg [2:0] dec31_dec_sub4_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_cry_in; reg [1:0] dec31_dec_sub4_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_cry_out; reg dec31_dec_sub4_cry_out; (* enum_base_type = "Form" *) @@ -114105,7 +114105,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub4_form; reg [4:0] dec31_dec_sub4_form; (* enum_base_type = "Function" *) @@ -114123,7 +114123,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub4_function_unit; reg [13:0] dec31_dec_sub4_function_unit; (* enum_base_type = "In1Sel" *) @@ -114132,7 +114132,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_in1_sel; reg [2:0] dec31_dec_sub4_in1_sel; (* enum_base_type = "In2Sel" *) @@ -114150,14 +114150,14 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub4_in2_sel; reg [3:0] dec31_dec_sub4_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_in3_sel; reg [1:0] dec31_dec_sub4_in3_sel; (* enum_base_type = "MicrOp" *) @@ -114235,16 +114235,16 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub4_internal_op; reg [6:0] dec31_dec_sub4_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_inv_a; reg dec31_dec_sub4_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_inv_out; reg dec31_dec_sub4_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_is_32b; reg dec31_dec_sub4_is_32b; (* enum_base_type = "LdstLen" *) @@ -114253,10 +114253,10 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub4_ldst_len; reg [3:0] dec31_dec_sub4_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_lk; reg dec31_dec_sub4_lk; (* enum_base_type = "OutSel" *) @@ -114265,26 +114265,26 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_out_sel; reg [2:0] dec31_dec_sub4_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_rc_sel; reg [1:0] dec31_dec_sub4_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_rsrv; reg dec31_dec_sub4_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_sgl_pipe; reg dec31_dec_sub4_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_sgn; reg dec31_dec_sub4_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_sgn_ext; reg dec31_dec_sub4_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -114294,7 +114294,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_cr_in; reg [2:0] dec31_dec_sub4_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -114304,7 +114304,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_cr_out; reg [2:0] dec31_dec_sub4_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -114314,7 +114314,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_in1; reg [2:0] dec31_dec_sub4_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -114324,7 +114324,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_in2; reg [2:0] dec31_dec_sub4_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -114334,7 +114334,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_in3; reg [2:0] dec31_dec_sub4_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -114344,7 +114344,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_out; reg [2:0] dec31_dec_sub4_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -114354,7 +114354,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_out2; reg [2:0] dec31_dec_sub4_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -114362,22 +114362,22 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_upd; reg [1:0] dec31_dec_sub4_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub4_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_function_unit = 14'h0080; endcase @@ -114385,12 +114385,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_cr_in = 3'h0; endcase @@ -114398,12 +114398,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_cr_out = 3'h0; endcase @@ -114411,12 +114411,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_sv_in1 = 3'h0; endcase @@ -114424,12 +114424,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_sv_in2 = 3'h0; endcase @@ -114437,12 +114437,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_sv_in3 = 3'h0; endcase @@ -114450,12 +114450,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_sv_out = 3'h0; endcase @@ -114463,12 +114463,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_sv_out2 = 3'h0; endcase @@ -114476,12 +114476,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_sv_cr_in = 3'h0; endcase @@ -114489,12 +114489,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_sv_cr_out = 3'h0; endcase @@ -114502,12 +114502,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_ldst_len = 4'h0; endcase @@ -114515,12 +114515,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_internal_op = 7'h3f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_internal_op = 7'h3f; endcase @@ -114528,12 +114528,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_upd = 2'h0; endcase @@ -114541,12 +114541,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_rc_sel = 2'h0; endcase @@ -114554,12 +114554,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_cry_in = 2'h0; endcase @@ -114567,12 +114567,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_asmcode = 8'hcb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_asmcode = 8'hcf; endcase @@ -114580,12 +114580,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_inv_a = 1'h0; endcase @@ -114593,12 +114593,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_inv_out = 1'h0; endcase @@ -114606,12 +114606,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_cry_out = 1'h0; endcase @@ -114619,12 +114619,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_br = 1'h0; endcase @@ -114632,12 +114632,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_sgn_ext = 1'h0; endcase @@ -114645,12 +114645,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_rsrv = 1'h0; endcase @@ -114658,12 +114658,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_form = 5'h08; endcase @@ -114671,12 +114671,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_is_32b = 1'h1; endcase @@ -114684,12 +114684,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_sgn = 1'h0; endcase @@ -114697,12 +114697,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_lk = 1'h0; endcase @@ -114710,12 +114710,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_sgl_pipe = 1'h1; endcase @@ -114723,12 +114723,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_SV_Etype = 2'h0; endcase @@ -114736,12 +114736,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_SV_Ptype = 2'h0; endcase @@ -114749,12 +114749,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_in1_sel = 3'h1; endcase @@ -114762,12 +114762,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_in2_sel = 4'h1; endcase @@ -114775,12 +114775,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_in3_sel = 2'h0; endcase @@ -114788,12 +114788,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub4_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub4_out_sel = 3'h0; endcase @@ -114809,20 +114809,20 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_SV_Etype; reg [1:0] dec31_dec_sub8_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_SV_Ptype; reg [1:0] dec31_dec_sub8_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub8_asmcode; reg [7:0] dec31_dec_sub8_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_br; reg dec31_dec_sub8_br; (* enum_base_type = "CRInSel" *) @@ -114834,7 +114834,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_cr_in; reg [2:0] dec31_dec_sub8_cr_in; (* enum_base_type = "CROutSel" *) @@ -114844,17 +114844,17 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_cr_out; reg [2:0] dec31_dec_sub8_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_cry_in; reg [1:0] dec31_dec_sub8_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_cry_out; reg dec31_dec_sub8_cry_out; (* enum_base_type = "Form" *) @@ -114888,7 +114888,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub8_form; reg [4:0] dec31_dec_sub8_form; (* enum_base_type = "Function" *) @@ -114906,7 +114906,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub8_function_unit; reg [13:0] dec31_dec_sub8_function_unit; (* enum_base_type = "In1Sel" *) @@ -114915,7 +114915,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_in1_sel; reg [2:0] dec31_dec_sub8_in1_sel; (* enum_base_type = "In2Sel" *) @@ -114933,14 +114933,14 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub8_in2_sel; reg [3:0] dec31_dec_sub8_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_in3_sel; reg [1:0] dec31_dec_sub8_in3_sel; (* enum_base_type = "MicrOp" *) @@ -115018,16 +115018,16 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub8_internal_op; reg [6:0] dec31_dec_sub8_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_inv_a; reg dec31_dec_sub8_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_inv_out; reg dec31_dec_sub8_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_is_32b; reg dec31_dec_sub8_is_32b; (* enum_base_type = "LdstLen" *) @@ -115036,10 +115036,10 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub8_ldst_len; reg [3:0] dec31_dec_sub8_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_lk; reg dec31_dec_sub8_lk; (* enum_base_type = "OutSel" *) @@ -115048,26 +115048,26 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_out_sel; reg [2:0] dec31_dec_sub8_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_rc_sel; reg [1:0] dec31_dec_sub8_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_rsrv; reg dec31_dec_sub8_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_sgl_pipe; reg dec31_dec_sub8_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_sgn; reg dec31_dec_sub8_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_sgn_ext; reg dec31_dec_sub8_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -115077,7 +115077,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_cr_in; reg [2:0] dec31_dec_sub8_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -115087,7 +115087,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_cr_out; reg [2:0] dec31_dec_sub8_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -115097,7 +115097,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_in1; reg [2:0] dec31_dec_sub8_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -115107,7 +115107,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_in2; reg [2:0] dec31_dec_sub8_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -115117,7 +115117,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_in3; reg [2:0] dec31_dec_sub8_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -115127,7 +115127,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_out; reg [2:0] dec31_dec_sub8_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -115137,7 +115137,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_out2; reg [2:0] dec31_dec_sub8_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -115145,52 +115145,52 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_upd; reg [1:0] dec31_dec_sub8_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub8_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_function_unit = 14'h0002; endcase @@ -115198,42 +115198,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_cr_in = 3'h0; endcase @@ -115241,42 +115241,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_cr_out = 3'h1; endcase @@ -115284,42 +115284,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_sv_in1 = 3'h2; endcase @@ -115327,42 +115327,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_sv_in2 = 3'h0; endcase @@ -115370,42 +115370,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_sv_in3 = 3'h0; endcase @@ -115413,42 +115413,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_sv_out = 3'h1; endcase @@ -115456,42 +115456,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_sv_out2 = 3'h0; endcase @@ -115499,42 +115499,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_sv_cr_in = 3'h0; endcase @@ -115542,42 +115542,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_sv_cr_out = 3'h1; endcase @@ -115585,42 +115585,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_ldst_len = 4'h0; endcase @@ -115628,42 +115628,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_internal_op = 7'h02; endcase @@ -115671,42 +115671,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_upd = 2'h0; endcase @@ -115714,42 +115714,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_rc_sel = 2'h2; endcase @@ -115757,42 +115757,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_cry_in = 2'h2; endcase @@ -115800,42 +115800,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_asmcode = 8'h84; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_asmcode = 8'h85; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_asmcode = 8'hbf; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_asmcode = 8'hc7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_asmcode = 8'hc0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_asmcode = 8'hc1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_asmcode = 8'hc2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_asmcode = 8'hc3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_asmcode = 8'hc5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_asmcode = 8'hc6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_asmcode = 8'hc8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_asmcode = 8'hc9; endcase @@ -115843,42 +115843,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_inv_a = 1'h1; endcase @@ -115886,42 +115886,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_inv_out = 1'h0; endcase @@ -115929,42 +115929,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_cry_out = 1'h1; endcase @@ -115972,42 +115972,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_br = 1'h0; endcase @@ -116015,42 +116015,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_sgn_ext = 1'h0; endcase @@ -116058,42 +116058,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_rsrv = 1'h0; endcase @@ -116101,42 +116101,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_form = 5'h11; endcase @@ -116144,42 +116144,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_is_32b = 1'h0; endcase @@ -116187,42 +116187,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_sgn = 1'h0; endcase @@ -116230,42 +116230,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_lk = 1'h0; endcase @@ -116273,42 +116273,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_sgl_pipe = 1'h0; endcase @@ -116316,42 +116316,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_SV_Etype = 2'h2; endcase @@ -116359,42 +116359,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_SV_Ptype = 2'h2; endcase @@ -116402,42 +116402,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_in1_sel = 3'h1; endcase @@ -116445,42 +116445,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_in2_sel = 4'h0; endcase @@ -116488,42 +116488,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_in3_sel = 2'h0; endcase @@ -116531,42 +116531,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h03: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h13: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h01: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h11: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h04: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h14: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h06: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h16: dec31_dec_sub8_out_sel = 3'h1; endcase @@ -116582,20 +116582,20 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_SV_Etype; reg [1:0] dec31_dec_sub9_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_SV_Ptype; reg [1:0] dec31_dec_sub9_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub9_asmcode; reg [7:0] dec31_dec_sub9_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_br; reg dec31_dec_sub9_br; (* enum_base_type = "CRInSel" *) @@ -116607,7 +116607,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_cr_in; reg [2:0] dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) @@ -116617,17 +116617,17 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_cr_out; reg [2:0] dec31_dec_sub9_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_cry_in; reg [1:0] dec31_dec_sub9_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_cry_out; reg dec31_dec_sub9_cry_out; (* enum_base_type = "Form" *) @@ -116661,7 +116661,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub9_form; reg [4:0] dec31_dec_sub9_form; (* enum_base_type = "Function" *) @@ -116679,7 +116679,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec31_dec_sub9_function_unit; reg [13:0] dec31_dec_sub9_function_unit; (* enum_base_type = "In1Sel" *) @@ -116688,7 +116688,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_in1_sel; reg [2:0] dec31_dec_sub9_in1_sel; (* enum_base_type = "In2Sel" *) @@ -116706,14 +116706,14 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub9_in2_sel; reg [3:0] dec31_dec_sub9_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_in3_sel; reg [1:0] dec31_dec_sub9_in3_sel; (* enum_base_type = "MicrOp" *) @@ -116791,16 +116791,16 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub9_internal_op; reg [6:0] dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_inv_a; reg dec31_dec_sub9_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_inv_out; reg dec31_dec_sub9_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_is_32b; reg dec31_dec_sub9_is_32b; (* enum_base_type = "LdstLen" *) @@ -116809,10 +116809,10 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub9_ldst_len; reg [3:0] dec31_dec_sub9_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_lk; reg dec31_dec_sub9_lk; (* enum_base_type = "OutSel" *) @@ -116821,26 +116821,26 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_out_sel; reg [2:0] dec31_dec_sub9_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_rc_sel; reg [1:0] dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_rsrv; reg dec31_dec_sub9_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_sgl_pipe; reg dec31_dec_sub9_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_sgn; reg dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_sgn_ext; reg dec31_dec_sub9_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -116850,7 +116850,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_cr_in; reg [2:0] dec31_dec_sub9_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -116860,7 +116860,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_cr_out; reg [2:0] dec31_dec_sub9_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -116870,7 +116870,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_in1; reg [2:0] dec31_dec_sub9_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -116880,7 +116880,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_in2; reg [2:0] dec31_dec_sub9_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -116890,7 +116890,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_in3; reg [2:0] dec31_dec_sub9_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -116900,7 +116900,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_out; reg [2:0] dec31_dec_sub9_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -116910,7 +116910,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_out2; reg [2:0] dec31_dec_sub9_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -116918,64 +116918,64 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_upd; reg [1:0] dec31_dec_sub9_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end dec31_dec_sub9_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_function_unit = 14'h0100; endcase @@ -116983,54 +116983,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_cr_in = 3'h0; endcase @@ -117038,54 +117038,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_cr_out = 3'h1; endcase @@ -117093,54 +117093,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_sv_in1 = 3'h2; endcase @@ -117148,54 +117148,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_sv_in2 = 3'h3; endcase @@ -117203,54 +117203,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_sv_in3 = 3'h0; endcase @@ -117258,54 +117258,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_sv_out = 3'h1; endcase @@ -117313,54 +117313,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_sv_out2 = 3'h0; endcase @@ -117368,54 +117368,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_sv_cr_in = 3'h0; endcase @@ -117423,54 +117423,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_sv_cr_out = 3'h1; endcase @@ -117478,54 +117478,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_ldst_len = 4'h0; endcase @@ -117533,54 +117533,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_internal_op = 7'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_internal_op = 7'h32; endcase @@ -117588,54 +117588,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_upd = 2'h0; endcase @@ -117643,54 +117643,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_rc_sel = 2'h2; endcase @@ -117698,54 +117698,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_cry_in = 2'h0; endcase @@ -117753,54 +117753,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_asmcode = 8'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_asmcode = 8'h37; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_asmcode = 8'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_asmcode = 8'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_asmcode = 8'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_asmcode = 8'h3a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_asmcode = 8'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_asmcode = 8'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_asmcode = 8'h74; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_asmcode = 8'h72; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_asmcode = 8'h7a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_asmcode = 8'h7b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_asmcode = 8'h7a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_asmcode = 8'h7b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_asmcode = 8'h7e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_asmcode = 8'h7f; endcase @@ -117808,54 +117808,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_inv_a = 1'h0; endcase @@ -117863,54 +117863,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_inv_out = 1'h0; endcase @@ -117918,54 +117918,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_cry_out = 1'h0; endcase @@ -117973,54 +117973,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_br = 1'h0; endcase @@ -118028,54 +118028,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_sgn_ext = 1'h0; endcase @@ -118083,54 +118083,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_rsrv = 1'h0; endcase @@ -118138,54 +118138,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_form = 5'h11; endcase @@ -118193,54 +118193,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_is_32b = 1'h0; endcase @@ -118248,54 +118248,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_sgn = 1'h1; endcase @@ -118303,54 +118303,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_lk = 1'h0; endcase @@ -118358,54 +118358,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_sgl_pipe = 1'h0; endcase @@ -118413,54 +118413,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_SV_Etype = 2'h2; endcase @@ -118468,54 +118468,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_SV_Ptype = 2'h1; endcase @@ -118523,54 +118523,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_in1_sel = 3'h1; endcase @@ -118578,54 +118578,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_in2_sel = 4'h1; endcase @@ -118633,54 +118633,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_in3_sel = 2'h0; endcase @@ -118688,54 +118688,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0c: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1c: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0d: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1d: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0e: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1e: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h0f: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h1f: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h08: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h18: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h02: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h00: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h12: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h10: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h07: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 5'h17: dec31_dec_sub9_out_sel = 3'h1; endcase @@ -118751,20 +118751,20 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_SV_Etype; reg [1:0] dec58_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_SV_Ptype; reg [1:0] dec58_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec58_asmcode; reg [7:0] dec58_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_br; reg dec58_br; (* enum_base_type = "CRInSel" *) @@ -118776,7 +118776,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_cr_in; reg [2:0] dec58_cr_in; (* enum_base_type = "CROutSel" *) @@ -118786,17 +118786,17 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_cr_out; reg [2:0] dec58_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_cry_in; reg [1:0] dec58_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_cry_out; reg dec58_cry_out; (* enum_base_type = "Form" *) @@ -118830,7 +118830,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec58_form; reg [4:0] dec58_form; (* enum_base_type = "Function" *) @@ -118848,7 +118848,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec58_function_unit; reg [13:0] dec58_function_unit; (* enum_base_type = "In1Sel" *) @@ -118857,7 +118857,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_in1_sel; reg [2:0] dec58_in1_sel; (* enum_base_type = "In2Sel" *) @@ -118875,14 +118875,14 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec58_in2_sel; reg [3:0] dec58_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_in3_sel; reg [1:0] dec58_in3_sel; (* enum_base_type = "MicrOp" *) @@ -118960,16 +118960,16 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec58_internal_op; reg [6:0] dec58_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_inv_a; reg dec58_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_inv_out; reg dec58_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_is_32b; reg dec58_is_32b; (* enum_base_type = "LdstLen" *) @@ -118978,10 +118978,10 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec58_ldst_len; reg [3:0] dec58_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_lk; reg dec58_lk; (* enum_base_type = "OutSel" *) @@ -118990,26 +118990,26 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_out_sel; reg [2:0] dec58_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_rc_sel; reg [1:0] dec58_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_rsrv; reg dec58_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_sgl_pipe; reg dec58_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_sgn; reg dec58_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_sgn_ext; reg dec58_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -119019,7 +119019,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_cr_in; reg [2:0] dec58_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -119029,7 +119029,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_cr_out; reg [2:0] dec58_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -119039,7 +119039,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_in1; reg [2:0] dec58_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -119049,7 +119049,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_in2; reg [2:0] dec58_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -119059,7 +119059,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_in3; reg [2:0] dec58_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -119069,7 +119069,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_out; reg [2:0] dec58_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -119079,7 +119079,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_out2; reg [2:0] dec58_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -119087,25 +119087,25 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_upd; reg [1:0] dec58_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [1:0] opcode_switch; always @* begin if (\initial ) begin end dec58_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_function_unit = 14'h0004; endcase @@ -119113,15 +119113,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_cr_in = 3'h0; endcase @@ -119129,15 +119129,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_cr_out = 3'h0; endcase @@ -119145,15 +119145,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_sv_in1 = 3'h2; endcase @@ -119161,15 +119161,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_sv_in2 = 3'h0; endcase @@ -119177,15 +119177,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_sv_in3 = 3'h0; endcase @@ -119193,15 +119193,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_sv_out = 3'h1; endcase @@ -119209,15 +119209,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_sv_out2 = 3'h0; endcase @@ -119225,15 +119225,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_sv_cr_in = 3'h0; endcase @@ -119241,15 +119241,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_sv_cr_out = 3'h0; endcase @@ -119257,15 +119257,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_ldst_len = 4'h4; endcase @@ -119273,15 +119273,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_internal_op = 7'h25; endcase @@ -119289,15 +119289,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_upd = 2'h0; endcase @@ -119305,15 +119305,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_rc_sel = 2'h0; endcase @@ -119321,15 +119321,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_cry_in = 2'h0; endcase @@ -119337,15 +119337,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_asmcode = 8'h52; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_asmcode = 8'h55; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_asmcode = 8'h62; endcase @@ -119353,15 +119353,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_inv_a = 1'h0; endcase @@ -119369,15 +119369,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_inv_out = 1'h0; endcase @@ -119385,15 +119385,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_cry_out = 1'h0; endcase @@ -119401,15 +119401,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_br = 1'h0; endcase @@ -119417,15 +119417,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_sgn_ext = 1'h1; endcase @@ -119433,15 +119433,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_rsrv = 1'h0; endcase @@ -119449,15 +119449,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_form = 5'h05; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_form = 5'h05; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_form = 5'h05; endcase @@ -119465,15 +119465,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_is_32b = 1'h0; endcase @@ -119481,15 +119481,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_sgn = 1'h0; endcase @@ -119497,15 +119497,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_lk = 1'h0; endcase @@ -119513,15 +119513,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_sgl_pipe = 1'h1; endcase @@ -119529,15 +119529,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_SV_Etype = 2'h2; endcase @@ -119545,15 +119545,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_SV_Ptype = 2'h2; endcase @@ -119561,15 +119561,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_in1_sel = 3'h2; endcase @@ -119577,15 +119577,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_in2_sel = 4'h8; endcase @@ -119593,15 +119593,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_in3_sel = 2'h0; endcase @@ -119609,15 +119609,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec58_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec58_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h2: dec58_out_sel = 3'h1; endcase @@ -119633,20 +119633,20 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_SV_Etype; reg [1:0] dec62_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_SV_Ptype; reg [1:0] dec62_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec62_asmcode; reg [7:0] dec62_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_br; reg dec62_br; (* enum_base_type = "CRInSel" *) @@ -119658,7 +119658,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_cr_in; reg [2:0] dec62_cr_in; (* enum_base_type = "CROutSel" *) @@ -119668,17 +119668,17 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_cr_out; reg [2:0] dec62_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_cry_in; reg [1:0] dec62_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_cry_out; reg dec62_cry_out; (* enum_base_type = "Form" *) @@ -119712,7 +119712,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec62_form; reg [4:0] dec62_form; (* enum_base_type = "Function" *) @@ -119730,7 +119730,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [13:0] dec62_function_unit; reg [13:0] dec62_function_unit; (* enum_base_type = "In1Sel" *) @@ -119739,7 +119739,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_in1_sel; reg [2:0] dec62_in1_sel; (* enum_base_type = "In2Sel" *) @@ -119757,14 +119757,14 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec62_in2_sel; reg [3:0] dec62_in2_sel; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_in3_sel; reg [1:0] dec62_in3_sel; (* enum_base_type = "MicrOp" *) @@ -119842,16 +119842,16 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec62_internal_op; reg [6:0] dec62_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_inv_a; reg dec62_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_inv_out; reg dec62_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_is_32b; reg dec62_is_32b; (* enum_base_type = "LdstLen" *) @@ -119860,10 +119860,10 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec62_ldst_len; reg [3:0] dec62_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_lk; reg dec62_lk; (* enum_base_type = "OutSel" *) @@ -119872,26 +119872,26 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_out_sel; reg [2:0] dec62_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_rc_sel; reg [1:0] dec62_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_rsrv; reg dec62_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_sgl_pipe; reg dec62_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_sgn; reg dec62_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_sgn_ext; reg dec62_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -119901,7 +119901,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_cr_in; reg [2:0] dec62_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -119911,7 +119911,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_cr_out; reg [2:0] dec62_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -119921,7 +119921,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_in1; reg [2:0] dec62_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -119931,7 +119931,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_in2; reg [2:0] dec62_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -119941,7 +119941,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_in3; reg [2:0] dec62_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -119951,7 +119951,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_out; reg [2:0] dec62_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -119961,7 +119961,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_out2; reg [2:0] dec62_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -119969,22 +119969,22 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_upd; reg [1:0] dec62_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:342" *) wire [1:0] opcode_switch; always @* begin if (\initial ) begin end dec62_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_function_unit = 14'h0004; endcase @@ -119992,12 +119992,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_cr_in = 3'h0; endcase @@ -120005,12 +120005,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_cr_out = 3'h0; endcase @@ -120018,12 +120018,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_sv_in1 = 3'h3; endcase @@ -120031,12 +120031,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_sv_in2 = 3'h0; endcase @@ -120044,12 +120044,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_sv_in3 = 3'h2; endcase @@ -120057,12 +120057,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_sv_out = 3'h0; endcase @@ -120070,12 +120070,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_sv_out2 = 3'h1; endcase @@ -120083,12 +120083,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_sv_cr_in = 3'h0; endcase @@ -120096,12 +120096,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_sv_cr_out = 3'h0; endcase @@ -120109,12 +120109,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_ldst_len = 4'h8; endcase @@ -120122,12 +120122,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_internal_op = 7'h26; endcase @@ -120135,12 +120135,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_upd = 2'h1; endcase @@ -120148,12 +120148,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_rc_sel = 2'h0; endcase @@ -120161,12 +120161,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_cry_in = 2'h0; endcase @@ -120174,12 +120174,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_asmcode = 8'had; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_asmcode = 8'hb0; endcase @@ -120187,12 +120187,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_inv_a = 1'h0; endcase @@ -120200,12 +120200,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_inv_out = 1'h0; endcase @@ -120213,12 +120213,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_cry_out = 1'h0; endcase @@ -120226,12 +120226,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_br = 1'h0; endcase @@ -120239,12 +120239,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_sgn_ext = 1'h0; endcase @@ -120252,12 +120252,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_rsrv = 1'h0; endcase @@ -120265,12 +120265,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_form = 5'h05; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_form = 5'h05; endcase @@ -120278,12 +120278,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_is_32b = 1'h0; endcase @@ -120291,12 +120291,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_sgn = 1'h0; endcase @@ -120304,12 +120304,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_lk = 1'h0; endcase @@ -120317,12 +120317,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_sgl_pipe = 1'h1; endcase @@ -120330,12 +120330,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_SV_Etype = 2'h1; endcase @@ -120343,12 +120343,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_SV_Ptype = 2'h2; endcase @@ -120356,12 +120356,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_in1_sel = 3'h2; endcase @@ -120369,12 +120369,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_in2_sel = 4'h8; endcase @@ -120382,12 +120382,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_in3_sel = 2'h1; endcase @@ -120395,12 +120395,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:443" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h0: dec62_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:445" */ 2'h1: dec62_out_sel = 3'h0; endcase @@ -120412,53 +120412,53 @@ endmodule (* generator = "nMigen" *) module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__data, ALU__imm_data__ok, ALU__rc__rc, ALU__rc__ok, ALU__oe__oe, ALU__oe__ok, ALU__invert_in, ALU__zero_a, ALU__invert_out, ALU__write_cr0, ALU__input_carry, ALU__output_carry, ALU__is_32bit, ALU__is_signed, ALU__data_len, ALU__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$8 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output [3:0] ALU__data_len; @@ -120593,27 +120593,27 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ reg ALU__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output ALU__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_ALU_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_ALU_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [23:0] dec_ALU_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_ALU_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_ALU_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_ALU_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_ALU_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_ALU_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] dec_ALU_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_ALU_UI; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -120622,15 +120622,15 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_ALU_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_ALU_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_ALU_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -120647,7 +120647,7 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec_ALU_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -120655,7 +120655,7 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_ALU_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -120672,7 +120672,7 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_ALU_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -120749,13 +120749,13 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_ALU_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_ALU_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_ALU_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_ALU_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -120763,19 +120763,19 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_ALU_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_ALU_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_ALU_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] dec_ALU_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:179" *) wire dec_ai_immz_out; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -120783,13 +120783,13 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:178" *) wire [2:0] dec_ai_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:180" *) wire dec_ai_sv_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -120806,68 +120806,68 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:462" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:841" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:840" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:835" *) wire [9:0] spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) input sv_a_nz; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$12 ; + assign \$16 = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) 7'h31; + assign \$18 = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 10'h2d0; + assign \$2 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) \$32 ; + assign \$36 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$42 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$8 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; dec dec ( .ALU_BD(dec_ALU_BD), .ALU_DS(dec_ALU_DS), @@ -120931,14 +120931,14 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ always @* begin if (\initial ) begin end ALU__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) casez (dec_ALU_cr_out) /* \nmigen.decoding = "CR0/1|CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:879" */ 3'h1, 3'h5: ALU__write_cr0 = dec_rc_rc; /* \nmigen.decoding = "BF/2|BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:881" */ 3'h2, 3'h3: ALU__write_cr0 = 1'h1; endcase @@ -120946,12 +120946,12 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ always @* begin if (\initial ) begin end ALU__insn_type = dec_ALU_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: ALU__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: ALU__insn_type = 7'h00; endcase @@ -120959,15 +120959,15 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: ALU__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: ALU__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:857" */ default: ALU__fn_unit = dec_ALU_function_unit; endcase @@ -121000,53 +121000,53 @@ endmodule (* generator = "nMigen" *) module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRANCH__fn_unit, BRANCH__insn, BRANCH__imm_data__data, BRANCH__imm_data__ok, BRANCH__lk, BRANCH__is_32bit, core_pc); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$8 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output [63:0] BRANCH__cia; @@ -121157,29 +121157,29 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output BRANCH__lk; reg BRANCH__lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) input [63:0] core_pc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_BRANCH_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_BRANCH_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [23:0] dec_BRANCH_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_BRANCH_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_BRANCH_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_BRANCH_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_BRANCH_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_BRANCH_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] dec_BRANCH_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_BRANCH_UI; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -121188,7 +121188,7 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_BRANCH_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -121205,7 +121205,7 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec_BRANCH_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -121222,7 +121222,7 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_BRANCH_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -121299,23 +121299,23 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_BRANCH_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_BRANCH_is_32b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_BRANCH_lk; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_BRANCH_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] dec_BRANCH_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -121332,58 +121332,58 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) wire [3:0] dec_bi_sel_in; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec_opcode_in; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:462" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:841" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:840" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:835" *) wire [9:0] spr; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$12 ; + assign \$16 = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) 7'h31; + assign \$18 = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 10'h2d0; + assign \$2 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) \$32 ; + assign \$36 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$42 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$8 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; \dec$141 dec ( .BRANCH_BD(dec_BRANCH_BD), .BRANCH_DS(dec_BRANCH_DS), @@ -121431,15 +121431,15 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: BRANCH__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: BRANCH__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:857" */ default: BRANCH__fn_unit = dec_BRANCH_function_unit; endcase @@ -121447,9 +121447,9 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN always @* begin if (\initial ) begin end BRANCH__lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:897" *) casez (dec_BRANCH_lk) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:897" */ 1'h1: BRANCH__lk = dec_BRANCH_LK; endcase @@ -121457,12 +121457,12 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN always @* begin if (\initial ) begin end BRANCH__insn_type = dec_BRANCH_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: BRANCH__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: BRANCH__insn_type = 7'h00; endcase @@ -121485,53 +121485,53 @@ endmodule (* generator = "nMigen" *) module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$8 ; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -121631,13 +121631,13 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output [6:0] CR__insn_type; reg [6:0] CR__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_CR_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_CR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] dec_CR_SPR; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -121646,7 +121646,7 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_CR_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -121663,7 +121663,7 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec_CR_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -121740,64 +121740,64 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_CR_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_CR_rc_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec_opcode_in; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:462" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:841" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:840" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:835" *) wire [9:0] spr; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$12 ; + assign \$16 = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) 7'h31; + assign \$18 = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 10'h2d0; + assign \$2 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) \$32 ; + assign \$36 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$42 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$8 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; \dec$138 dec ( .CR_OE(dec_CR_OE), .CR_Rc(dec_CR_Rc), @@ -121822,12 +121822,12 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); always @* begin if (\initial ) begin end CR__insn_type = dec_CR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: CR__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: CR__insn_type = 7'h00; endcase @@ -121835,15 +121835,15 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: CR__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: CR__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:857" */ default: CR__fn_unit = dec_CR_function_unit; endcase @@ -121862,53 +121862,53 @@ endmodule (* generator = "nMigen" *) module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__data, DIV__imm_data__ok, DIV__rc__rc, DIV__rc__ok, DIV__oe__oe, DIV__oe__ok, DIV__invert_in, DIV__zero_a, DIV__input_carry, DIV__invert_out, DIV__write_cr0, DIV__output_carry, DIV__is_32bit, DIV__is_signed, DIV__data_len, DIV__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$8 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output [3:0] DIV__data_len; @@ -122043,27 +122043,27 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ reg DIV__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output DIV__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_DIV_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_DIV_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [23:0] dec_DIV_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_DIV_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_DIV_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_DIV_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_DIV_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_DIV_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] dec_DIV_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_DIV_UI; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -122072,15 +122072,15 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_DIV_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_DIV_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_DIV_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -122097,7 +122097,7 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec_DIV_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -122105,7 +122105,7 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_DIV_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -122122,7 +122122,7 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_DIV_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -122199,13 +122199,13 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_DIV_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_DIV_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_DIV_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_DIV_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -122213,19 +122213,19 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_DIV_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_DIV_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_DIV_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] dec_DIV_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:179" *) wire dec_ai_immz_out; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -122233,13 +122233,13 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:178" *) wire [2:0] dec_ai_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:180" *) wire dec_ai_sv_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -122256,68 +122256,68 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:462" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:841" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:840" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:835" *) wire [9:0] spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) input sv_a_nz; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$12 ; + assign \$16 = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) 7'h31; + assign \$18 = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 10'h2d0; + assign \$2 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) \$32 ; + assign \$36 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$42 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$8 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; \dec$153 dec ( .DIV_BD(dec_DIV_BD), .DIV_DS(dec_DIV_DS), @@ -122381,14 +122381,14 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ always @* begin if (\initial ) begin end DIV__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) casez (dec_DIV_cr_out) /* \nmigen.decoding = "CR0/1|CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:879" */ 3'h1, 3'h5: DIV__write_cr0 = dec_rc_rc; /* \nmigen.decoding = "BF/2|BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:881" */ 3'h2, 3'h3: DIV__write_cr0 = 1'h1; endcase @@ -122396,12 +122396,12 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ always @* begin if (\initial ) begin end DIV__insn_type = dec_DIV_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: DIV__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: DIV__insn_type = 7'h00; endcase @@ -122409,15 +122409,15 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: DIV__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: DIV__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:857" */ default: DIV__fn_unit = dec_DIV_function_unit; endcase @@ -122450,53 +122450,53 @@ endmodule (* generator = "nMigen" *) module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_data__data, LDST__imm_data__ok, LDST__zero_a, LDST__rc__rc, LDST__rc__ok, LDST__oe__oe, LDST__oe__ok, LDST__is_32bit, LDST__is_signed, LDST__data_len, LDST__byte_reverse, LDST__sign_extend, LDST__ldst_mode, LDST__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$8 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output LDST__byte_reverse; @@ -122627,29 +122627,29 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da output LDST__sign_extend; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output LDST__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_LDST_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_LDST_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [23:0] dec_LDST_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_LDST_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_LDST_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_LDST_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_LDST_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_LDST_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] dec_LDST_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_LDST_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LDST_br; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -122658,7 +122658,7 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_LDST_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -122675,7 +122675,7 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec_LDST_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -122683,7 +122683,7 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_LDST_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -122700,7 +122700,7 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_LDST_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -122777,9 +122777,9 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_LDST_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LDST_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -122787,28 +122787,28 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_LDST_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_LDST_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LDST_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LDST_sgn_ext; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] dec_LDST_sh; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_LDST_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:179" *) wire dec_ai_immz_out; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -122816,13 +122816,13 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:178" *) wire [2:0] dec_ai_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:180" *) wire dec_ai_sv_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -122839,68 +122839,68 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:462" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:841" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:840" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:835" *) wire [9:0] spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) input sv_a_nz; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$12 ; + assign \$16 = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) 7'h31; + assign \$18 = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 10'h2d0; + assign \$2 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) \$32 ; + assign \$36 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$42 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$8 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; \dec$166 dec ( .LDST_BD(dec_LDST_BD), .LDST_DS(dec_LDST_DS), @@ -122963,12 +122963,12 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da always @* begin if (\initial ) begin end LDST__insn_type = dec_LDST_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: LDST__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: LDST__insn_type = 7'h00; endcase @@ -122976,15 +122976,15 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: LDST__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: LDST__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:857" */ default: LDST__fn_unit = dec_LDST_function_unit; endcase @@ -123016,53 +123016,53 @@ endmodule (* generator = "nMigen" *) module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOGICAL__imm_data__data, LOGICAL__imm_data__ok, LOGICAL__rc__rc, LOGICAL__rc__ok, LOGICAL__oe__oe, LOGICAL__oe__ok, LOGICAL__invert_in, LOGICAL__zero_a, LOGICAL__input_carry, LOGICAL__invert_out, LOGICAL__write_cr0, LOGICAL__output_carry, LOGICAL__is_32bit, LOGICAL__is_signed, LOGICAL__data_len, LOGICAL__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$8 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output [3:0] LOGICAL__data_len; @@ -123197,27 +123197,27 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG reg LOGICAL__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output LOGICAL__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_LOGICAL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_LOGICAL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [23:0] dec_LOGICAL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_LOGICAL_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_LOGICAL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_LOGICAL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_LOGICAL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_LOGICAL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] dec_LOGICAL_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_LOGICAL_UI; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -123226,15 +123226,15 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_LOGICAL_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_LOGICAL_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LOGICAL_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -123251,7 +123251,7 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec_LOGICAL_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -123259,7 +123259,7 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_LOGICAL_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -123276,7 +123276,7 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_LOGICAL_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -123353,13 +123353,13 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_LOGICAL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LOGICAL_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LOGICAL_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LOGICAL_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -123367,19 +123367,19 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_LOGICAL_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_LOGICAL_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LOGICAL_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] dec_LOGICAL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:179" *) wire dec_ai_immz_out; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -123387,13 +123387,13 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:178" *) wire [2:0] dec_ai_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:180" *) wire dec_ai_sv_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -123410,68 +123410,68 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:462" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:841" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:840" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:835" *) wire [9:0] spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) input sv_a_nz; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$12 ; + assign \$16 = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) 7'h31; + assign \$18 = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 10'h2d0; + assign \$2 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) \$32 ; + assign \$36 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$42 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$8 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; \dec$145 dec ( .LOGICAL_BD(dec_LOGICAL_BD), .LOGICAL_DS(dec_LOGICAL_DS), @@ -123535,14 +123535,14 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG always @* begin if (\initial ) begin end LOGICAL__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) casez (dec_LOGICAL_cr_out) /* \nmigen.decoding = "CR0/1|CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:879" */ 3'h1, 3'h5: LOGICAL__write_cr0 = dec_rc_rc; /* \nmigen.decoding = "BF/2|BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:881" */ 3'h2, 3'h3: LOGICAL__write_cr0 = 1'h1; endcase @@ -123550,12 +123550,12 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG always @* begin if (\initial ) begin end LOGICAL__insn_type = dec_LOGICAL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: LOGICAL__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: LOGICAL__insn_type = 7'h00; endcase @@ -123563,15 +123563,15 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: LOGICAL__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: LOGICAL__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:857" */ default: LOGICAL__fn_unit = dec_LOGICAL_function_unit; endcase @@ -123604,53 +123604,53 @@ endmodule (* generator = "nMigen" *) module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL__imm_data__ok, MUL__rc__rc, MUL__rc__ok, MUL__oe__oe, MUL__oe__ok, MUL__write_cr0, MUL__is_32bit, MUL__is_signed, MUL__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$8 ; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -123769,25 +123769,25 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output MUL__write_cr0; reg MUL__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_MUL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_MUL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [23:0] dec_MUL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_MUL_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_MUL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_MUL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_MUL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] dec_MUL_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_MUL_UI; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -123796,7 +123796,7 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_MUL_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -123813,7 +123813,7 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec_MUL_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -123830,7 +123830,7 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_MUL_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -123907,23 +123907,23 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_MUL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_MUL_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_MUL_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_MUL_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] dec_MUL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -123940,66 +123940,66 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:462" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:841" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:840" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:835" *) wire [9:0] spr; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$12 ; + assign \$16 = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) 7'h31; + assign \$18 = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 10'h2d0; + assign \$2 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) \$32 ; + assign \$36 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$42 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$8 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; \dec$158 dec ( .MUL_BD(dec_MUL_BD), .MUL_DS(dec_MUL_DS), @@ -124050,14 +124050,14 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL always @* begin if (\initial ) begin end MUL__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) casez (dec_MUL_cr_out) /* \nmigen.decoding = "CR0/1|CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:879" */ 3'h1, 3'h5: MUL__write_cr0 = dec_rc_rc; /* \nmigen.decoding = "BF/2|BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:881" */ 3'h2, 3'h3: MUL__write_cr0 = 1'h1; endcase @@ -124065,12 +124065,12 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL always @* begin if (\initial ) begin end MUL__insn_type = dec_MUL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: MUL__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: MUL__insn_type = 7'h00; endcase @@ -124078,15 +124078,15 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: MUL__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: MUL__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:857" */ default: MUL__fn_unit = dec_MUL_function_unit; endcase @@ -124111,53 +124111,53 @@ endmodule (* generator = "nMigen" *) module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ROT__imm_data__data, SHIFT_ROT__imm_data__ok, SHIFT_ROT__rc__rc, SHIFT_ROT__rc__ok, SHIFT_ROT__oe__oe, SHIFT_ROT__oe__ok, SHIFT_ROT__write_cr0, SHIFT_ROT__invert_in, SHIFT_ROT__input_carry, SHIFT_ROT__output_carry, SHIFT_ROT__input_cr, SHIFT_ROT__output_cr, SHIFT_ROT__is_32bit, SHIFT_ROT__is_signed, SHIFT_ROT__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$8 ; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -124290,25 +124290,25 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output SHIFT_ROT__write_cr0; reg SHIFT_ROT__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_SHIFT_ROT_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [13:0] dec_SHIFT_ROT_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [23:0] dec_SHIFT_ROT_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_SHIFT_ROT_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_SHIFT_ROT_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [4:0] dec_SHIFT_ROT_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_SHIFT_ROT_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] dec_SHIFT_ROT_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [15:0] dec_SHIFT_ROT_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -124319,7 +124319,7 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_SHIFT_ROT_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -124328,15 +124328,15 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_SHIFT_ROT_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_SHIFT_ROT_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_SHIFT_ROT_cry_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -124353,7 +124353,7 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec_SHIFT_ROT_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -124370,7 +124370,7 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_SHIFT_ROT_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -124447,25 +124447,25 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_SHIFT_ROT_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_SHIFT_ROT_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_SHIFT_ROT_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_SHIFT_ROT_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_SHIFT_ROT_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [5:0] dec_SHIFT_ROT_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -124482,66 +124482,66 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:462" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:841" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:840" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:835" *) wire [9:0] spr; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$12 ; + assign \$16 = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) 7'h31; + assign \$18 = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 10'h2d0; + assign \$2 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) \$32 ; + assign \$36 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$42 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$8 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; \dec$162 dec ( .SHIFT_ROT_BD(dec_SHIFT_ROT_BD), .SHIFT_ROT_DS(dec_SHIFT_ROT_DS), @@ -124596,14 +124596,14 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) casez (dec_SHIFT_ROT_cr_out) /* \nmigen.decoding = "CR0/1|CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:879" */ 3'h1, 3'h5: SHIFT_ROT__write_cr0 = dec_rc_rc; /* \nmigen.decoding = "BF/2|BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:881" */ 3'h2, 3'h3: SHIFT_ROT__write_cr0 = 1'h1; endcase @@ -124611,12 +124611,12 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT__insn_type = dec_SHIFT_ROT_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: SHIFT_ROT__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: SHIFT_ROT__insn_type = 7'h00; endcase @@ -124624,15 +124624,15 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: SHIFT_ROT__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: SHIFT_ROT__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:857" */ default: SHIFT_ROT__fn_unit = dec_SHIFT_ROT_function_unit; endcase @@ -124662,53 +124662,53 @@ endmodule (* generator = "nMigen" *) module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) wire \$8 ; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -124810,13 +124810,13 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit reg [6:0] SPR__insn_type; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output SPR__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_SPR_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire dec_SPR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [9:0] dec_SPR_SPR; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -124825,7 +124825,7 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_SPR_cr_out; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -124842,7 +124842,7 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [13:0] dec_SPR_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -124919,66 +124919,66 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_SPR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_SPR_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_SPR_rc_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:305" *) wire [31:0] dec_opcode_in; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:462" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:841" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:840" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:835" *) wire [9:0] spr; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$12 ; + assign \$16 = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:842" *) 7'h31; + assign \$18 = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:843" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) 10'h2d0; + assign \$2 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:846" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:847" *) \$32 ; + assign \$36 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$42 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) is_mmu_spr; + assign \$8 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" *) 14'h0800; \dec$150 dec ( .SPR_OE(dec_SPR_OE), .SPR_Rc(dec_SPR_Rc), @@ -125004,12 +125004,12 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit always @* begin if (\initial ) begin end SPR__insn_type = dec_SPR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: SPR__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: SPR__insn_type = 7'h00; endcase @@ -125017,15 +125017,15 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:849" */ 2'b?1: SPR__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:853" */ 2'b1?: SPR__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:857" */ default: SPR__fn_unit = dec_SPR_function_unit; endcase @@ -125045,58 +125045,58 @@ endmodule (* generator = "nMigen" *) module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_a_ok, RS, RA, BO, XL_XO, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:127" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) wire \$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:127" *) wire \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:128" *) wire \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:128" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) wire \$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:146" *) wire \$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:153" *) wire \$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:153" *) wire \$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [9:0] SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] fast_a; reg [2:0] fast_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast_a_ok; reg fast_a_ok; (* enum_base_type = "MicrOp" *) @@ -125174,17 +125174,17 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:125" *) wire [4:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [4:0] reg_a; reg [4:0] reg_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output reg_a_ok; reg reg_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:135" *) wire [4:0] rs; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -125192,9 +125192,9 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:110" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:160" *) reg [9:0] spr; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -125310,17 +125310,17 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [9:0] spr_a; reg [9:0] spr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spr_a_ok; reg spr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] sprmap_fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire sprmap_fast_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:75" *) reg [9:0] sprmap_spr_i; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -125436,31 +125436,31 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [9:0] sprmap_spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire sprmap_spr_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:115" *) input sv_nz; - assign \$9 = \$5 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$7 ; - assign \$11 = \$3 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$9 ; - assign \$13 = \$1 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$11 ; - assign \$15 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) 3'h4; - assign \$17 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) 3'h1; - assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) 3'h1; - assign \$19 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) 3'h2; - assign \$21 = ra != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 5'h00; - assign \$23 = sv_nz != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 1'h0; - assign \$25 = \$21 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$23 ; - assign \$27 = \$19 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$25 ; - assign \$29 = \$17 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$27 ; - assign \$31 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) 3'h4; - assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *) BO[2]; - assign \$35 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) XL_XO[5]; - assign \$37 = XL_XO[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) \$35 ; - assign \$3 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) 3'h2; - assign \$5 = ra != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 5'h00; - assign \$7 = sv_nz != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 1'h0; + assign \$9 = \$5 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$7 ; + assign \$11 = \$3 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$9 ; + assign \$13 = \$1 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$11 ; + assign \$15 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) 3'h4; + assign \$17 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:127" *) 3'h1; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:127" *) 3'h1; + assign \$19 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:128" *) 3'h2; + assign \$21 = ra != (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) 5'h00; + assign \$23 = sv_nz != (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) 1'h0; + assign \$25 = \$21 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$23 ; + assign \$27 = \$19 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$25 ; + assign \$29 = \$17 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$27 ; + assign \$31 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) 3'h4; + assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:146" *) BO[2]; + assign \$35 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:153" *) XL_XO[5]; + assign \$37 = XL_XO[9] & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:153" *) \$35 ; + assign \$3 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:128" *) 3'h2; + assign \$5 = ra != (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) 5'h00; + assign \$7 = sv_nz != (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) 1'h0; sprmap sprmap ( .fast_o(sprmap_fast_o), .fast_o_ok(sprmap_fast_o_ok), @@ -125471,15 +125471,15 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ always @* begin if (\initial ) begin end reg_a = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) casez (\$13 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" */ 1'h1: reg_a = ra; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) casez (\$15 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" */ 1'h1: reg_a = rs; endcase @@ -125487,15 +125487,15 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ always @* begin if (\initial ) begin end reg_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) casez (\$29 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" */ 1'h1: reg_a_ok = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) casez (\$31 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" */ 1'h1: reg_a_ok = 1'h1; endcase @@ -125504,14 +125504,14 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ if (\initial ) begin end fast_a = 3'h0; fast_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:142" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:145" */ 7'h07: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:146" *) casez (\$33 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:146" */ 1'h1: begin fast_a = 3'h0; @@ -125519,11 +125519,11 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ end endcase /* \nmigen.decoding = "OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:150" */ 7'h08: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:153" *) casez (\$37 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:153" */ 1'h1: begin fast_a = 3'h0; @@ -125531,7 +125531,7 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ end endcase /* \nmigen.decoding = "OP_MFSPR/46" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:159" */ 7'h2e: { fast_a_ok, fast_a } = { sprmap_fast_o_ok, sprmap_fast_o }; endcase @@ -125539,18 +125539,18 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ always @* begin if (\initial ) begin end spr = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:142" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:145" */ 7'h07: /* empty */; /* \nmigen.decoding = "OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:150" */ 7'h08: /* empty */; /* \nmigen.decoding = "OP_MFSPR/46" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:159" */ 7'h2e: spr = { SPR[4:0], SPR[9:5] }; endcase @@ -125558,18 +125558,18 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ always @* begin if (\initial ) begin end sprmap_spr_i = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:142" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:145" */ 7'h07: /* empty */; /* \nmigen.decoding = "OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:150" */ 7'h08: /* empty */; /* \nmigen.decoding = "OP_MFSPR/46" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:159" */ 7'h2e: sprmap_spr_i = spr; endcase @@ -125578,18 +125578,18 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ if (\initial ) begin end spr_a = 10'h000; spr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:142" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:145" */ 7'h07: /* empty */; /* \nmigen.decoding = "OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:150" */ 7'h08: /* empty */; /* \nmigen.decoding = "OP_MFSPR/46" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:159" */ 7'h2e: { spr_a_ok, spr_a } = { sprmap_spr_o_ok, sprmap_spr_o }; endcase @@ -125602,22 +125602,22 @@ endmodule (* generator = "nMigen" *) module dec_ai(sel_in, immz_out, ALU_RA, sv_nz); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] ALU_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:179" *) output immz_out; reg immz_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:187" *) wire [4:0] ra; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -125625,21 +125625,21 @@ module dec_ai(sel_in, immz_out, ALU_RA, sv_nz); (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:178" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:180" *) input sv_nz; - assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; - assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; - assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; - assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; - assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) 1'h0; always @* begin if (\initial ) begin end immz_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" */ 1'h1: immz_out = 1'h1; endcase @@ -125651,22 +125651,22 @@ endmodule (* generator = "nMigen" *) module \dec_ai$148 (sel_in, immz_out, LOGICAL_RA, sv_nz); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] LOGICAL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:179" *) output immz_out; reg immz_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:187" *) wire [4:0] ra; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -125674,21 +125674,21 @@ module \dec_ai$148 (sel_in, immz_out, LOGICAL_RA, sv_nz); (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:178" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:180" *) input sv_nz; - assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; - assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; - assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; - assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; - assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) 1'h0; always @* begin if (\initial ) begin end immz_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" */ 1'h1: immz_out = 1'h1; endcase @@ -125700,22 +125700,22 @@ endmodule (* generator = "nMigen" *) module \dec_ai$156 (sel_in, immz_out, DIV_RA, sv_nz); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] DIV_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:179" *) output immz_out; reg immz_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:187" *) wire [4:0] ra; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -125723,21 +125723,21 @@ module \dec_ai$156 (sel_in, immz_out, DIV_RA, sv_nz); (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:178" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:180" *) input sv_nz; - assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; - assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; - assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; - assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; - assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) 1'h0; always @* begin if (\initial ) begin end immz_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" */ 1'h1: immz_out = 1'h1; endcase @@ -125749,22 +125749,22 @@ endmodule (* generator = "nMigen" *) module \dec_ai$169 (sel_in, immz_out, LDST_RA, sv_nz); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] LDST_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:179" *) output immz_out; reg immz_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:187" *) wire [4:0] ra; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -125772,21 +125772,21 @@ module \dec_ai$169 (sel_in, immz_out, LDST_RA, sv_nz); (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:178" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:180" *) input sv_nz; - assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; - assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; - assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; - assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; - assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:190" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) 1'h0; always @* begin if (\initial ) begin end immz_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:191" */ 1'h1: immz_out = 1'h1; endcase @@ -125798,28 +125798,28 @@ endmodule (* generator = "nMigen" *) module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [6:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:236" *) wire \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [6:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:233" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:236" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:233" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] fast_b; reg [2:0] fast_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast_b_ok; reg fast_b_ok; (* enum_base_type = "MicrOp" *) @@ -125897,12 +125897,12 @@ module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [6:0] reg_b; reg [6:0] reg_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output reg_b_ok; reg reg_b_ok; (* enum_base_type = "In2Sel" *) @@ -125920,25 +125920,25 @@ module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:208" *) input [3:0] sel_in; - assign \$9 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) 7'h08; - assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) XL_XO[9]; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) RB; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) RS; - assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) 7'h08; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) XL_XO[9]; + assign \$9 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:233" *) 7'h08; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:236" *) XL_XO[9]; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) RB; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) RS; + assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:233" *) 7'h08; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:236" *) XL_XO[9]; always @* begin if (\initial ) begin end reg_b = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:221" *) casez (sel_in) /* \nmigen.decoding = "RB/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:222" */ 4'h1: reg_b = \$1 ; /* \nmigen.decoding = "RS/13" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:225" */ 4'hd: reg_b = \$3 ; endcase @@ -125946,14 +125946,14 @@ module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal always @* begin if (\initial ) begin end reg_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:221" *) casez (sel_in) /* \nmigen.decoding = "RB/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:222" */ 4'h1: reg_b_ok = 1'h1; /* \nmigen.decoding = "RS/13" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:225" */ 4'hd: reg_b_ok = 1'h1; endcase @@ -125961,16 +125961,16 @@ module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal always @* begin if (\initial ) begin end fast_b = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:233" *) casez (\$5 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:233" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:236" *) casez ({ XL_XO[5], \$7 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:236" */ 2'b?1: fast_b = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:240" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:239" */ 2'b1?: fast_b = 3'h2; endcase @@ -125979,16 +125979,16 @@ module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal always @* begin if (\initial ) begin end fast_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:233" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:233" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:236" *) casez ({ XL_XO[5], \$11 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:236" */ 2'b?1: fast_b_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:240" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:239" */ 2'b1?: fast_b_ok = 1'h1; endcase @@ -126000,59 +126000,59 @@ endmodule (* generator = "nMigen" *) module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, ALU_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] ALU_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] ALU_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [23:0] ALU_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] ALU_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] ALU_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] ALU_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [5:0] ALU_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:284" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:289" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:279" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -126069,67 +126069,67 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:264" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:269" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:274" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_SH32; - assign \$14 = ALU_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = ALU_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_UI; - assign \$20 = ALU_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = ALU_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) ALU_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) ALU_SH32; + assign \$14 = ALU_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) 5'h10; + assign \$17 = ALU_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) ALU_UI; + assign \$20 = ALU_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) 2'h2; + assign \$23 = ALU_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b = \$11 ; endcase @@ -126137,46 +126137,46 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -126184,14 +126184,14 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: si = ALU_SI; endcase @@ -126199,18 +126199,18 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -126218,22 +126218,22 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: ui = ALU_UI; endcase @@ -126241,26 +126241,26 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: li = \$16 [25:0]; endcase @@ -126268,30 +126268,30 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: bd = \$19 [15:0]; endcase @@ -126299,34 +126299,34 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: ds = \$22 [15:0]; endcase @@ -126341,59 +126341,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_sh, BRANCH_LI, BRANCH_BD, BRANCH_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] BRANCH_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] BRANCH_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [23:0] BRANCH_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] BRANCH_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] BRANCH_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] BRANCH_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [5:0] BRANCH_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:284" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:289" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:279" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -126410,67 +126410,67 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:264" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:269" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:274" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_SH32; - assign \$14 = BRANCH_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = BRANCH_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_UI; - assign \$20 = BRANCH_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = BRANCH_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) BRANCH_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) BRANCH_SH32; + assign \$14 = BRANCH_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) 5'h10; + assign \$17 = BRANCH_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) BRANCH_UI; + assign \$20 = BRANCH_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) 2'h2; + assign \$23 = BRANCH_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b = \$11 ; endcase @@ -126478,46 +126478,46 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -126525,14 +126525,14 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: si = BRANCH_SI; endcase @@ -126540,18 +126540,18 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -126559,22 +126559,22 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: ui = BRANCH_UI; endcase @@ -126582,26 +126582,26 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: li = \$16 [25:0]; endcase @@ -126609,30 +126609,30 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: bd = \$19 [15:0]; endcase @@ -126640,34 +126640,34 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: ds = \$22 [15:0]; endcase @@ -126682,59 +126682,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGICAL_sh, LOGICAL_LI, LOGICAL_BD, LOGICAL_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] LOGICAL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] LOGICAL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [23:0] LOGICAL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] LOGICAL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] LOGICAL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] LOGICAL_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [5:0] LOGICAL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:284" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:289" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:279" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -126751,67 +126751,67 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:264" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:269" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:274" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_SH32; - assign \$14 = LOGICAL_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = LOGICAL_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_UI; - assign \$20 = LOGICAL_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = LOGICAL_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) LOGICAL_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) LOGICAL_SH32; + assign \$14 = LOGICAL_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) 5'h10; + assign \$17 = LOGICAL_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) LOGICAL_UI; + assign \$20 = LOGICAL_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) 2'h2; + assign \$23 = LOGICAL_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b = \$11 ; endcase @@ -126819,46 +126819,46 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -126866,14 +126866,14 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: si = LOGICAL_SI; endcase @@ -126881,18 +126881,18 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -126900,22 +126900,22 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: ui = LOGICAL_UI; endcase @@ -126923,26 +126923,26 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: li = \$16 [25:0]; endcase @@ -126950,30 +126950,30 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: bd = \$19 [15:0]; endcase @@ -126981,34 +126981,34 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: ds = \$22 [15:0]; endcase @@ -127023,59 +127023,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, DIV_BD, DIV_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] DIV_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] DIV_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [23:0] DIV_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] DIV_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] DIV_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] DIV_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [5:0] DIV_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:284" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:289" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:279" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -127092,67 +127092,67 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:264" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:269" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:274" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_SH32; - assign \$14 = DIV_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = DIV_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_UI; - assign \$20 = DIV_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = DIV_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) DIV_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) DIV_SH32; + assign \$14 = DIV_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) 5'h10; + assign \$17 = DIV_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) DIV_UI; + assign \$20 = DIV_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) 2'h2; + assign \$23 = DIV_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b = \$11 ; endcase @@ -127160,46 +127160,46 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -127207,14 +127207,14 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: si = DIV_SI; endcase @@ -127222,18 +127222,18 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -127241,22 +127241,22 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: ui = DIV_UI; endcase @@ -127264,26 +127264,26 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: li = \$16 [25:0]; endcase @@ -127291,30 +127291,30 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: bd = \$19 [15:0]; endcase @@ -127322,34 +127322,34 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: ds = \$22 [15:0]; endcase @@ -127364,59 +127364,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, MUL_BD, MUL_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] MUL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] MUL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [23:0] MUL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] MUL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] MUL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] MUL_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [5:0] MUL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:284" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:289" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:279" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -127433,67 +127433,67 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:264" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:269" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:274" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_SH32; - assign \$14 = MUL_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = MUL_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_UI; - assign \$20 = MUL_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = MUL_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) MUL_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) MUL_SH32; + assign \$14 = MUL_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) 5'h10; + assign \$17 = MUL_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) MUL_UI; + assign \$20 = MUL_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) 2'h2; + assign \$23 = MUL_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b = \$11 ; endcase @@ -127501,46 +127501,46 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -127548,14 +127548,14 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: si = MUL_SI; endcase @@ -127563,18 +127563,18 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -127582,22 +127582,22 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: ui = MUL_UI; endcase @@ -127605,26 +127605,26 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: li = \$16 [25:0]; endcase @@ -127632,30 +127632,30 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: bd = \$19 [15:0]; endcase @@ -127663,34 +127663,34 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: ds = \$22 [15:0]; endcase @@ -127705,59 +127705,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, SHIFT_ROT_sh, SHIFT_ROT_LI, SHIFT_ROT_BD, SHIFT_ROT_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] SHIFT_ROT_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] SHIFT_ROT_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [23:0] SHIFT_ROT_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] SHIFT_ROT_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] SHIFT_ROT_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] SHIFT_ROT_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [5:0] SHIFT_ROT_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:284" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:289" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:279" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -127774,67 +127774,67 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:264" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:269" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:274" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_SH32; - assign \$14 = SHIFT_ROT_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = SHIFT_ROT_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_UI; - assign \$20 = SHIFT_ROT_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = SHIFT_ROT_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) SHIFT_ROT_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) SHIFT_ROT_SH32; + assign \$14 = SHIFT_ROT_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) 5'h10; + assign \$17 = SHIFT_ROT_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) SHIFT_ROT_UI; + assign \$20 = SHIFT_ROT_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) 2'h2; + assign \$23 = SHIFT_ROT_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b = \$11 ; endcase @@ -127842,46 +127842,46 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -127889,14 +127889,14 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: si = SHIFT_ROT_SI; endcase @@ -127904,18 +127904,18 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -127923,22 +127923,22 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: ui = SHIFT_ROT_UI; endcase @@ -127946,26 +127946,26 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: li = \$16 [25:0]; endcase @@ -127973,30 +127973,30 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: bd = \$19 [15:0]; endcase @@ -128004,34 +128004,34 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: ds = \$22 [15:0]; endcase @@ -128046,59 +128046,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_LI, LDST_BD, LDST_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] LDST_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [13:0] LDST_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [23:0] LDST_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] LDST_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] LDST_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [15:0] LDST_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [5:0] LDST_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:284" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:289" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:279" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -128115,67 +128115,67 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:251" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:264" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:269" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:274" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_SH32; - assign \$14 = LDST_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = LDST_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_UI; - assign \$20 = LDST_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = LDST_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) LDST_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) LDST_SH32; + assign \$14 = LDST_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:270" *) 5'h10; + assign \$17 = LDST_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) LDST_UI; + assign \$20 = LDST_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" *) 2'h2; + assign \$23 = LDST_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:294" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b = \$11 ; endcase @@ -128183,46 +128183,46 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:299" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -128230,14 +128230,14 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: si = LDST_SI; endcase @@ -128245,18 +128245,18 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -128264,22 +128264,22 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: ui = LDST_UI; endcase @@ -128287,26 +128287,26 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: li = \$16 [25:0]; endcase @@ -128314,30 +128314,30 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: bd = \$19 [15:0]; endcase @@ -128345,34 +128345,34 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:259" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:260" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:263" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:273" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:278" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:283" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:288" */ 4'h8: ds = \$22 [15:0]; endcase @@ -128387,33 +128387,33 @@ endmodule (* generator = "nMigen" *) module dec_c(reg_c, reg_c_ok, RS, RB, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [4:0] reg_c; reg [4:0] reg_c; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output reg_c_ok; reg reg_c_ok; (* enum_base_type = "In3Sel" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "RS" *) (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:314" *) input [1:0] sel_in; always @* begin if (\initial ) begin end reg_c = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:325" *) casez (sel_in) /* \nmigen.decoding = "RB/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:327" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:326" */ 2'h2: reg_c = RB; /* \nmigen.decoding = "RS/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:330" */ 2'h1: reg_c = RS; endcase @@ -128421,14 +128421,14 @@ module dec_c(reg_c, reg_c_ok, RS, RB, sel_in); always @* begin if (\initial ) begin end reg_c_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:325" *) casez (sel_in) /* \nmigen.decoding = "RB/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:327" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:326" */ 2'h2: reg_c_ok = 1'h1; /* \nmigen.decoding = "RS/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:330" */ 2'h1: reg_c_ok = 1'h1; endcase @@ -128439,53 +128439,53 @@ endmodule (* generator = "nMigen" *) module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok, cr_bitfield_b, cr_bitfield_b_ok, cr_bitfield_o, cr_bitfield_o_ok, BB, BA, BT, FXM, BI, BC, X_BFA, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [7:0] FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] cr_bitfield; reg [2:0] cr_bitfield; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] cr_bitfield_b; reg [2:0] cr_bitfield_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_bitfield_b_ok; reg cr_bitfield_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] cr_bitfield_o; reg [2:0] cr_bitfield_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_bitfield_o_ok; reg cr_bitfield_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_bitfield_ok; reg cr_bitfield_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [7:0] cr_fxm; reg [7:0] cr_fxm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_fxm_ok; reg cr_fxm_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:542" *) input [31:0] insn_in; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -128562,9 +128562,9 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) reg move_one; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) reg [7:0] ppick_i; @@ -128579,14 +128579,14 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:541" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" *) reg [1:0] sv_override; - assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) 7'h2d; - assign \$3 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) move_one; - assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) 7'h2d; - assign \$7 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) move_one; + assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" *) 7'h2d; + assign \$3 = \$1 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" *) move_one; + assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" *) 7'h2d; + assign \$7 = \$5 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" *) move_one; ppick ppick ( .i(ppick_i), .o(ppick_o) @@ -128594,34 +128594,34 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:575" */ 3'h2: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:578" */ 3'h3: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:581" */ 3'h4: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:588" */ 3'h5: cr_bitfield_ok = 1'h1; endcase @@ -128629,30 +128629,30 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:575" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:578" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:581" */ 3'h4: cr_bitfield_b_ok = 1'h1; endcase @@ -128661,46 +128661,46 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok if (\initial ) begin end cr_fxm = 8'h00; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:575" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:578" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:581" */ 3'h4: /* empty */; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:588" */ 3'h5: /* empty */; /* \nmigen.decoding = "WHOLE_REG/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:591" */ 3'h6: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" *) casez (\$7 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" */ 1'h1: cr_fxm = ppick_o; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:600" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:599" */ default: cr_fxm = 8'hff; endcase @@ -128709,30 +128709,30 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:575" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:578" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:581" */ 3'h4: cr_bitfield_o_ok = 1'h1; endcase @@ -128741,38 +128741,38 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok if (\initial ) begin end cr_fxm_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:575" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:578" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:581" */ 3'h4: /* empty */; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:588" */ 3'h5: /* empty */; /* \nmigen.decoding = "WHOLE_REG/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:591" */ 3'h6: cr_fxm_ok = 1'h1; endcase @@ -128780,18 +128780,18 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end sv_override = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: sv_override = 2'h1; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: sv_override = 2'h2; endcase @@ -128799,34 +128799,34 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: cr_bitfield = 3'h0; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: cr_bitfield = 3'h1; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:575" */ 3'h2: cr_bitfield = BI[4:2]; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:578" */ 3'h3: cr_bitfield = X_BFA; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:581" */ 3'h4: cr_bitfield = BA[4:2]; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:588" */ 3'h5: cr_bitfield = BC[4:2]; endcase @@ -128834,30 +128834,30 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield_b = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:575" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:578" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:581" */ 3'h4: cr_bitfield_b = BB[4:2]; endcase @@ -128865,30 +128865,30 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield_o = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:575" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:578" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:581" */ 3'h4: cr_bitfield_o = BT[4:2]; endcase @@ -128897,38 +128897,38 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok if (\initial ) begin end move_one = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:575" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:578" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:581" */ 3'h4: /* empty */; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:588" */ 3'h5: /* empty */; /* \nmigen.decoding = "WHOLE_REG/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:591" */ 3'h6: move_one = insn_in[20]; endcase @@ -128937,42 +128937,42 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok if (\initial ) begin end ppick_i = 8'h00; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:564" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:565" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:567" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:575" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:578" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:581" */ 3'h4: /* empty */; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:588" */ 3'h5: /* empty */; /* \nmigen.decoding = "WHOLE_REG/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:591" */ 3'h6: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" *) casez (\$3 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:595" */ 1'h1: ppick_i = FXM; endcase @@ -128984,29 +128984,29 @@ endmodule (* generator = "nMigen" *) module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok, FXM, X_BF, XL_BT, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:660" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:660" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [7:0] FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] cr_bitfield; reg [2:0] cr_bitfield; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_bitfield_ok; reg cr_bitfield_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [7:0] cr_fxm; reg [7:0] cr_fxm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_fxm_ok; reg cr_fxm_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:617" *) input [31:0] insn_in; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -129083,9 +129083,9 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:659" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:658" *) reg move_one; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire ppick_en_o; @@ -129093,7 +129093,7 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit reg [7:0] ppick_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) wire [7:0] ppick_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:615" *) input rc_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -129102,12 +129102,12 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:616" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:621" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:620" *) reg [1:0] sv_override; - assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) 7'h30; - assign \$3 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) 7'h30; + assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:660" *) 7'h30; + assign \$3 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:660" *) 7'h30; \ppick$175 ppick ( .en_o(ppick_en_o), .i(ppick_i), @@ -129116,26 +129116,26 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end cr_bitfield_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:639" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:640" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:642" */ 3'h1: cr_bitfield_ok = rc_in; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:646" */ 3'h5: cr_bitfield_ok = rc_in; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:650" */ 3'h2: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:653" */ 3'h3: cr_bitfield_ok = 1'h1; endcase @@ -129143,30 +129143,30 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end cr_fxm_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:639" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:640" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:642" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:646" */ 3'h5: /* empty */; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:650" */ 3'h2: /* empty */; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "WHOLE_REG/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:656" */ 3'h4: cr_fxm_ok = 1'h1; endcase @@ -129174,18 +129174,18 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end sv_override = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:639" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:640" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:642" */ 3'h1: sv_override = 2'h1; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:646" */ 3'h5: sv_override = 2'h2; endcase @@ -129193,26 +129193,26 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end cr_bitfield = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:639" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:640" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:642" */ 3'h1: cr_bitfield = 3'h0; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:646" */ 3'h5: cr_bitfield = 3'h1; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:650" */ 3'h2: cr_bitfield = X_BF; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:653" */ 3'h3: cr_bitfield = XL_BT[4:2]; endcase @@ -129220,30 +129220,30 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end move_one = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:639" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:640" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:642" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:646" */ 3'h5: /* empty */; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:650" */ 3'h2: /* empty */; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "WHOLE_REG/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:656" */ 3'h4: move_one = insn_in[20]; endcase @@ -129251,38 +129251,38 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end ppick_i = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:639" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:640" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:642" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:646" */ 3'h5: /* empty */; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:650" */ 3'h2: /* empty */; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "WHOLE_REG/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:656" */ 3'h4: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:660" *) casez (\$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:660" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:661" *) casez (move_one) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:661" */ 1'h1: ppick_i = FXM; endcase @@ -129292,56 +129292,56 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end cr_fxm = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:639" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:640" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:642" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:646" */ 3'h5: /* empty */; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:650" */ 3'h2: /* empty */; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "WHOLE_REG/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:656" */ 3'h4: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:660" *) casez (\$3 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:660" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:661" *) casez (move_one) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:661" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:664" *) casez (ppick_en_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:664" */ 1'h1: cr_fxm = ppick_o; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:667" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:666" */ default: cr_fxm = 8'h01; endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:669" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:668" */ default: cr_fxm = FXM; endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:670" */ default: cr_fxm = 8'hff; endcase @@ -129353,26 +129353,26 @@ endmodule (* generator = "nMigen" *) module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, RT, RA, BO, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:385" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [9:0] SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] fast_o; reg [2:0] fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast_o_ok; reg fast_o_ok; (* enum_base_type = "MicrOp" *) @@ -129450,12 +129450,12 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [4:0] reg_o; reg [4:0] reg_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output reg_o_ok; reg reg_o_ok; (* enum_base_type = "OutSel" *) @@ -129464,9 +129464,9 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:350" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:372" *) reg [9:0] spr; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -129582,17 +129582,17 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [9:0] spr_o; reg [9:0] spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spr_o_ok; reg spr_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] sprmap_fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire sprmap_fast_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:75" *) reg [9:0] sprmap_spr_i; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -129708,14 +129708,14 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [9:0] sprmap_spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire sprmap_spr_o_ok; - assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31; - assign \$3 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31; - assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *) BO[2]; + assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" *) 7'h31; + assign \$3 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" *) 7'h31; + assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" *) 7'h31; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:385" *) BO[2]; \sprmap$174 sprmap ( .fast_o(sprmap_fast_o), .fast_o_ok(sprmap_fast_o_ok), @@ -129726,14 +129726,14 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R always @* begin if (\initial ) begin end reg_o = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:364" *) casez (sel_in) /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:365" */ 3'h1: reg_o = RT; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:368" */ 3'h2: reg_o = RA; endcase @@ -129741,14 +129741,14 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R always @* begin if (\initial ) begin end reg_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:364" *) casez (sel_in) /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:365" */ 3'h1: reg_o_ok = 1'h1; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:368" */ 3'h2: reg_o_ok = 1'h1; endcase @@ -129756,18 +129756,18 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R always @* begin if (\initial ) begin end spr = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:364" *) casez (sel_in) /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:365" */ 3'h1: /* empty */; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:368" */ 3'h2: /* empty */; /* \nmigen.decoding = "SPR/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:371" */ 3'h3: spr = { SPR[4:0], SPR[9:5] }; endcase @@ -129775,22 +129775,22 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R always @* begin if (\initial ) begin end sprmap_spr_i = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:364" *) casez (sel_in) /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:365" */ 3'h1: /* empty */; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:368" */ 3'h2: /* empty */; /* \nmigen.decoding = "SPR/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:371" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" *) casez (\$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" */ 1'h1: sprmap_spr_i = spr; endcase @@ -129800,22 +129800,22 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R if (\initial ) begin end spr_o = 10'h000; spr_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:364" *) casez (sel_in) /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:365" */ 3'h1: /* empty */; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:368" */ 3'h2: /* empty */; /* \nmigen.decoding = "SPR/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:371" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" *) casez (\$3 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" */ 1'h1: { spr_o_ok, spr_o } = { sprmap_spr_o_ok, sprmap_spr_o }; endcase @@ -129825,34 +129825,34 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R if (\initial ) begin end fast_o = 3'h0; fast_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:364" *) casez (sel_in) /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:365" */ 3'h1: /* empty */; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:368" */ 3'h2: /* empty */; /* \nmigen.decoding = "SPR/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:371" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" *) casez (\$5 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:375" */ 1'h1: { fast_o_ok, fast_o } = { sprmap_fast_o_ok, sprmap_fast_o }; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:382" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:381" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7|OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:384" */ 7'h07, 7'h08: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:385" *) casez (\$7 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:385" */ 1'h1: begin fast_o = 3'h0; @@ -129860,7 +129860,7 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R end endcase /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:392" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:391" */ 7'h46: begin fast_o = 3'h3; @@ -129874,16 +129874,16 @@ endmodule (* generator = "nMigen" *) module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:431" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:431" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input [4:0] RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] fast_o2; reg [2:0] fast_o2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast_o2_ok; reg fast_o2_ok; (* enum_base_type = "MicrOp" *) @@ -129961,14 +129961,14 @@ module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:415" *) input lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [4:0] reg_o2; reg [4:0] reg_o2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output reg_o2_ok; reg reg_o2_ok; (* enum_base_type = "LDSTMode" *) @@ -129976,16 +129976,16 @@ module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [1:0] upd; - assign \$1 = upd == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) 2'h1; - assign \$3 = upd == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) 2'h1; + assign \$1 = upd == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:431" *) 2'h1; + assign \$3 = upd == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:431" *) 2'h1; always @* begin if (\initial ) begin end reg_o2 = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:431" *) casez (\$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:431" */ 1'h1: reg_o2 = RA; endcase @@ -129993,9 +129993,9 @@ module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); always @* begin if (\initial ) begin end reg_o2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:431" *) casez (\$3 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:431" */ 1'h1: reg_o2_ok = 1'h1; endcase @@ -130003,19 +130003,19 @@ module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); always @* begin if (\initial ) begin end fast_o2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:437" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7|OP_B/6|OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:440" */ 7'h07, 7'h06, 7'h08: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:441" *) casez (lk) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:441" */ 1'h1: fast_o2 = 3'h1; endcase /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:447" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:446" */ 7'h46: fast_o2 = 3'h4; endcase @@ -130023,19 +130023,19 @@ module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); always @* begin if (\initial ) begin end fast_o2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:437" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7|OP_B/6|OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:440" */ 7'h07, 7'h06, 7'h08: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:441" *) casez (lk) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:441" */ 1'h1: fast_o2_ok = 1'h1; endcase /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:447" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:446" */ 7'h46: fast_o2_ok = 1'h1; endcase @@ -130046,7 +130046,7 @@ endmodule (* generator = "nMigen" *) module dec_oe(ALU_internal_op, oe, oe_ok, ALU_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input ALU_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130123,37 +130123,37 @@ module dec_oe(ALU_internal_op, oe, oe_ok, ALU_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] ALU_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (ALU_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe = ALU_OE; endcase @@ -130163,19 +130163,19 @@ module dec_oe(ALU_internal_op, oe, oe_ok, ALU_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (ALU_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe_ok = 1'h1; endcase @@ -130187,7 +130187,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$140 (CR_internal_op, CR_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input CR_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130264,35 +130264,35 @@ module \dec_oe$140 (CR_internal_op, CR_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] CR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (CR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe = CR_OE; endcase @@ -130302,19 +130302,19 @@ module \dec_oe$140 (CR_internal_op, CR_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (CR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe_ok = 1'h1; endcase @@ -130326,7 +130326,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$143 (BRANCH_internal_op, BRANCH_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input BRANCH_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130403,35 +130403,35 @@ module \dec_oe$143 (BRANCH_internal_op, BRANCH_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] BRANCH_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (BRANCH_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe = BRANCH_OE; endcase @@ -130441,19 +130441,19 @@ module \dec_oe$143 (BRANCH_internal_op, BRANCH_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (BRANCH_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe_ok = 1'h1; endcase @@ -130465,7 +130465,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$147 (LOGICAL_internal_op, oe, oe_ok, LOGICAL_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input LOGICAL_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130542,37 +130542,37 @@ module \dec_oe$147 (LOGICAL_internal_op, oe, oe_ok, LOGICAL_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] LOGICAL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (LOGICAL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe = LOGICAL_OE; endcase @@ -130582,19 +130582,19 @@ module \dec_oe$147 (LOGICAL_internal_op, oe, oe_ok, LOGICAL_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (LOGICAL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe_ok = 1'h1; endcase @@ -130606,7 +130606,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$152 (SPR_internal_op, SPR_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input SPR_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130683,35 +130683,35 @@ module \dec_oe$152 (SPR_internal_op, SPR_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] SPR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (SPR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe = SPR_OE; endcase @@ -130721,19 +130721,19 @@ module \dec_oe$152 (SPR_internal_op, SPR_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (SPR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe_ok = 1'h1; endcase @@ -130745,7 +130745,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$155 (DIV_internal_op, oe, oe_ok, DIV_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input DIV_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130822,37 +130822,37 @@ module \dec_oe$155 (DIV_internal_op, oe, oe_ok, DIV_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] DIV_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (DIV_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe = DIV_OE; endcase @@ -130862,19 +130862,19 @@ module \dec_oe$155 (DIV_internal_op, oe, oe_ok, DIV_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (DIV_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe_ok = 1'h1; endcase @@ -130886,7 +130886,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$160 (MUL_internal_op, oe, oe_ok, MUL_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input MUL_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130963,37 +130963,37 @@ module \dec_oe$160 (MUL_internal_op, oe, oe_ok, MUL_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] MUL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (MUL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe = MUL_OE; endcase @@ -131003,19 +131003,19 @@ module \dec_oe$160 (MUL_internal_op, oe, oe_ok, MUL_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (MUL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe_ok = 1'h1; endcase @@ -131027,7 +131027,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$164 (SHIFT_ROT_internal_op, oe, oe_ok, SHIFT_ROT_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input SHIFT_ROT_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -131104,37 +131104,37 @@ module \dec_oe$164 (SHIFT_ROT_internal_op, oe, oe_ok, SHIFT_ROT_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] SHIFT_ROT_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (SHIFT_ROT_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe = SHIFT_ROT_OE; endcase @@ -131144,19 +131144,19 @@ module \dec_oe$164 (SHIFT_ROT_internal_op, oe, oe_ok, SHIFT_ROT_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (SHIFT_ROT_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe_ok = 1'h1; endcase @@ -131168,7 +131168,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$168 (LDST_internal_op, oe, oe_ok, LDST_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input LDST_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -131245,37 +131245,37 @@ module \dec_oe$168 (LDST_internal_op, oe, oe_ok, LDST_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] LDST_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (LDST_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe = LDST_OE; endcase @@ -131285,19 +131285,19 @@ module \dec_oe$168 (LDST_internal_op, oe, oe_ok, LDST_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (LDST_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe_ok = 1'h1; endcase @@ -131309,7 +131309,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$173 (internal_op, oe, oe_ok, OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -131386,37 +131386,37 @@ module \dec_oe$173 (internal_op, oe, oe_ok, OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:498" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe = OE; endcase @@ -131426,19 +131426,19 @@ module \dec_oe$173 (internal_op, oe, oe_ok, OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:507" *) casez (internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:518" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:522" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:524" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:525" */ 2'h2: oe_ok = 1'h1; endcase @@ -131450,35 +131450,35 @@ endmodule (* generator = "nMigen" *) module dec_rc(rc, rc_ok, ALU_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input ALU_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc = ALU_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc = 1'h0; endcase @@ -131486,18 +131486,18 @@ module dec_rc(rc, rc_ok, ALU_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc_ok = 1'h1; endcase @@ -131508,33 +131508,33 @@ endmodule (* generator = "nMigen" *) module \dec_rc$139 (CR_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input CR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc = CR_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc = 1'h0; endcase @@ -131542,18 +131542,18 @@ module \dec_rc$139 (CR_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc_ok = 1'h1; endcase @@ -131564,33 +131564,33 @@ endmodule (* generator = "nMigen" *) module \dec_rc$142 (BRANCH_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input BRANCH_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc = BRANCH_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc = 1'h0; endcase @@ -131598,18 +131598,18 @@ module \dec_rc$142 (BRANCH_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc_ok = 1'h1; endcase @@ -131620,35 +131620,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$146 (rc, rc_ok, LOGICAL_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input LOGICAL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc = LOGICAL_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc = 1'h0; endcase @@ -131656,18 +131656,18 @@ module \dec_rc$146 (rc, rc_ok, LOGICAL_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc_ok = 1'h1; endcase @@ -131678,33 +131678,33 @@ endmodule (* generator = "nMigen" *) module \dec_rc$151 (SPR_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input SPR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc = SPR_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc = 1'h0; endcase @@ -131712,18 +131712,18 @@ module \dec_rc$151 (SPR_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc_ok = 1'h1; endcase @@ -131734,35 +131734,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$154 (rc, rc_ok, DIV_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input DIV_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc = DIV_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc = 1'h0; endcase @@ -131770,18 +131770,18 @@ module \dec_rc$154 (rc, rc_ok, DIV_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc_ok = 1'h1; endcase @@ -131792,35 +131792,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$159 (rc, rc_ok, MUL_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input MUL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc = MUL_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc = 1'h0; endcase @@ -131828,18 +131828,18 @@ module \dec_rc$159 (rc, rc_ok, MUL_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc_ok = 1'h1; endcase @@ -131850,35 +131850,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$163 (rc, rc_ok, SHIFT_ROT_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input SHIFT_ROT_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc = SHIFT_ROT_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc = 1'h0; endcase @@ -131886,18 +131886,18 @@ module \dec_rc$163 (rc, rc_ok, SHIFT_ROT_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc_ok = 1'h1; endcase @@ -131908,35 +131908,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$167 (rc, rc_ok, LDST_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input LDST_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc = LDST_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc = 1'h0; endcase @@ -131944,18 +131944,18 @@ module \dec_rc$167 (rc, rc_ok, LDST_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc_ok = 1'h1; endcase @@ -131966,35 +131966,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$172 (rc, rc_ok, Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:470" *) input Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:461" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc = Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc = 1'h0; endcase @@ -132002,18 +132002,18 @@ module \dec_rc$172 (rc, rc_ok, Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:470" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:471" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:474" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:477" */ 2'h0: rc_ok = 1'h1; endcase @@ -132160,7 +132160,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, wire all_rd_pulse; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire all_rd_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] alu_div0_cr_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg [3:0] alu_div0_logical_op__data_len = 4'h0; @@ -132332,7 +132332,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, wire alu_div0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_div0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_div0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_div0_p_ready_o; @@ -132342,9 +132342,9 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, wire [63:0] alu_div0_ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] alu_div0_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] alu_div0_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire alu_div0_xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire \alu_div0_xer_so$1 ; @@ -132376,11 +132376,11 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -132448,7 +132448,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output dest4_o; reg dest4_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -132670,9 +132670,9 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, wire \src_sel$82 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; assign \$100 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_div0_logical_op__zero_a; assign \$102 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_div0_logical_op__imm_data__ok; @@ -132923,7 +132923,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -132932,7 +132932,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$64 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -132941,7 +132941,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -132950,7 +132950,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -132959,7 +132959,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -132968,7 +132968,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -132977,7 +132977,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -132986,7 +132986,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -132995,7 +132995,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$66 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 4'h0; @@ -133004,7 +133004,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 4'hf; @@ -133036,7 +133036,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \alu_div0_logical_op__insn$next , \alu_div0_logical_op__data_len$next , \alu_div0_logical_op__is_signed$next , \alu_div0_logical_op__is_32bit$next , \alu_div0_logical_op__output_carry$next , \alu_div0_logical_op__write_cr0$next , \alu_div0_logical_op__invert_out$next , \alu_div0_logical_op__input_carry$next , \alu_div0_logical_op__zero_a$next , \alu_div0_logical_op__invert_in$next , \alu_div0_logical_op__oe__ok$next , \alu_div0_logical_op__oe__oe$next , \alu_div0_logical_op__rc__ok$next , \alu_div0_logical_op__rc__rc$next , \alu_div0_logical_op__imm_data__ok$next , \alu_div0_logical_op__imm_data__data$next , \alu_div0_logical_op__fn_unit$next , \alu_div0_logical_op__insn_type$next } = { oper_i_alu_div0__insn, oper_i_alu_div0__data_len, oper_i_alu_div0__is_signed, oper_i_alu_div0__is_32bit, oper_i_alu_div0__output_carry, oper_i_alu_div0__write_cr0, oper_i_alu_div0__invert_out, oper_i_alu_div0__input_carry, oper_i_alu_div0__zero_a, oper_i_alu_div0__invert_in, oper_i_alu_div0__oe__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__rc__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__fn_unit, oper_i_alu_div0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -133065,7 +133065,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -133087,7 +133087,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -133109,7 +133109,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r2__xer_ov_ok$next , \data_r2__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__xer_ov_ok$next = 1'h0; @@ -133131,7 +133131,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r3__xer_so_ok$next = 1'h0; @@ -133170,7 +133170,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$94 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -133179,7 +133179,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$96 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -133228,7 +133228,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$20 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 4'h0; @@ -133621,9 +133621,9 @@ endmodule (* generator = "nMigen" *) module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 , issue__wen, issue__data_i, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] dest1__addr; @@ -133644,33 +133644,33 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 input issue__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input issue__wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [2:0] memory_r_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [2:0] \memory_r_addr$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [63:0] memory_r_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [63:0] \memory_r_data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [2:0] memory_w_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [2:0] \memory_w_addr$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [63:0] memory_w_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [63:0] \memory_w_data$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire memory_w_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire \memory_w_en$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg ren_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] src1__addr; @@ -133707,7 +133707,7 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 always @* begin if (\initial ) begin end \ren_delay$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 1'h0; @@ -133716,9 +133716,9 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 always @* begin if (\initial ) begin end src1__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" *) casez (ren_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" */ 1'h1: src1__data_o = memory_r_data; endcase @@ -133726,7 +133726,7 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 always @* begin if (\initial ) begin end \ren_delay$8$next = issue__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$8$next = 1'h0; @@ -133735,9 +133735,9 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 always @* begin if (\initial ) begin end issue__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" *) casez (\ren_delay$8 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" */ 1'h1: issue__data_o = \memory_r_data$4 ; endcase @@ -133756,37 +133756,37 @@ endmodule (* generator = "nMigen" *) module fsm(capture, shift, update, isir, posjtag_rst, negjtag_rst, posjtag_clk, negjtag_clk, TAP_bus__tck, TAP_bus__tms, isdr); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) wire \$11 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" *) wire \$13 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" *) wire \$15 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) wire \$17 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) wire \$19 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" *) wire \$21 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" *) wire \$23 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" *) wire \$25 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" *) wire \$27 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" *) wire \$29 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" *) wire \$31 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) - wire \$5 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) wire \$9 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tck; @@ -133794,9 +133794,9 @@ module fsm(capture, shift, update, isir, posjtag_rst, negjtag_rst, posjtag_clk, input TAP_bus__tms; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) output capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" *) reg [3:0] fsm_state = 4'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" *) reg [3:0] \fsm_state$next ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *) output isdr; @@ -133808,38 +133808,38 @@ module fsm(capture, shift, update, isir, posjtag_rst, negjtag_rst, posjtag_clk, reg isir = 1'h0; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) reg \isir$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:50" *) wire local_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" *) output negjtag_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" *) output negjtag_rst; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) output posjtag_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) output posjtag_rst; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:37" *) wire rst; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) output shift; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) output update; - assign \$9 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) 1'h0; - assign \$11 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) 1'h0; - assign \$13 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *) 1'h0; - assign \$15 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *) 1'h1; - assign \$17 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) 1'h0; - assign \$1 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" *) 1'h0; - assign \$19 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) 1'h0; - assign \$21 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *) 1'h0; - assign \$23 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *) 1'h1; - assign \$25 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *) 1'h0; - assign \$27 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *) 1'h1; - assign \$29 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *) 1'h0; - assign \$31 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *) 1'h0; - assign \$3 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) 2'h3; - assign \$5 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) 3'h5; - assign \$7 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *) 4'h8; + assign \$9 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) 1'h0; + assign \$11 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) 1'h0; + assign \$13 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" *) 1'h0; + assign \$15 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" *) 1'h1; + assign \$17 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) 1'h0; + assign \$1 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) 1'h0; + assign \$19 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) 1'h0; + assign \$21 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" *) 1'h0; + assign \$23 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" *) 1'h1; + assign \$25 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" *) 1'h0; + assign \$27 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" *) 1'h1; + assign \$29 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" *) 1'h0; + assign \$31 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" *) 1'h0; + assign \$3 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) 2'h3; + assign \$5 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *) 3'h5; + assign \$7 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" *) 4'h8; always @(posedge local_clk) fsm_state <= \fsm_state$next ; always @(posedge local_clk) @@ -133849,51 +133849,51 @@ module fsm(capture, shift, update, isir, posjtag_rst, negjtag_rst, posjtag_clk, always @* begin if (\initial ) begin end \isdr$next = isdr; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" *) casez (fsm_state) /* \nmigen.decoding = "TestLogicReset/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:54" */ 4'h0: \isdr$next = 1'h0; /* \nmigen.decoding = "RunTestIdle/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:61" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:62" */ 4'h1: \isdr$next = 1'h0; /* \nmigen.decoding = "SelectDRScan/2" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:69" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ 4'h2: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) casez (\$11 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" */ 1'h1: \isdr$next = 1'h1; endcase /* \nmigen.decoding = "SelectIRScan/4" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:75" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ 4'h4: /* empty */; /* \nmigen.decoding = "CaptureState/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:81" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" */ 4'h3: /* empty */; /* \nmigen.decoding = "ShiftState/5" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:86" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" */ 4'h5: /* empty */; /* \nmigen.decoding = "Exit1/6" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:89" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" */ 4'h6: /* empty */; /* \nmigen.decoding = "Pause/7" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:94" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" */ 4'h7: /* empty */; /* \nmigen.decoding = "Exit2/9" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:97" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" */ 4'h9: /* empty */; /* \nmigen.decoding = "UpdateState/8" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:102" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:103" */ 4'h8: \isdr$next = 1'h0; endcase @@ -133901,119 +133901,119 @@ module fsm(capture, shift, update, isir, posjtag_rst, negjtag_rst, posjtag_clk, always @* begin if (\initial ) begin end \fsm_state$next = fsm_state; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" *) casez (fsm_state) /* \nmigen.decoding = "TestLogicReset/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:54" */ 4'h0: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" *) casez (\$13 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" */ 1'h1: \fsm_state$next = 4'h1; endcase /* \nmigen.decoding = "RunTestIdle/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:61" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:62" */ 4'h1: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" *) casez (\$15 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" */ 1'h1: \fsm_state$next = 4'h2; endcase /* \nmigen.decoding = "SelectDRScan/2" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:69" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ 4'h2: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) casez (\$17 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" */ 1'h1: \fsm_state$next = 4'h3; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:73" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:74" */ default: \fsm_state$next = 4'h4; endcase /* \nmigen.decoding = "SelectIRScan/4" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:75" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ 4'h4: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) casez (\$19 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" */ 1'h1: \fsm_state$next = 4'h3; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:79" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:80" */ default: \fsm_state$next = 4'h0; endcase /* \nmigen.decoding = "CaptureState/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:81" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" */ 4'h3: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" *) casez (\$21 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" */ 1'h1: \fsm_state$next = 4'h5; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:84" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:85" */ default: \fsm_state$next = 4'h6; endcase /* \nmigen.decoding = "ShiftState/5" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:86" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" */ 4'h5: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" *) casez (\$23 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" */ 1'h1: \fsm_state$next = 4'h6; endcase /* \nmigen.decoding = "Exit1/6" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:89" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" */ 4'h6: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" *) casez (\$25 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" */ 1'h1: \fsm_state$next = 4'h7; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:92" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:93" */ default: \fsm_state$next = 4'h8; endcase /* \nmigen.decoding = "Pause/7" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:94" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" */ 4'h7: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" *) casez (\$27 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" */ 1'h1: \fsm_state$next = 4'h9; endcase /* \nmigen.decoding = "Exit2/9" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:97" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" */ 4'h9: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" *) casez (\$29 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" */ 1'h1: \fsm_state$next = 4'h5; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:100" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:101" */ default: \fsm_state$next = 4'h8; endcase /* \nmigen.decoding = "UpdateState/8" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:102" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:103" */ 4'h8: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" *) casez (\$31 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" */ 1'h1: \fsm_state$next = 4'h1; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:109" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:110" */ default: \fsm_state$next = 4'h2; endcase @@ -134022,51 +134022,51 @@ module fsm(capture, shift, update, isir, posjtag_rst, negjtag_rst, posjtag_clk, always @* begin if (\initial ) begin end \isir$next = isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" *) casez (fsm_state) /* \nmigen.decoding = "TestLogicReset/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:54" */ 4'h0: \isir$next = 1'h0; /* \nmigen.decoding = "RunTestIdle/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:61" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:62" */ 4'h1: \isir$next = 1'h0; /* \nmigen.decoding = "SelectDRScan/2" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:69" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ 4'h2: /* empty */; /* \nmigen.decoding = "SelectIRScan/4" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:75" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ 4'h4: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" */ 1'h1: \isir$next = 1'h1; endcase /* \nmigen.decoding = "CaptureState/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:81" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" */ 4'h3: /* empty */; /* \nmigen.decoding = "ShiftState/5" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:86" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" */ 4'h5: /* empty */; /* \nmigen.decoding = "Exit1/6" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:89" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" */ 4'h6: /* empty */; /* \nmigen.decoding = "Pause/7" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:94" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" */ 4'h7: /* empty */; /* \nmigen.decoding = "Exit2/9" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:97" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" */ 4'h9: /* empty */; /* \nmigen.decoding = "UpdateState/8" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:102" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:103" */ 4'h8: \isir$next = 1'h0; endcase @@ -134085,21 +134085,21 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus" *) (* generator = "nMigen" *) module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src2_i$79 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$80 , \cu_wr__rel_o$81 , \cu_wr__go_i$82 , \o_ok$83 , \cu_wr__rel_o$84 , \cu_wr__go_i$85 , \o_ok$86 , \cu_wr__rel_o$87 , \cu_wr__go_i$88 , \o_ok$89 , \cu_wr__rel_o$90 , \cu_wr__go_i$91 , \o_ok$92 , \cu_wr__rel_o$93 , \cu_wr__go_i$94 , \o_ok$95 , \cu_wr__rel_o$96 , \cu_wr__go_i$97 , \o_ok$98 , \cu_wr__rel_o$99 , \cu_wr__go_i$100 , \cu_wr__rel_o$101 , \cu_wr__go_i$102 , dest1_o, \dest1_o$103 , \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$110 , \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \dest2_o$115 , dest3_o, \dest2_o$116 , \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , xer_ca_ok, \xer_ca_ok$120 , \xer_ca_ok$121 , \dest3_o$122 , dest6_o, \dest3_o$123 , xer_ov_ok, \xer_ov_ok$124 , \xer_ov_ok$125 , \xer_ov_ok$126 , dest4_o, dest5_o, \dest3_o$127 , \dest3_o$128 , xer_so_ok, \xer_so_ok$129 , \xer_so_ok$130 , \xer_so_ok$131 , \dest5_o$132 , \dest4_o$133 , \dest4_o$134 , \dest4_o$135 , fast1_ok, \cu_wr__rel_o$136 , \cu_wr__go_i$137 , \fast1_ok$138 , \fast1_ok$139 , fast2_ok, \fast2_ok$140 , \dest1_o$141 , \dest2_o$142 , \dest3_o$143 , \dest2_o$144 , \dest3_o$145 , nia_ok, \nia_ok$146 , \dest3_o$147 , \dest4_o$148 , msr_ok, \dest5_o$149 , spr1_ok, \dest2_o$150 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$151 , \ldst_port0_exc_$signal$152 , \ldst_port0_exc_$signal$153 , \ldst_port0_exc_$signal$154 , \ldst_port0_exc_$signal$155 , \ldst_port0_exc_$signal$156 , \ldst_port0_exc_$signal$157 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \cr_a_ok$110 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \cr_a_ok$111 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \cr_a_ok$112 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \cr_a_ok$113 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \cr_a_ok$114 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) input cu_ad__go_i; @@ -134319,23 +134319,23 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o output [63:0] \dest5_o$149 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [1:0] dest6_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \fast1_ok$138 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \fast1_ok$139 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \fast2_ok$140 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output full_cr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [95:0] ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output ldst_port0_addr_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) input ldst_port0_addr_ok_o; @@ -134343,57 +134343,57 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o input ldst_port0_busy_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) output [3:0] ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$151 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$153 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$154 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$155 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$156 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$157 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) output ldst_port0_is_ld_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) output ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output ldst_port0_st_data_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output msr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \nia_ok$146 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$98 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) input [3:0] oper_i_alu_alu0__data_len; @@ -135562,7 +135562,7 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o input oper_i_ldst_ldst0__sign_extend; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) input oper_i_ldst_ldst0__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spr1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [63:0] src1_i; @@ -135644,27 +135644,27 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o input [1:0] src6_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [3:0] \src6_i$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_ca_ok$120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_ca_ok$121 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_ov_ok$124 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_ov_ok$125 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_ov_ok$126 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so_ok$129 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so_ok$130 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so_ok$131 ; alu0 alu0 ( .coresync_clk(coresync_clk), @@ -136040,66 +136040,66 @@ endmodule (* generator = "nMigen" *) module idblock(id_bypass, capture, shift, update, TAP_bus__tdi, TAP_id_tdo, posjtag_rst, posjtag_clk, select_id); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:389" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:390" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" *) wire \$5 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tdi; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" *) reg [31:0] TAP_id_sr = 32'd0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" *) reg [31:0] \TAP_id_sr$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:230" *) output TAP_id_tdo; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:248" *) wire _bypass; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:245" *) wire _capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:246" *) wire _shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:244" *) wire _tdi; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:247" *) wire _update; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) input capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:381" *) input id_bypass; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) input posjtag_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) input posjtag_rst; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" *) input select_id; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) input shift; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) input update; - assign \$1 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) capture; - assign \$3 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) shift; - assign \$5 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" *) update; + assign \$1 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:389" *) capture; + assign \$3 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:390" *) shift; + assign \$5 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" *) update; always @(posedge posjtag_clk) TAP_id_sr <= \TAP_id_sr$next ; always @* begin if (\initial ) begin end \TAP_id_sr$next = TAP_id_sr; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:259" *) casez ({ _shift, _capture }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:259" */ 2'b?1: \TAP_id_sr$next = 32'd6399; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:256" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:261" */ 2'b1?: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:262" *) casez (_bypass) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:262" */ 1'h1: \TAP_id_sr$next [0] = _tdi; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:259" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:264" */ default: \TAP_id_sr$next = { _tdi, TAP_id_sr[31:1] }; endcase @@ -136133,9 +136133,9 @@ module idx_l(coresync_rst, q_idx_l, s_idx_l, r_idx_l, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_idx_l; @@ -136164,7 +136164,7 @@ module idx_l(coresync_rst, q_idx_l, s_idx_l, r_idx_l, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -136239,7 +136239,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en wire a_stall_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *) input a_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *) reg [44:0] f_badaddr_o = 45'h000000000000; @@ -136289,7 +136289,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en reg [63:0] ibus_rdata = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *) reg [63:0] \ibus_rdata$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) input wb_icache_en; @@ -136355,7 +136355,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__cyc$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ibus__cyc$next = 1'h0; @@ -136383,7 +136383,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__stb$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ibus__stb$next = 1'h0; @@ -136411,7 +136411,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__sel$next = 8'hff; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ibus__sel$next = 8'h00; @@ -136436,7 +136436,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ibus_rdata$next = 64'h0000000000000000; @@ -136459,7 +136459,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__adr$next = a_pc_i[47:3]; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ibus__adr$next = 45'h000000000000; @@ -136482,7 +136482,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \f_fetch_err_o$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \f_fetch_err_o$next = 1'h0; @@ -136502,7 +136502,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \f_badaddr_o$next = ibus__adr; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \f_badaddr_o$next = 45'h000000000000; @@ -138105,9 +138105,9 @@ endmodule (* generator = "nMigen" *) module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [4:0] dest1__addr; @@ -138122,27 +138122,27 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ reg [63:0] dmi__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input dmi__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [4:0] memory_r_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [4:0] \memory_r_addr$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [63:0] memory_r_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [63:0] \memory_r_data$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [4:0] memory_w_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [63:0] memory_w_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire memory_w_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg ren_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$4 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [4:0] src1__addr; @@ -138202,7 +138202,7 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ always @* begin if (\initial ) begin end \ren_delay$next = dmi__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 1'h0; @@ -138211,9 +138211,9 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ always @* begin if (\initial ) begin end dmi__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" *) casez (ren_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" */ 1'h1: dmi__data_o = memory_r_data; endcase @@ -138221,7 +138221,7 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ always @* begin if (\initial ) begin end \ren_delay$4$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$4$next = 1'h0; @@ -138230,9 +138230,9 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ always @* begin if (\initial ) begin end src1__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" *) casez (\ren_delay$4 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" */ 1'h1: src1__data_o = \memory_r_data$3 ; endcase @@ -138248,49 +138248,49 @@ endmodule (* generator = "nMigen" *) module irblock(capture, shift, update, TAP_bus__tdi, isir, tdo, posjtag_rst, posjtag_clk, ir); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:372" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) wire \$11 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:372" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" *) wire \$9 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tdi; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) input capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" *) output [3:0] ir; reg [3:0] ir = 4'h1; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" *) reg [3:0] \ir$next ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) input isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) input posjtag_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) input posjtag_rst; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) input shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:140" *) reg [3:0] shift_ir = 4'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:140" *) reg [3:0] \shift_ir$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:130" *) output tdo; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) input update; - assign \$9 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) shift; - assign \$11 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) update; - assign \$1 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) capture; - assign \$3 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) shift; - assign \$5 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) update; - assign \$7 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) capture; + assign \$9 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" *) shift; + assign \$11 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) update; + assign \$1 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:372" *) capture; + assign \$3 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" *) shift; + assign \$5 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) update; + assign \$7 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:372" *) capture; always @(posedge posjtag_clk) ir <= \ir$next ; always @(posedge posjtag_clk) @@ -138298,12 +138298,12 @@ module irblock(capture, shift, update, TAP_bus__tdi, isir, tdo, posjtag_rst, pos always @* begin if (\initial ) begin end \shift_ir$next = shift_ir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" *) casez ({ \$5 , \$3 , \$1 }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" */ 3'b??1: \shift_ir$next = ir; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:145" */ 3'b?1?: \shift_ir$next = { TAP_bus__tdi, shift_ir[3:1] }; endcase @@ -138311,19 +138311,19 @@ module irblock(capture, shift, update, TAP_bus__tdi, isir, tdo, posjtag_rst, pos always @* begin if (\initial ) begin end \ir$next = ir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" *) casez ({ \$11 , \$9 , \$7 }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" */ 3'b??1: /* empty */; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:145" */ 3'b?1?: /* empty */; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:145" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:147" */ 3'b1??: \ir$next = shift_ir; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \ir$next = 4'h1; @@ -138334,491 +138334,491 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.jtag" *) (* generator = "nMigen" *) -module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0__dout, rst, wb_dcache_en, wb_icache_en, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__cyc, jtag_wb__we, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, clk); +module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0__dout, rst, wb_dcache_en, wb_icache_en, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$101 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$103 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$105 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$107 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$109 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$11 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$111 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$113 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$115 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$117 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$119 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$121 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$123 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$125 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$127 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$129 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$13 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$131 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$133 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$135 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$137 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$139 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$141 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$143 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$145 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$147 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$149 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$15 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$151 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$153 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$155 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$157 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$159 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$161 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$163 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$165 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$167 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$169 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:406" *) wire \$17 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$171 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$173 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$175 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$177 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$179 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$181 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$183 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$185 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$187 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$189 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$19 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$191 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$193 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$195 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$197 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$199 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$201 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$203 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$205 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$207 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$209 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$21 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$211 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$213 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$215 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$217 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$219 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$221 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$223 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$225 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$227 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$229 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$23 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$231 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$233 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$235 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$237 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$239 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$241 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$243 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$245 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$247 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$249 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) wire \$25 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$251 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$253 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$255 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$257 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$259 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$261 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$263 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$265 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$267 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$269 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) wire \$27 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$271 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$273 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$275 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$277 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$279 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$281 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$283 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$285 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$287 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$289 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) wire \$29 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$291 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$293 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$295 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$297 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$299 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$301 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$303 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) wire \$305 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) wire \$307 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) wire \$309 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:408" *) wire \$31 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$311 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$313 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$315 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) wire \$317 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) wire \$319 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) wire \$321 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) wire \$323 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$325 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$327 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$329 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$33 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$331 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$333 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$335 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$337 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$339 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) wire \$341 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$343 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$345 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$347 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$349 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$35 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$351 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$353 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$355 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$357 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) wire \$359 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) wire \$361 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$363 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$365 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$367 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$369 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) wire \$37 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$371 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$373 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$375 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$377 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) wire \$379 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$381 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$383 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$385 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$387 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$389 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) wire \$39 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$391 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$393 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$395 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) wire \$397 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) wire \$399 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$401 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$403 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$405 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$407 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$409 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) wire \$41 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$411 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$413 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$415 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) wire \$417 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$419 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) wire \$421 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$423 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) wire \$425 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$427 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) wire \$429 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) wire \$43 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$431 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) wire \$433 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) wire \$435 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) wire \$437 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) wire \$439 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) wire \$441 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) wire \$443 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:798" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:808" *) wire \$445 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:798" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:808" *) wire \$447 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:800" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:809" *) wire \$449 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:409" *) wire \$45 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:800" *) - wire \$450 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:801" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:810" *) + wire \$451 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:810" *) wire \$453 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:802" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:811" *) wire \$455 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:802" *) - wire \$457 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:811" *) + wire \$456 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:770" *) wire [30:0] \$459 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:770" *) wire [30:0] \$460 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:795" *) wire [30:0] \$462 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:795" *) wire [30:0] \$463 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) wire [7:0] \$465 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) wire \$468 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:410" *) wire \$47 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) wire \$470 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) wire \$472 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:531" *) wire \$474 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:500" *) wire [4:0] \$476 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:500" *) wire [4:0] \$477 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:525" *) wire [4:0] \$479 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:525" *) wire [4:0] \$480 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:411" *) wire \$49 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$51 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$53 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$55 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) wire \$57 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) wire \$59 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$61 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$63 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$65 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$67 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$69 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$71 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$73 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$75 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$77 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$79 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$81 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$83 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$85 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$87 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$89 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$91 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$93 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) wire \$95 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) wire \$97 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) wire \$99 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tck; @@ -138829,9 +138829,9 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ reg TAP_bus__tdo; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tms; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:420" *) reg TAP_tdo; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input clk; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) input dmi0__ack_o; @@ -138851,63 +138851,63 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ output dmi0__req_i; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) output dmi0__we_i; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:477" *) wire [7:0] dmi0_addrsr__i; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:477" *) wire [7:0] dmi0_addrsr__o; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:477" *) reg dmi0_addrsr__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:477" *) reg \dmi0_addrsr__oe$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) wire dmi0_addrsr_capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) wire dmi0_addrsr_isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [7:0] dmi0_addrsr_reg = 8'h00; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [7:0] \dmi0_addrsr_reg$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) wire dmi0_addrsr_shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) wire dmi0_addrsr_update; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg dmi0_addrsr_update_core = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg \dmi0_addrsr_update_core$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg dmi0_addrsr_update_core_prev = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg \dmi0_addrsr_update_core_prev$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:479" *) reg [63:0] dmi0_datasr__i = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:479" *) reg [63:0] \dmi0_datasr__i$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:479" *) wire [63:0] dmi0_datasr__o; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:479" *) reg [1:0] dmi0_datasr__oe = 2'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:479" *) reg [1:0] \dmi0_datasr__oe$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) wire dmi0_datasr_capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) wire [1:0] dmi0_datasr_isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [63:0] dmi0_datasr_reg = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [63:0] \dmi0_datasr_reg$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) wire dmi0_datasr_shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) wire dmi0_datasr_update; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg dmi0_datasr_update_core = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg \dmi0_datasr_update_core$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg dmi0_datasr_update_core_prev = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg \dmi0_datasr_update_core_prev$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output eint_0__core__i; @@ -138929,13 +138929,13 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ wire fsm_isir; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) wire fsm_shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) reg [2:0] fsm_state = 3'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) reg [2:0] \fsm_state$467 = 3'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) reg [2:0] \fsm_state$467$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) reg [2:0] \fsm_state$next ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) wire fsm_update; @@ -139131,113 +139131,113 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ output gpio_s7__pad__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output gpio_s7__pad__oe; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:230" *) wire idblock_TAP_id_tdo; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:381" *) wire idblock_id_bypass; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" *) wire idblock_select_id; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:556" *) reg [129:0] io_bd = 130'h000000000000000000000000000000000; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:556" *) reg [129:0] \io_bd$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:401" *) wire io_bd2core; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" *) wire io_bd2io; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) wire io_capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) wire io_shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:555" *) reg [129:0] io_sr = 130'h000000000000000000000000000000000; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:555" *) reg [129:0] \io_sr$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:399" *) wire io_update; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" *) wire [3:0] irblock_ir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:130" *) wire irblock_tdo; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) input jtag_wb__ack; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output [29:0] jtag_wb__adr; reg [29:0] jtag_wb__adr = 30'h00000000; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) reg [29:0] \jtag_wb__adr$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__cyc; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) input [31:0] jtag_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output [31:0] jtag_wb__dat_w; reg [31:0] jtag_wb__dat_w = 32'd0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) reg [31:0] \jtag_wb__dat_w$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output [3:0] jtag_wb__sel; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__stb; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__we; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) wire [29:0] jtag_wb_addrsr__i; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) wire [29:0] jtag_wb_addrsr__o; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) reg jtag_wb_addrsr__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) reg \jtag_wb_addrsr__oe$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) wire jtag_wb_addrsr_capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) wire jtag_wb_addrsr_isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [29:0] jtag_wb_addrsr_reg = 30'h00000000; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [29:0] \jtag_wb_addrsr_reg$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) wire jtag_wb_addrsr_shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) wire jtag_wb_addrsr_update; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg jtag_wb_addrsr_update_core = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg \jtag_wb_addrsr_update_core$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg jtag_wb_addrsr_update_core_prev = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg \jtag_wb_addrsr_update_core_prev$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:744" *) reg [31:0] jtag_wb_datasr__i = 32'd0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:744" *) reg [31:0] \jtag_wb_datasr__i$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:744" *) wire [31:0] jtag_wb_datasr__o; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:744" *) reg [1:0] jtag_wb_datasr__oe = 2'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:744" *) reg [1:0] \jtag_wb_datasr__oe$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) wire jtag_wb_datasr_capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) wire [1:0] jtag_wb_datasr_isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [31:0] jtag_wb_datasr_reg = 32'd0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [31:0] \jtag_wb_datasr_reg$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) wire jtag_wb_datasr_shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) wire jtag_wb_datasr_update; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg jtag_wb_datasr_update_core = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg \jtag_wb_datasr_update_core$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg jtag_wb_datasr_update_core_prev = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg \jtag_wb_datasr_update_core_prev$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input mspi0_clk__core__o; @@ -139271,15 +139271,15 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ output mtwi_sda__pad__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output mtwi_sda__pad__oe; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" *) wire negjtag_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" *) wire negjtag_rst; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) wire posjtag_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) wire posjtag_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -139573,25 +139573,25 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ reg sr0__oe = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *) reg \sr0__oe$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) wire sr0_capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) wire sr0_isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [2:0] sr0_reg = 3'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [2:0] \sr0_reg$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) wire sr0_shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) wire sr0_update; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg sr0_update_core = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg \sr0_update_core$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg sr0_update_core_prev = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg \sr0_update_core_prev$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) reg [2:0] sr5__i; @@ -139603,25 +139603,25 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ reg sr5__oe = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) reg \sr5__oe$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) wire sr5_capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) wire sr5_isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [2:0] sr5_reg = 3'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) reg [2:0] \sr5_reg$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) wire sr5_shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) wire sr5_update; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg sr5_update_core = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) reg \sr5_update_core$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg sr5_update_core_prev = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) reg \sr5_update_core_prev$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) output wb_dcache_en; @@ -139637,244 +139637,244 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ reg wb_sram_en = 1'h1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) reg \wb_sram_en$next ; - assign \$9 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" *) 4'hf; - assign \$99 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[24] : sdr_dq_6__core__o; - assign \$101 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[25] : sdr_dq_6__core__oe; - assign \$103 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[26] : sdr_dq_7__pad__i; - assign \$105 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[27] : sdr_dq_7__core__o; - assign \$107 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[28] : sdr_dq_7__core__oe; - assign \$109 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[29] : sdr_a_0__core__o; - assign \$111 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[30] : sdr_a_1__core__o; - assign \$113 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[31] : sdr_a_2__core__o; - assign \$115 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[32] : sdr_a_3__core__o; - assign \$117 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[33] : sdr_a_4__core__o; - assign \$11 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; - assign \$119 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[34] : sdr_a_5__core__o; - assign \$121 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[35] : sdr_a_6__core__o; - assign \$123 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[36] : sdr_a_7__core__o; - assign \$125 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[37] : sdr_a_8__core__o; - assign \$127 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[38] : sdr_a_9__core__o; - assign \$129 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[39] : sdr_ba_0__core__o; - assign \$131 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[40] : sdr_ba_1__core__o; - assign \$133 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[41] : sdr_clock__core__o; - assign \$135 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[42] : sdr_cke__core__o; - assign \$137 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[43] : sdr_ras_n__core__o; - assign \$13 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; - assign \$139 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[44] : sdr_cas_n__core__o; - assign \$141 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[45] : sdr_we_n__core__o; - assign \$143 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[46] : sdr_cs_n__core__o; - assign \$145 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[47] : sdr_a_10__core__o; - assign \$147 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[48] : sdr_a_11__core__o; - assign \$149 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[49] : sdr_a_12__core__o; - assign \$151 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[50] : sdr_dm_1__core__o; - assign \$153 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[51] : sdr_dq_8__pad__i; - assign \$155 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[52] : sdr_dq_8__core__o; - assign \$157 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[53] : sdr_dq_8__core__oe; - assign \$15 = \$11 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) \$13 ; - assign \$159 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[54] : sdr_dq_9__pad__i; - assign \$161 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[55] : sdr_dq_9__core__o; - assign \$163 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[56] : sdr_dq_9__core__oe; - assign \$165 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[57] : sdr_dq_10__pad__i; - assign \$167 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[58] : sdr_dq_10__core__o; - assign \$169 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[59] : sdr_dq_10__core__oe; - assign \$171 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[60] : sdr_dq_11__pad__i; - assign \$173 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[61] : sdr_dq_11__core__o; - assign \$175 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[62] : sdr_dq_11__core__oe; - assign \$177 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[63] : sdr_dq_12__pad__i; - assign \$17 = \$15 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" *) fsm_capture; - assign \$179 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[64] : sdr_dq_12__core__o; - assign \$181 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[65] : sdr_dq_12__core__oe; - assign \$183 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[66] : sdr_dq_13__pad__i; - assign \$185 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[67] : sdr_dq_13__core__o; - assign \$187 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[68] : sdr_dq_13__core__oe; - assign \$189 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[69] : sdr_dq_14__pad__i; - assign \$191 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[70] : sdr_dq_14__core__o; - assign \$193 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[71] : sdr_dq_14__core__oe; - assign \$195 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[72] : sdr_dq_15__pad__i; - assign \$197 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[73] : sdr_dq_15__core__o; - assign \$1 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) 1'h1; - assign \$19 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; - assign \$199 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[74] : sdr_dq_15__core__oe; - assign \$201 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[75] : gpio_e8__pad__i; - assign \$203 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[76] : gpio_e8__core__o; - assign \$205 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[77] : gpio_e8__core__oe; - assign \$207 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[78] : gpio_e9__pad__i; - assign \$209 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[79] : gpio_e9__core__o; - assign \$211 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[80] : gpio_e9__core__oe; - assign \$213 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[81] : gpio_e10__pad__i; - assign \$215 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[82] : gpio_e10__core__o; - assign \$217 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[83] : gpio_e10__core__oe; - assign \$21 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; - assign \$219 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[84] : gpio_e11__pad__i; - assign \$221 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[85] : gpio_e11__core__o; - assign \$223 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[86] : gpio_e11__core__oe; - assign \$225 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[87] : gpio_e12__pad__i; - assign \$227 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[88] : gpio_e12__core__o; - assign \$229 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[89] : gpio_e12__core__oe; - assign \$231 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[90] : gpio_e13__pad__i; - assign \$233 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[91] : gpio_e13__core__o; - assign \$235 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[92] : gpio_e13__core__oe; - assign \$237 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[93] : gpio_e14__pad__i; - assign \$23 = \$19 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) \$21 ; - assign \$239 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[94] : gpio_e14__core__o; - assign \$241 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[95] : gpio_e14__core__oe; - assign \$243 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[96] : gpio_e15__pad__i; - assign \$245 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[97] : gpio_e15__core__o; - assign \$247 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[98] : gpio_e15__core__oe; - assign \$249 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[99] : gpio_s0__pad__i; - assign \$251 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[100] : gpio_s0__core__o; - assign \$253 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[101] : gpio_s0__core__oe; - assign \$255 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[102] : gpio_s1__pad__i; - assign \$257 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[103] : gpio_s1__core__o; - assign \$25 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2; - assign \$259 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[104] : gpio_s1__core__oe; - assign \$261 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[105] : gpio_s2__pad__i; - assign \$263 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[106] : gpio_s2__core__o; - assign \$265 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[107] : gpio_s2__core__oe; - assign \$267 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[108] : gpio_s3__pad__i; - assign \$269 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[109] : gpio_s3__core__o; - assign \$271 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[110] : gpio_s3__core__oe; - assign \$273 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[111] : gpio_s4__pad__i; - assign \$275 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[112] : gpio_s4__core__o; - assign \$277 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[113] : gpio_s4__core__oe; - assign \$27 = \$23 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$25 ; - assign \$279 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[114] : gpio_s5__pad__i; - assign \$281 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[115] : gpio_s5__core__o; - assign \$283 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[116] : gpio_s5__core__oe; - assign \$285 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[117] : gpio_s6__pad__i; - assign \$287 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[118] : gpio_s6__core__o; - assign \$289 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[119] : gpio_s6__core__oe; - assign \$291 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[120] : gpio_s7__pad__i; - assign \$293 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[121] : gpio_s7__core__o; - assign \$295 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[122] : gpio_s7__core__oe; - assign \$297 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[123] : mtwi_sda__pad__i; - assign \$29 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$27 ; - assign \$299 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[124] : mtwi_sda__core__o; - assign \$301 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[125] : mtwi_sda__core__oe; - assign \$303 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[126] : mtwi_scl__core__o; - assign \$305 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[127] : eint_0__pad__i; - assign \$307 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[128] : eint_1__pad__i; - assign \$309 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[129] : eint_2__pad__i; - assign \$311 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; - assign \$313 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; - assign \$315 = \$311 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) \$313 ; - assign \$317 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2; - assign \$31 = \$29 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) fsm_shift; - assign \$319 = \$315 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$317 ; - assign \$321 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$319 ; - assign \$323 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h4; - assign \$325 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$327 = \$325 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; - assign \$329 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$331 = \$329 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; - assign \$333 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$335 = \$333 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; - assign \$337 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) sr0_update_core; - assign \$33 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; - assign \$339 = sr0_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$337 ; - assign \$341 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h5; - assign \$343 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$345 = \$343 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; - assign \$347 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$349 = \$347 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; - assign \$351 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$353 = \$351 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; - assign \$355 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) jtag_wb_addrsr_update_core; - assign \$357 = jtag_wb_addrsr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$355 ; - assign \$35 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; - assign \$359 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h6; - assign \$361 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h7; - assign \$363 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$365 = \$363 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; - assign \$367 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$369 = \$367 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; - assign \$371 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$373 = \$371 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; - assign \$375 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) jtag_wb_datasr_update_core; - assign \$377 = jtag_wb_datasr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$375 ; - assign \$37 = \$33 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) \$35 ; - assign \$379 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'h8; - assign \$381 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$383 = \$381 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; - assign \$385 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$387 = \$385 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; - assign \$389 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$391 = \$389 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; - assign \$393 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) dmi0_addrsr_update_core; - assign \$395 = dmi0_addrsr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$393 ; - assign \$397 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'h9; - assign \$3 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) 4'hf; - assign \$39 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2; - assign \$399 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'ha; - assign \$401 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$403 = \$401 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; - assign \$405 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$407 = \$405 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; - assign \$409 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$411 = \$409 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; - assign \$413 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) dmi0_datasr_update_core; - assign \$415 = dmi0_datasr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$413 ; - assign \$417 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'hb; - assign \$41 = \$37 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$39 ; - assign \$419 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$421 = \$419 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; - assign \$423 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$425 = \$423 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; - assign \$427 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$429 = \$427 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; - assign \$431 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) sr5_update_core; - assign \$433 = sr5_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$431 ; - assign \$435 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) 1'h1; - assign \$437 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) 2'h2; - assign \$43 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$41 ; - assign \$439 = \$435 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) \$437 ; - assign \$441 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) 2'h3; - assign \$443 = \$439 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) \$441 ; - assign \$445 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:798" *) 3'h4; - assign \$447 = \$443 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:798" *) \$445 ; - assign \$450 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:800" *) 1'h0; - assign \$449 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:800" *) \$450 ; - assign \$453 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:801" *) 2'h2; - assign \$455 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:802" *) 3'h4; - assign \$457 = \$453 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:802" *) \$455 ; - assign \$45 = \$43 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) fsm_update; - assign \$460 = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" *) 1'h1; - assign \$463 = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" *) 1'h1; + assign \$9 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) 4'hf; + assign \$99 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[24] : sdr_dq_6__core__o; + assign \$101 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[25] : sdr_dq_6__core__oe; + assign \$103 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[26] : sdr_dq_7__pad__i; + assign \$105 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[27] : sdr_dq_7__core__o; + assign \$107 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[28] : sdr_dq_7__core__oe; + assign \$109 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[29] : sdr_a_0__core__o; + assign \$111 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[30] : sdr_a_1__core__o; + assign \$113 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[31] : sdr_a_2__core__o; + assign \$115 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[32] : sdr_a_3__core__o; + assign \$117 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[33] : sdr_a_4__core__o; + assign \$11 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 1'h0; + assign \$119 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[34] : sdr_a_5__core__o; + assign \$121 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[35] : sdr_a_6__core__o; + assign \$123 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[36] : sdr_a_7__core__o; + assign \$125 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[37] : sdr_a_8__core__o; + assign \$127 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[38] : sdr_a_9__core__o; + assign \$129 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[39] : sdr_ba_0__core__o; + assign \$131 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[40] : sdr_ba_1__core__o; + assign \$133 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[41] : sdr_clock__core__o; + assign \$135 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[42] : sdr_cke__core__o; + assign \$137 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[43] : sdr_ras_n__core__o; + assign \$13 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 2'h2; + assign \$139 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[44] : sdr_cas_n__core__o; + assign \$141 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[45] : sdr_we_n__core__o; + assign \$143 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[46] : sdr_cs_n__core__o; + assign \$145 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[47] : sdr_a_10__core__o; + assign \$147 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[48] : sdr_a_11__core__o; + assign \$149 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[49] : sdr_a_12__core__o; + assign \$151 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[50] : sdr_dm_1__core__o; + assign \$153 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[51] : sdr_dq_8__pad__i; + assign \$155 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[52] : sdr_dq_8__core__o; + assign \$157 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[53] : sdr_dq_8__core__oe; + assign \$15 = \$11 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) \$13 ; + assign \$159 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[54] : sdr_dq_9__pad__i; + assign \$161 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[55] : sdr_dq_9__core__o; + assign \$163 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[56] : sdr_dq_9__core__oe; + assign \$165 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[57] : sdr_dq_10__pad__i; + assign \$167 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[58] : sdr_dq_10__core__o; + assign \$169 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[59] : sdr_dq_10__core__oe; + assign \$171 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[60] : sdr_dq_11__pad__i; + assign \$173 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[61] : sdr_dq_11__core__o; + assign \$175 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[62] : sdr_dq_11__core__oe; + assign \$177 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[63] : sdr_dq_12__pad__i; + assign \$17 = \$15 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:406" *) fsm_capture; + assign \$179 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[64] : sdr_dq_12__core__o; + assign \$181 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[65] : sdr_dq_12__core__oe; + assign \$183 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[66] : sdr_dq_13__pad__i; + assign \$185 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[67] : sdr_dq_13__core__o; + assign \$187 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[68] : sdr_dq_13__core__oe; + assign \$189 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[69] : sdr_dq_14__pad__i; + assign \$191 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[70] : sdr_dq_14__core__o; + assign \$193 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[71] : sdr_dq_14__core__oe; + assign \$195 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[72] : sdr_dq_15__pad__i; + assign \$197 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[73] : sdr_dq_15__core__o; + assign \$1 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) 1'h1; + assign \$19 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 1'h0; + assign \$199 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[74] : sdr_dq_15__core__oe; + assign \$201 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[75] : gpio_e8__pad__i; + assign \$203 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[76] : gpio_e8__core__o; + assign \$205 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[77] : gpio_e8__core__oe; + assign \$207 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[78] : gpio_e9__pad__i; + assign \$209 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[79] : gpio_e9__core__o; + assign \$211 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[80] : gpio_e9__core__oe; + assign \$213 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[81] : gpio_e10__pad__i; + assign \$215 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[82] : gpio_e10__core__o; + assign \$217 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[83] : gpio_e10__core__oe; + assign \$21 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 2'h2; + assign \$219 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[84] : gpio_e11__pad__i; + assign \$221 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[85] : gpio_e11__core__o; + assign \$223 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[86] : gpio_e11__core__oe; + assign \$225 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[87] : gpio_e12__pad__i; + assign \$227 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[88] : gpio_e12__core__o; + assign \$229 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[89] : gpio_e12__core__oe; + assign \$231 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[90] : gpio_e13__pad__i; + assign \$233 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[91] : gpio_e13__core__o; + assign \$235 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[92] : gpio_e13__core__oe; + assign \$237 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[93] : gpio_e14__pad__i; + assign \$23 = \$19 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) \$21 ; + assign \$239 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[94] : gpio_e14__core__o; + assign \$241 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[95] : gpio_e14__core__oe; + assign \$243 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[96] : gpio_e15__pad__i; + assign \$245 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[97] : gpio_e15__core__o; + assign \$247 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[98] : gpio_e15__core__oe; + assign \$249 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[99] : gpio_s0__pad__i; + assign \$251 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[100] : gpio_s0__core__o; + assign \$253 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[101] : gpio_s0__core__oe; + assign \$255 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[102] : gpio_s1__pad__i; + assign \$257 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[103] : gpio_s1__core__o; + assign \$25 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) 2'h2; + assign \$259 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[104] : gpio_s1__core__oe; + assign \$261 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[105] : gpio_s2__pad__i; + assign \$263 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[106] : gpio_s2__core__o; + assign \$265 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[107] : gpio_s2__core__oe; + assign \$267 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[108] : gpio_s3__pad__i; + assign \$269 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[109] : gpio_s3__core__o; + assign \$271 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[110] : gpio_s3__core__oe; + assign \$273 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[111] : gpio_s4__pad__i; + assign \$275 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[112] : gpio_s4__core__o; + assign \$277 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[113] : gpio_s4__core__oe; + assign \$27 = \$23 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$25 ; + assign \$279 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[114] : gpio_s5__pad__i; + assign \$281 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[115] : gpio_s5__core__o; + assign \$283 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[116] : gpio_s5__core__oe; + assign \$285 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[117] : gpio_s6__pad__i; + assign \$287 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[118] : gpio_s6__core__o; + assign \$289 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[119] : gpio_s6__core__oe; + assign \$291 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[120] : gpio_s7__pad__i; + assign \$293 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[121] : gpio_s7__core__o; + assign \$295 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[122] : gpio_s7__core__oe; + assign \$297 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[123] : mtwi_sda__pad__i; + assign \$29 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$27 ; + assign \$299 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[124] : mtwi_sda__core__o; + assign \$301 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[125] : mtwi_sda__core__oe; + assign \$303 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[126] : mtwi_scl__core__o; + assign \$305 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) io_bd[127] : eint_0__pad__i; + assign \$307 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) io_bd[128] : eint_1__pad__i; + assign \$309 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) io_bd[129] : eint_2__pad__i; + assign \$311 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 1'h0; + assign \$313 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 2'h2; + assign \$315 = \$311 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) \$313 ; + assign \$317 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) 2'h2; + assign \$31 = \$29 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:408" *) fsm_shift; + assign \$319 = \$315 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$317 ; + assign \$321 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$319 ; + assign \$323 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 3'h4; + assign \$325 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$327 = \$325 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$329 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$331 = \$329 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$333 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$335 = \$333 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$337 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) sr0_update_core; + assign \$33 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 1'h0; + assign \$339 = sr0_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$337 ; + assign \$341 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 3'h5; + assign \$343 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$345 = \$343 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$347 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$349 = \$347 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$351 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$353 = \$351 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$355 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) jtag_wb_addrsr_update_core; + assign \$357 = jtag_wb_addrsr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$355 ; + assign \$35 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 2'h2; + assign \$359 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 3'h6; + assign \$361 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 3'h7; + assign \$363 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$365 = \$363 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$367 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$369 = \$367 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$371 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$373 = \$371 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$375 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) jtag_wb_datasr_update_core; + assign \$377 = jtag_wb_datasr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$375 ; + assign \$37 = \$33 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) \$35 ; + assign \$379 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 4'h8; + assign \$381 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$383 = \$381 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$385 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$387 = \$385 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$389 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$391 = \$389 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$393 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) dmi0_addrsr_update_core; + assign \$395 = dmi0_addrsr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$393 ; + assign \$397 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 4'h9; + assign \$3 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) 4'hf; + assign \$39 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) 2'h2; + assign \$399 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 4'ha; + assign \$401 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$403 = \$401 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$405 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$407 = \$405 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$409 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$411 = \$409 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$413 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) dmi0_datasr_update_core; + assign \$415 = dmi0_datasr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$413 ; + assign \$417 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 4'hb; + assign \$41 = \$37 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$39 ; + assign \$419 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$421 = \$419 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$423 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$425 = \$423 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$427 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$429 = \$427 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$431 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) sr5_update_core; + assign \$433 = sr5_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$431 ; + assign \$435 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) 1'h1; + assign \$437 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) 2'h2; + assign \$43 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$41 ; + assign \$439 = \$435 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) \$437 ; + assign \$441 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) 2'h3; + assign \$443 = \$439 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) \$441 ; + assign \$445 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:808" *) 3'h4; + assign \$447 = \$443 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:808" *) \$445 ; + assign \$449 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:809" *) 2'h2; + assign \$451 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:810" *) 3'h4; + assign \$453 = \$449 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:810" *) \$451 ; + assign \$456 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:811" *) 1'h0; + assign \$455 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:811" *) \$456 ; + assign \$45 = \$43 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:409" *) fsm_update; + assign \$460 = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:770" *) 1'h1; + assign \$463 = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:795" *) 1'h1; assign \$465 = + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) dmi0__addr_i; - assign \$468 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) 1'h1; - assign \$470 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) 2'h2; - assign \$472 = \$468 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) \$470 ; - assign \$474 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) 2'h2; - assign \$477 = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" *) 1'h1; - assign \$47 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) 1'h0; - assign \$480 = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" *) 1'h1; - assign \$49 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" *) 1'h0; - assign \$51 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[0] : mspi0_clk__core__o; - assign \$53 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[1] : mspi0_cs_n__core__o; - assign \$55 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[2] : mspi0_mosi__core__o; - assign \$57 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[3] : mspi0_miso__pad__i; - assign \$5 = \$1 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) \$3 ; - assign \$59 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[4] : sdr_dm_0__core__o; - assign \$61 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[5] : sdr_dq_0__pad__i; - assign \$63 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[6] : sdr_dq_0__core__o; - assign \$65 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[7] : sdr_dq_0__core__oe; - assign \$67 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[8] : sdr_dq_1__pad__i; - assign \$69 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[9] : sdr_dq_1__core__o; - assign \$71 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[10] : sdr_dq_1__core__oe; - assign \$73 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[11] : sdr_dq_2__pad__i; - assign \$75 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[12] : sdr_dq_2__core__o; - assign \$77 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[13] : sdr_dq_2__core__oe; - assign \$7 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) \$5 ; - assign \$79 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[14] : sdr_dq_3__pad__i; - assign \$81 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[15] : sdr_dq_3__core__o; - assign \$83 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[16] : sdr_dq_3__core__oe; - assign \$85 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[17] : sdr_dq_4__pad__i; - assign \$87 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[18] : sdr_dq_4__core__o; - assign \$89 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[19] : sdr_dq_4__core__oe; - assign \$91 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[20] : sdr_dq_5__pad__i; - assign \$93 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[21] : sdr_dq_5__core__o; - assign \$95 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[22] : sdr_dq_5__core__oe; - assign \$97 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[23] : sdr_dq_6__pad__i; + assign \$468 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) 1'h1; + assign \$470 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) 2'h2; + assign \$472 = \$468 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) \$470 ; + assign \$474 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:531" *) 2'h2; + assign \$477 = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:500" *) 1'h1; + assign \$47 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:410" *) 1'h0; + assign \$480 = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:525" *) 1'h1; + assign \$49 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:411" *) 1'h0; + assign \$51 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[0] : mspi0_clk__core__o; + assign \$53 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[1] : mspi0_cs_n__core__o; + assign \$55 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[2] : mspi0_mosi__core__o; + assign \$57 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) io_bd[3] : mspi0_miso__pad__i; + assign \$5 = \$1 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) \$3 ; + assign \$59 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[4] : sdr_dm_0__core__o; + assign \$61 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[5] : sdr_dq_0__pad__i; + assign \$63 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[6] : sdr_dq_0__core__o; + assign \$65 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[7] : sdr_dq_0__core__oe; + assign \$67 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[8] : sdr_dq_1__pad__i; + assign \$69 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[9] : sdr_dq_1__core__o; + assign \$71 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[10] : sdr_dq_1__core__oe; + assign \$73 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[11] : sdr_dq_2__pad__i; + assign \$75 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[12] : sdr_dq_2__core__o; + assign \$77 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[13] : sdr_dq_2__core__oe; + assign \$7 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) \$5 ; + assign \$79 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[14] : sdr_dq_3__pad__i; + assign \$81 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[15] : sdr_dq_3__core__o; + assign \$83 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[16] : sdr_dq_3__core__oe; + assign \$85 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[17] : sdr_dq_4__pad__i; + assign \$87 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[18] : sdr_dq_4__core__o; + assign \$89 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[19] : sdr_dq_4__core__oe; + assign \$91 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[20] : sdr_dq_5__pad__i; + assign \$93 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[21] : sdr_dq_5__core__o; + assign \$95 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[22] : sdr_dq_5__core__oe; + assign \$97 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[23] : sdr_dq_6__pad__i; always @(posedge clk) wb_icache_en <= \wb_icache_en$next ; always @(posedge clk) @@ -139987,15 +139987,15 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end TAP_tdo = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:421" *) casez ({ \$321 , idblock_select_id, fsm_isir }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:421" */ 3'b??1: TAP_tdo = irblock_tdo; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:417" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:423" */ 3'b?1?: TAP_tdo = idblock_TAP_id_tdo; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:420" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:426" */ 3'b1??: TAP_tdo = io_sr[129]; endcase @@ -140003,7 +140003,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \sr0_update_core$next = sr0_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr0_update_core$next = 1'h0; @@ -140012,7 +140012,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \sr0_update_core_prev$next = sr0_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr0_update_core_prev$next = 1'h0; @@ -140021,16 +140021,16 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) casez (\$339 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ 1'h1: \sr0__oe$next = sr0_isir; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:670" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ default: \sr0__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr0__oe$next = 1'h0; @@ -140039,19 +140039,19 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \sr0_reg$next = sr0_reg; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) casez (sr0_shift) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ 1'h1: \sr0_reg$next = { TAP_bus__tdi, sr0_reg[2:1] }; endcase - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) casez (sr0_capture) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ 1'h1: \sr0_reg$next = sr0__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \sr0_reg$next = 3'h0; @@ -140060,7 +140060,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_addrsr_update_core$next = jtag_wb_addrsr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_addrsr_update_core$next = 1'h0; @@ -140069,7 +140069,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_addrsr_update_core_prev$next = jtag_wb_addrsr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_addrsr_update_core_prev$next = 1'h0; @@ -140078,16 +140078,16 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) casez (\$357 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ 1'h1: \jtag_wb_addrsr__oe$next = jtag_wb_addrsr_isir; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:670" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ default: \jtag_wb_addrsr__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_addrsr__oe$next = 1'h0; @@ -140096,19 +140096,19 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_addrsr_reg$next = jtag_wb_addrsr_reg; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) casez (jtag_wb_addrsr_shift) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ 1'h1: \jtag_wb_addrsr_reg$next = { TAP_bus__tdi, jtag_wb_addrsr_reg[29:1] }; endcase - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) casez (jtag_wb_addrsr_capture) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ 1'h1: \jtag_wb_addrsr_reg$next = jtag_wb_addrsr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \jtag_wb_addrsr_reg$next = 30'h00000000; @@ -140117,7 +140117,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_datasr_update_core$next = jtag_wb_datasr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_datasr_update_core$next = 1'h0; @@ -140126,7 +140126,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_datasr_update_core_prev$next = jtag_wb_datasr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_datasr_update_core_prev$next = 1'h0; @@ -140135,16 +140135,16 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) casez (\$377 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ 1'h1: \jtag_wb_datasr__oe$next = jtag_wb_datasr_isir; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:670" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ default: \jtag_wb_datasr__oe$next = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_datasr__oe$next = 2'h0; @@ -140153,19 +140153,19 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_datasr_reg$next = jtag_wb_datasr_reg; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) casez (jtag_wb_datasr_shift) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ 1'h1: \jtag_wb_datasr_reg$next = { TAP_bus__tdi, jtag_wb_datasr_reg[31:1] }; endcase - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) casez (jtag_wb_datasr_capture) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ 1'h1: \jtag_wb_datasr_reg$next = jtag_wb_datasr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \jtag_wb_datasr_reg$next = 32'd0; @@ -140174,7 +140174,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_addrsr_update_core$next = dmi0_addrsr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_addrsr_update_core$next = 1'h0; @@ -140183,7 +140183,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_addrsr_update_core_prev$next = dmi0_addrsr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_addrsr_update_core_prev$next = 1'h0; @@ -140192,16 +140192,16 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) casez (\$395 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ 1'h1: \dmi0_addrsr__oe$next = dmi0_addrsr_isir; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:670" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ default: \dmi0_addrsr__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_addrsr__oe$next = 1'h0; @@ -140210,19 +140210,19 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_addrsr_reg$next = dmi0_addrsr_reg; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) casez (dmi0_addrsr_shift) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ 1'h1: \dmi0_addrsr_reg$next = { TAP_bus__tdi, dmi0_addrsr_reg[7:1] }; endcase - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) casez (dmi0_addrsr_capture) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ 1'h1: \dmi0_addrsr_reg$next = dmi0_addrsr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \dmi0_addrsr_reg$next = 8'h00; @@ -140231,7 +140231,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_datasr_update_core$next = dmi0_datasr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_datasr_update_core$next = 1'h0; @@ -140240,7 +140240,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_datasr_update_core_prev$next = dmi0_datasr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_datasr_update_core_prev$next = 1'h0; @@ -140249,16 +140249,16 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) casez (\$415 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ 1'h1: \dmi0_datasr__oe$next = dmi0_datasr_isir; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:670" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ default: \dmi0_datasr__oe$next = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_datasr__oe$next = 2'h0; @@ -140267,19 +140267,19 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_datasr_reg$next = dmi0_datasr_reg; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) casez (dmi0_datasr_shift) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ 1'h1: \dmi0_datasr_reg$next = { TAP_bus__tdi, dmi0_datasr_reg[63:1] }; endcase - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) casez (dmi0_datasr_capture) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ 1'h1: \dmi0_datasr_reg$next = dmi0_datasr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \dmi0_datasr_reg$next = 64'h0000000000000000; @@ -140288,7 +140288,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \sr5_update_core$next = sr5_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr5_update_core$next = 1'h0; @@ -140297,7 +140297,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \sr5_update_core_prev$next = sr5_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr5_update_core_prev$next = 1'h0; @@ -140306,16 +140306,16 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) casez (\$433 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ 1'h1: \sr5__oe$next = sr5_isir; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:670" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ default: \sr5__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr5__oe$next = 1'h0; @@ -140324,19 +140324,19 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \sr5_reg$next = sr5_reg; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) casez (sr5_shift) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ 1'h1: \sr5_reg$next = { TAP_bus__tdi, sr5_reg[2:1] }; endcase - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) casez (sr5_capture) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ 1'h1: \sr5_reg$next = sr5__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \sr5_reg$next = 3'h0; @@ -140345,27 +140345,27 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:694" *) casez ({ sr5_shift, dmi0_datasr_shift, dmi0_addrsr_shift, jtag_wb_datasr_shift, jtag_wb_addrsr_shift, sr0_shift }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:694" */ 6'b?????1: TAP_bus__tdo = sr0_reg[0]; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:688" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:697" */ 6'b????1?: TAP_bus__tdo = jtag_wb_addrsr_reg[0]; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:688" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:697" */ 6'b???1??: TAP_bus__tdo = jtag_wb_datasr_reg[0]; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:688" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:697" */ 6'b??1???: TAP_bus__tdo = dmi0_addrsr_reg[0]; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:688" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:697" */ 6'b?1????: TAP_bus__tdo = dmi0_datasr_reg[0]; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:688" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:697" */ 6'b1?????: TAP_bus__tdo = sr5_reg[0]; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:692" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:701" */ default: TAP_bus__tdo = TAP_tdo; endcase @@ -140373,43 +140373,43 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb__adr$next = jtag_wb__adr; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) casez (fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:755" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:764" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" *) casez ({ jtag_wb_datasr__oe, jtag_wb_addrsr__oe }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" */ 3'b??1: \jtag_wb__adr$next = jtag_wb_addrsr__o; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:759" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:768" */ 3'b?1?: \jtag_wb__adr$next = \$459 [29:0]; endcase /* \nmigen.decoding = "READ/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:766" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:775" */ 3'h1: /* empty */; /* \nmigen.decoding = "READACK/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:772" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:781" */ 3'h3: /* empty */; /* \nmigen.decoding = "WRITEREAD/2" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:778" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:787" */ 3'h2: /* empty */; /* \nmigen.decoding = "WRITEREADACK/4" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:784" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:793" */ 3'h4: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:794" *) casez (jtag_wb__ack) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:794" */ 1'h1: \jtag_wb__adr$next = \$462 [29:0]; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb__adr$next = 30'h00000000; @@ -140418,51 +140418,51 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \fsm_state$next = fsm_state; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) casez (fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:755" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:764" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" *) casez ({ jtag_wb_datasr__oe, jtag_wb_addrsr__oe }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" */ 3'b??1: \fsm_state$next = 3'h1; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:759" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:768" */ 3'b?1?: \fsm_state$next = 3'h1; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:772" */ 3'b1??: \fsm_state$next = 3'h2; endcase /* \nmigen.decoding = "READ/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:766" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:775" */ 3'h1: \fsm_state$next = 3'h3; /* \nmigen.decoding = "READACK/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:772" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:781" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:782" *) casez (jtag_wb__ack) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:782" */ 1'h1: \fsm_state$next = 3'h0; endcase /* \nmigen.decoding = "WRITEREAD/2" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:778" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:787" */ 3'h2: \fsm_state$next = 3'h4; /* \nmigen.decoding = "WRITEREADACK/4" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:784" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:793" */ 3'h4: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:794" *) casez (jtag_wb__ack) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:794" */ 1'h1: \fsm_state$next = 3'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \fsm_state$next = 3'h0; @@ -140471,25 +140471,25 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb__dat_w$next = jtag_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) casez (fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:755" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:764" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" *) casez ({ jtag_wb_datasr__oe, jtag_wb_addrsr__oe }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" */ 3'b??1: /* empty */; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:759" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:768" */ 3'b?1?: /* empty */; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:772" */ 3'b1??: \jtag_wb__dat_w$next = jtag_wb_datasr__o; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb__dat_w$next = 32'd0; @@ -140498,27 +140498,27 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_datasr__i$next = jtag_wb_datasr__i; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) casez (fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:755" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:764" */ 3'h0: /* empty */; /* \nmigen.decoding = "READ/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:766" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:775" */ 3'h1: /* empty */; /* \nmigen.decoding = "READACK/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:772" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:781" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:782" *) casez (jtag_wb__ack) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:782" */ 1'h1: \jtag_wb_datasr__i$next = jtag_wb__dat_r; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_datasr__i$next = 32'd0; @@ -140527,43 +140527,43 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0__addr_i$next = dmi0__addr_i; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) casez (\fsm_state$467 ) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:488" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" *) casez ({ dmi0_datasr__oe, dmi0_addrsr__oe }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" */ 3'b??1: \dmi0__addr_i$next = dmi0_addrsr__o[3:0]; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:492" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:498" */ 3'b?1?: \dmi0__addr_i$next = \$476 [3:0]; endcase /* \nmigen.decoding = "READ/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:501" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:507" */ 3'h1: /* empty */; /* \nmigen.decoding = "READACK/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:505" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:511" */ 3'h3: /* empty */; /* \nmigen.decoding = "WRRD/2" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:519" */ 3'h2: /* empty */; /* \nmigen.decoding = "WRRDACK/4" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:516" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" */ 3'h4: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) casez (dmi0__ack_o) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" */ 1'h1: \dmi0__addr_i$next = \$479 [3:0]; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0__addr_i$next = 4'h0; @@ -140572,51 +140572,51 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \fsm_state$467$next = \fsm_state$467 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) casez (\fsm_state$467 ) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:488" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" *) casez ({ dmi0_datasr__oe, dmi0_addrsr__oe }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" */ 3'b??1: \fsm_state$467$next = 3'h1; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:492" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:498" */ 3'b?1?: \fsm_state$467$next = 3'h1; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:496" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:502" */ 3'b1??: \fsm_state$467$next = 3'h2; endcase /* \nmigen.decoding = "READ/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:501" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:507" */ 3'h1: \fsm_state$467$next = 3'h3; /* \nmigen.decoding = "READACK/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:505" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:511" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" *) casez (dmi0__ack_o) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" */ 1'h1: \fsm_state$467$next = 3'h0; endcase /* \nmigen.decoding = "WRRD/2" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:519" */ 3'h2: \fsm_state$467$next = 3'h4; /* \nmigen.decoding = "WRRDACK/4" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:516" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" */ 3'h4: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) casez (dmi0__ack_o) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" */ 1'h1: \fsm_state$467$next = 3'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \fsm_state$467$next = 3'h0; @@ -140625,25 +140625,25 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0__din$next = dmi0__din; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) casez (\fsm_state$467 ) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:488" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" *) casez ({ dmi0_datasr__oe, dmi0_addrsr__oe }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" */ 3'b??1: /* empty */; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:492" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:498" */ 3'b?1?: /* empty */; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:496" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:502" */ 3'b1??: \dmi0__din$next = dmi0_datasr__o; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0__din$next = 64'h0000000000000000; @@ -140652,27 +140652,27 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_datasr__i$next = dmi0_datasr__i; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) casez (\fsm_state$467 ) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:488" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" */ 3'h0: /* empty */; /* \nmigen.decoding = "READ/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:501" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:507" */ 3'h1: /* empty */; /* \nmigen.decoding = "READACK/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:505" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:511" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" *) casez (dmi0__ack_o) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" */ 1'h1: \dmi0_datasr__i$next = dmi0__dout; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_datasr__i$next = 64'h0000000000000000; @@ -140689,7 +140689,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ 1'h1: { \wb_sram_en$next , \wb_dcache_en$next , \wb_icache_en$next } = sr5__o; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -140712,16 +140712,16 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \io_sr$next = io_sr; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" *) casez ({ io_update, io_shift, io_capture }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" */ 3'b??1: \io_sr$next = { eint_2__pad__i, eint_1__pad__i, eint_0__pad__i, mtwi_scl__core__o, mtwi_sda__core__oe, mtwi_sda__core__o, mtwi_sda__pad__i, gpio_s7__core__oe, gpio_s7__core__o, gpio_s7__pad__i, gpio_s6__core__oe, gpio_s6__core__o, gpio_s6__pad__i, gpio_s5__core__oe, gpio_s5__core__o, gpio_s5__pad__i, gpio_s4__core__oe, gpio_s4__core__o, gpio_s4__pad__i, gpio_s3__core__oe, gpio_s3__core__o, gpio_s3__pad__i, gpio_s2__core__oe, gpio_s2__core__o, gpio_s2__pad__i, gpio_s1__core__oe, gpio_s1__core__o, gpio_s1__pad__i, gpio_s0__core__oe, gpio_s0__core__o, gpio_s0__pad__i, gpio_e15__core__oe, gpio_e15__core__o, gpio_e15__pad__i, gpio_e14__core__oe, gpio_e14__core__o, gpio_e14__pad__i, gpio_e13__core__oe, gpio_e13__core__o, gpio_e13__pad__i, gpio_e12__core__oe, gpio_e12__core__o, gpio_e12__pad__i, gpio_e11__core__oe, gpio_e11__core__o, gpio_e11__pad__i, gpio_e10__core__oe, gpio_e10__core__o, gpio_e10__pad__i, gpio_e9__core__oe, gpio_e9__core__o, gpio_e9__pad__i, gpio_e8__core__oe, gpio_e8__core__o, gpio_e8__pad__i, sdr_dq_15__core__oe, sdr_dq_15__core__o, sdr_dq_15__pad__i, sdr_dq_14__core__oe, sdr_dq_14__core__o, sdr_dq_14__pad__i, sdr_dq_13__core__oe, sdr_dq_13__core__o, sdr_dq_13__pad__i, sdr_dq_12__core__oe, sdr_dq_12__core__o, sdr_dq_12__pad__i, sdr_dq_11__core__oe, sdr_dq_11__core__o, sdr_dq_11__pad__i, sdr_dq_10__core__oe, sdr_dq_10__core__o, sdr_dq_10__pad__i, sdr_dq_9__core__oe, sdr_dq_9__core__o, sdr_dq_9__pad__i, sdr_dq_8__core__oe, sdr_dq_8__core__o, sdr_dq_8__pad__i, sdr_dm_1__core__o, sdr_a_12__core__o, sdr_a_11__core__o, sdr_a_10__core__o, sdr_cs_n__core__o, sdr_we_n__core__o, sdr_cas_n__core__o, sdr_ras_n__core__o, sdr_cke__core__o, sdr_clock__core__o, sdr_ba_1__core__o, sdr_ba_0__core__o, sdr_a_9__core__o, sdr_a_8__core__o, sdr_a_7__core__o, sdr_a_6__core__o, sdr_a_5__core__o, sdr_a_4__core__o, sdr_a_3__core__o, sdr_a_2__core__o, sdr_a_1__core__o, sdr_a_0__core__o, sdr_dq_7__core__oe, sdr_dq_7__core__o, sdr_dq_7__pad__i, sdr_dq_6__core__oe, sdr_dq_6__core__o, sdr_dq_6__pad__i, sdr_dq_5__core__oe, sdr_dq_5__core__o, sdr_dq_5__pad__i, sdr_dq_4__core__oe, sdr_dq_4__core__o, sdr_dq_4__pad__i, sdr_dq_3__core__oe, sdr_dq_3__core__o, sdr_dq_3__pad__i, sdr_dq_2__core__oe, sdr_dq_2__core__o, sdr_dq_2__pad__i, sdr_dq_1__core__oe, sdr_dq_1__core__o, sdr_dq_1__pad__i, sdr_dq_0__core__oe, sdr_dq_0__core__o, sdr_dq_0__pad__i, sdr_dm_0__core__o, mspi0_miso__pad__i, mspi0_mosi__core__o, mspi0_cs_n__core__o, mspi0_clk__core__o }; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:570" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:577" */ 3'b?1?: \io_sr$next = { io_sr[128:0], TAP_bus__tdi }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \io_sr$next = 130'h000000000000000000000000000000000; @@ -140730,19 +140730,19 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \io_bd$next = io_bd; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" *) casez ({ io_update, io_shift, io_capture }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" */ 3'b??1: /* empty */; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:570" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:577" */ 3'b?1?: /* empty */; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:574" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:581" */ 3'b1??: \io_bd$next = io_sr; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (negjtag_rst) 1'h1: \io_bd$next = 130'h000000000000000000000000000000000; @@ -140757,8 +140757,8 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign dmi0__we_i = \$474 ; assign dmi0__req_i = \$472 ; assign dmi0_addrsr__i = \$465 ; - assign jtag_wb__we = \$457 ; - assign jtag_wb__cyc = \$449 ; + assign jtag_wb__cyc = \$455 ; + assign jtag_wb__we = \$453 ; assign jtag_wb__stb = \$447 ; assign jtag_wb__sel[3] = 1'h1; assign jtag_wb__sel[2] = 1'h1; @@ -140937,9 +140937,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.l0" *) (* generator = "nMigen" *) module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -140959,9 +140959,9 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_ output dbus__stb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) output dbus__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [95:0] ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input ldst_port0_addr_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) output ldst_port0_addr_ok_o; @@ -140969,37 +140969,37 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_ output ldst_port0_busy_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) input [3:0] ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$7 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) input ldst_port0_is_ld_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) input ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input ldst_port0_st_data_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [47:0] pimem_ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pimem_ldst_port0_addr_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) wire pimem_ldst_port0_addr_ok_o; @@ -141007,19 +141007,19 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_ wire pimem_ldst_port0_busy_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) wire [3:0] pimem_ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \pimem_ldst_port0_exc_$signal ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) wire pimem_ldst_port0_is_ld_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) wire pimem_ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pimem_ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pimem_ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] pimem_ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire pimem_ldst_port0_st_data_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" *) wire [63:0] pimem_m_ld_data_o; @@ -141145,9 +141145,9 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ wire [95:0] \$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" *) wire [95:0] \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg \idx_l$23 = 1'h0; @@ -141159,14 +141159,14 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ reg idx_l_r_idx_l; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg idx_l_s_idx_l; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [95:0] ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [47:0] \ldst_port0_addr_i$12 ; reg [47:0] \ldst_port0_addr_i$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input ldst_port0_addr_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \ldst_port0_addr_i_ok$13 ; reg \ldst_port0_addr_i_ok$13 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) @@ -141188,44 +141188,44 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) output [3:0] \ldst_port0_data_len$11 ; reg [3:0] \ldst_port0_data_len$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal ; reg \ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$1 ; reg \ldst_port0_exc_$signal$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$2 ; reg \ldst_port0_exc_$signal$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$3 ; reg \ldst_port0_exc_$signal$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \ldst_port0_exc_$signal$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \ldst_port0_exc_$signal$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \ldst_port0_exc_$signal$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \ldst_port0_exc_$signal$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \ldst_port0_exc_$signal$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \ldst_port0_exc_$signal$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \ldst_port0_exc_$signal$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$4 ; reg \ldst_port0_exc_$signal$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$5 ; reg \ldst_port0_exc_$signal$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$6 ; reg \ldst_port0_exc_$signal$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) output \ldst_port0_exc_$signal$7 ; reg \ldst_port0_exc_$signal$7 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) @@ -141242,15 +141242,15 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) output \ldst_port0_is_st_i$9 ; reg \ldst_port0_is_st_i$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] ldst_port0_ld_data_o; reg [63:0] ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] \ldst_port0_ld_data_o$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output ldst_port0_ld_data_o_ok; reg ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input \ldst_port0_ld_data_o_ok$16 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" *) reg ldst_port0_ldst_error; @@ -141260,14 +141260,14 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ reg ldst_port0_mmu_done; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" *) wire \ldst_port0_mmu_done$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \ldst_port0_st_data_i$18 ; reg [63:0] \ldst_port0_st_data_i$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input ldst_port0_st_data_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \ldst_port0_st_data_i_ok$17 ; reg \ldst_port0_st_data_i_ok$17 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" *) @@ -141401,7 +141401,7 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ 1'h1: \idx_l$23$next = pick_o; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \idx_l$23$next = 1'h0; @@ -141559,9 +141559,9 @@ module ld_active(coresync_rst, r_ld_active, s_ld_active, q_ld_active, coresync_c wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -141590,7 +141590,7 @@ module ld_active(coresync_rst, r_ld_active, s_ld_active, q_ld_active, coresync_c always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -141819,9 +141819,9 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, wire \alu_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" *) wire alu_valid; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) input cu_ad__go_i; @@ -141857,27 +141857,27 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg [63:0] dest1_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) reg [63:0] dest2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] ea; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg [63:0] ea_r = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg [63:0] \ea_r$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \exc_$signal$179 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \exc_$signal$180 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \exc_$signal$181 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \exc_$signal$182 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \exc_$signal$183 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \exc_$signal$184 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \exc_$signal$185 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" *) wire ld_o; @@ -141893,15 +141893,15 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg [63:0] ldo_r = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg [63:0] \ldo_r$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [95:0] ldst_port0_addr_i; reg [95:0] ldst_port0_addr_i = 96'h000000000000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [95:0] \ldst_port0_addr_i$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output ldst_port0_addr_i_ok; reg ldst_port0_addr_i_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \ldst_port0_addr_i_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) input ldst_port0_addr_ok_o; @@ -141909,34 +141909,34 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, input ldst_port0_busy_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) output [3:0] ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal$7 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) output ldst_port0_is_ld_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) output ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] ldst_port0_st_data_i; reg [63:0] ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output ldst_port0_st_data_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" *) wire load_mem_o; @@ -141954,7 +141954,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg \lsd_l_r_lsd$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire lsd_l_s_lsd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" *) wire op_is_ld; @@ -142588,7 +142588,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -142597,7 +142597,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \opc_l_r_opc$next = reset_o; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -142606,7 +142606,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -142615,7 +142615,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -142624,7 +142624,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \adr_l_r_adr$next = reset_a; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \adr_l_r_adr$next = 1'h1; @@ -142633,7 +142633,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \wri_l_r_wri$next = \$38 [0]; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wri_l_r_wri$next = 1'h1; @@ -142642,7 +142642,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \upd_l_s_upd$next = reset_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \upd_l_s_upd$next = 1'h0; @@ -142651,7 +142651,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \upd_l_r_upd$next = reset_u; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \upd_l_r_upd$next = 1'h1; @@ -142660,7 +142660,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \sto_l_r_sto$next = \$59 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \sto_l_r_sto$next = 1'h1; @@ -142669,7 +142669,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \lsd_l_r_lsd$next = \$63 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \lsd_l_r_lsd$next = 1'h1; @@ -142705,7 +142705,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, 1'h1: { \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = 133'h0000000000000000000000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -142809,7 +142809,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \ldst_port0_addr_i_ok$next = \$177 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ldst_port0_addr_i_ok$next = 1'h0; @@ -143616,9 +143616,9 @@ module lod_l(coresync_rst, s_lod, r_lod, qn_lod, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -143647,7 +143647,7 @@ module lod_l(coresync_rst, s_lod, r_lod, qn_lod, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -143802,7 +143802,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical reg \alu_l_r_alu$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alu_l_s_alu; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] alu_logical0_cr_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg [3:0] alu_logical0_logical_op__data_len = 4'h0; @@ -143974,7 +143974,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical wire alu_logical0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_logical0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_logical0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_logical0_p_ready_o; @@ -143998,11 +143998,11 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -144048,7 +144048,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [3:0] dest2_o; reg [3:0] dest2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -144501,7 +144501,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -144510,7 +144510,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$63 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -144519,7 +144519,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -144528,7 +144528,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -144537,7 +144537,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -144546,7 +144546,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -144555,7 +144555,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -144564,7 +144564,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -144573,7 +144573,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \req_l_s_req$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 2'h0; @@ -144582,7 +144582,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \req_l_r_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 2'h3; @@ -144614,7 +144614,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical 1'h1: { \alu_logical0_logical_op__insn$next , \alu_logical0_logical_op__data_len$next , \alu_logical0_logical_op__is_signed$next , \alu_logical0_logical_op__is_32bit$next , \alu_logical0_logical_op__output_carry$next , \alu_logical0_logical_op__write_cr0$next , \alu_logical0_logical_op__invert_out$next , \alu_logical0_logical_op__input_carry$next , \alu_logical0_logical_op__zero_a$next , \alu_logical0_logical_op__invert_in$next , \alu_logical0_logical_op__oe__ok$next , \alu_logical0_logical_op__oe__oe$next , \alu_logical0_logical_op__rc__ok$next , \alu_logical0_logical_op__rc__rc$next , \alu_logical0_logical_op__imm_data__ok$next , \alu_logical0_logical_op__imm_data__data$next , \alu_logical0_logical_op__fn_unit$next , \alu_logical0_logical_op__insn_type$next } = { oper_i_alu_logical0__insn, oper_i_alu_logical0__data_len, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -144643,7 +144643,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -144665,7 +144665,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -144704,7 +144704,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -144713,7 +144713,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$91 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -144742,7 +144742,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \prev_wr_go$next = \$19 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 2'h0; @@ -144788,27 +144788,27 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; reg [3:0] cr_a = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [3:0] \cr_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \cr_a_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [3:0] input_logical_op__data_len; @@ -145794,9 +145794,9 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \main_muxid$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] main_ra; @@ -145804,7 +145804,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn wire [63:0] main_rb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire main_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \main_xer_so$62 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] muxid; @@ -145821,19 +145821,19 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -145851,23 +145851,23 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn input [63:0] ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so; reg xer_so = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input \xer_so$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$93 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so_ok$next ; assign \$64 = \p_valid_i$63 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) @@ -146034,7 +146034,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -146082,7 +146082,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn 2'b1?: { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -146108,7 +146108,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn 2'b1?: { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -146127,7 +146127,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn 2'b1?: { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -146146,7 +146146,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn 2'b1?: { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -146183,29 +146183,29 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] \cr_a$22 ; reg [3:0] \cr_a$22 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [3:0] \cr_a$22$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \cr_a_ok$23 ; reg \cr_a_ok$23 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \cr_a_ok$23$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$73 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) input [3:0] logical_op__data_len; @@ -146666,29 +146666,29 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \o$20 ; reg [63:0] \o$20 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$20$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$21 ; reg \o_ok$21 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$21$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] output_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \output_cr_a$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [3:0] output_logical_op__data_len; @@ -146954,15 +146954,15 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn wire [1:0] output_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \output_muxid$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] output_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \output_o$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \output_o_ok$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_so; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -146976,11 +146976,11 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$47 ; assign \$49 = \p_valid_i$48 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) @@ -147099,7 +147099,7 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -147147,7 +147147,7 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn 2'b1?: { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -147173,7 +147173,7 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn 2'b1?: { \o_ok$21$next , \o$20$next } = { \o_ok$71 , \o$70 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$21$next = 1'h0; @@ -147192,7 +147192,7 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn 2'b1?: { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$73 , \cr_a$72 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$23$next = 1'h0; @@ -147234,9 +147234,9 @@ module lsd_l(coresync_rst, s_lsd, r_lsd, q_lsd, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -147265,7 +147265,7 @@ module lsd_l(coresync_rst, s_lsd, r_lsd, q_lsd, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -147376,9 +147376,9 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ wire \$93 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *) wire \$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -147548,7 +147548,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__cyc$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__cyc$next = 1'h0; @@ -147576,7 +147576,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__stb$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__stb$next = 1'h0; @@ -147637,7 +147637,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__sel$next = 8'h00; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__sel$next = 8'h00; @@ -147662,7 +147662,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \m_ld_data_o$next = 64'h0000000000000000; @@ -147689,7 +147689,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__adr$next = 45'h000000000000; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__adr$next = 45'h000000000000; @@ -147716,7 +147716,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__we$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__we$next = 1'h0; @@ -147743,7 +147743,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__dat_w$next = 64'h0000000000000000; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__dat_w$next = 64'h0000000000000000; @@ -147766,7 +147766,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \m_load_err_o$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \m_load_err_o$next = 1'h0; @@ -147789,7 +147789,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \m_store_err_o$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \m_store_err_o$next = 1'h0; @@ -147809,7 +147809,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \m_badaddr_o$next = dbus__adr; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \m_badaddr_o$next = 45'h000000000000; @@ -148227,10 +148227,10 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ reg carry_32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" *) reg carry_64; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; reg [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; reg cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" *) @@ -148245,10 +148245,10 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" *) @@ -148263,21 +148263,21 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ reg [4:0] tval; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ca$20 ; reg [1:0] \xer_ca$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; reg xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ov; reg [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; reg xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$21 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" *) reg zerohi; @@ -148883,9 +148883,9 @@ module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) @@ -149178,11 +149178,11 @@ module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op input sr_op__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output \sr_op__write_cr0$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ca; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$19 ; rotator rotator ( .arith(rotator_arith), @@ -149570,27 +149570,27 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o reg ctr_zero_bo1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \fast1$10 ; reg [63:0] \fast1$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; reg fast1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \fast2$11 ; reg [63:0] \fast2$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast2_ok; reg fast2_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output nia_ok; assign \$12 = br_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) 7'h08; assign \$14 = br_op__insn[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) \$12 ; @@ -149931,18 +149931,18 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m wire equal; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \fast1$11 ; reg [63:0] \fast1$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; reg fast1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \fast2$12 ; reg [63:0] \fast2$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast2_ok; reg fast2_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" *) @@ -149953,26 +149953,26 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m wire lt_s; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" *) wire lt_u; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] msr; reg [63:0] msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output msr_ok; reg msr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] nia; reg [63:0] nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output nia_ok; reg nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) @@ -150201,21 +150201,21 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m input [7:0] trap_op__traptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) output [7:0] \trap_op__traptype$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \trapexc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \trapexc_$signal$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \trapexc_$signal$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \trapexc_$signal$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \trapexc_$signal$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \trapexc_$signal$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \trapexc_$signal$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \trapexc_$signal$70 ; assign \$13 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ra[31:0]; assign \$15 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) rb[31:0]; @@ -151246,10 +151246,10 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" *) @@ -151268,7 +151268,7 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat input [63:0] rb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$20 ; assign \$99 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; assign \$101 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; @@ -151842,10 +151842,10 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, reg [1:0] bt; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] \cr_a$6 ; reg [3:0] \cr_a$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; reg cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) @@ -152048,10 +152048,10 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, output [6:0] \cr_op__insn_type$2 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [31:0] full_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [31:0] \full_cr$5 ; reg [31:0] \full_cr$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output full_cr_ok; reg full_cr_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" *) @@ -152060,10 +152060,10 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) @@ -152558,7 +152558,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, reg \alu_l_r_alu$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alu_l_s_alu; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] alu_mul0_cr_a; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -152702,7 +152702,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, wire alu_mul0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_mul0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_mul0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_mul0_p_ready_o; @@ -152712,9 +152712,9 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, wire [63:0] alu_mul0_ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] alu_mul0_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] alu_mul0_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire alu_mul0_xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire \alu_mul0_xer_so$1 ; @@ -152730,11 +152730,11 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -152802,7 +152802,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output dest4_o; reg dest4_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -153004,9 +153004,9 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, wire src_sel; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; assign \$100 = \$96 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$98 ; assign \$102 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; @@ -153236,7 +153236,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -153245,7 +153245,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$64 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -153254,7 +153254,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -153263,7 +153263,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -153272,7 +153272,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -153281,7 +153281,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -153290,7 +153290,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -153299,7 +153299,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -153308,7 +153308,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$66 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 4'h0; @@ -153317,7 +153317,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 4'hf; @@ -153343,7 +153343,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \alu_mul0_mul_op__insn$next , \alu_mul0_mul_op__is_signed$next , \alu_mul0_mul_op__is_32bit$next , \alu_mul0_mul_op__write_cr0$next , \alu_mul0_mul_op__oe__ok$next , \alu_mul0_mul_op__oe__oe$next , \alu_mul0_mul_op__rc__ok$next , \alu_mul0_mul_op__rc__rc$next , \alu_mul0_mul_op__imm_data__ok$next , \alu_mul0_mul_op__imm_data__data$next , \alu_mul0_mul_op__fn_unit$next , \alu_mul0_mul_op__insn_type$next } = { oper_i_alu_mul0__insn, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -153372,7 +153372,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -153394,7 +153394,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -153416,7 +153416,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r2__xer_ov_ok$next , \data_r2__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__xer_ov_ok$next = 1'h0; @@ -153438,7 +153438,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r3__xer_so_ok$next = 1'h0; @@ -153477,7 +153477,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$88 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -153486,7 +153486,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$90 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -153535,7 +153535,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$20 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 4'h0; @@ -154449,23 +154449,23 @@ module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ input neg_res; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [128:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \o$14 ; reg [63:0] \o$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ov; reg [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; reg xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; assign \$17 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) o; assign \$19 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) o; @@ -154597,9 +154597,9 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -155668,7 +155668,7 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -155710,7 +155710,7 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m 2'b1?: { \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -155818,9 +155818,9 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -156609,7 +156609,7 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -156651,7 +156651,7 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -156742,29 +156742,29 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; reg [3:0] cr_a = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [3:0] \cr_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \cr_a_ok$next ; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -157002,19 +157002,19 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m wire mul3_neg_res; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [128:0] mul3_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \mul3_o$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire mul3_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] mul3_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire mul3_xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire mul3_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \mul3_xer_so$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire mul3_xer_so_ok; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -157417,25 +157417,25 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m wire \neg_res32$49 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [128:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \o$14 ; reg [63:0] \o$14 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$14$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] output_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \output_cr_a$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_cr_a_ok; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -157669,25 +157669,25 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m wire [1:0] output_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \output_muxid$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] output_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \output_o$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \output_o_ok$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] output_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \output_xer_ov$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \output_xer_so$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -157701,39 +157701,39 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ov; reg [1:0] xer_ov = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \xer_ov$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [1:0] \xer_ov$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; reg xer_ov_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ov_ok$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ov_ok$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_ov_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$15 ; reg \xer_so$15 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so$15$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so_ok$next ; assign \$56 = \p_valid_i$55 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) @@ -157878,7 +157878,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -157920,7 +157920,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -157946,7 +157946,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \o_ok$next , \o$14$next } = { \o_ok$72 , \o$71 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -157965,7 +157965,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$74 , \cr_a$73 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -157984,7 +157984,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$76 , \xer_ov$75 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -158003,7 +158003,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \xer_so_ok$next , \xer_so$15$next } = { \xer_so_ok$78 , \xer_so$77 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -158446,9 +158446,9 @@ module opc_l(coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158477,7 +158477,7 @@ module opc_l(coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158508,9 +158508,9 @@ module \opc_l$102 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158539,7 +158539,7 @@ module \opc_l$102 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158570,9 +158570,9 @@ module \opc_l$11 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158601,7 +158601,7 @@ module \opc_l$11 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158632,9 +158632,9 @@ module \opc_l$120 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158663,7 +158663,7 @@ module \opc_l$120 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158694,9 +158694,9 @@ module \opc_l$126 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158725,7 +158725,7 @@ module \opc_l$126 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158756,9 +158756,9 @@ module \opc_l$24 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158787,7 +158787,7 @@ module \opc_l$24 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158818,9 +158818,9 @@ module \opc_l$40 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158849,7 +158849,7 @@ module \opc_l$40 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158880,9 +158880,9 @@ module \opc_l$56 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158911,7 +158911,7 @@ module \opc_l$56 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158942,9 +158942,9 @@ module \opc_l$68 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158973,7 +158973,7 @@ module \opc_l$68 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -159004,9 +159004,9 @@ module \opc_l$85 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -159035,7 +159035,7 @@ module \opc_l$85 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -159056,7 +159056,7 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ wire [64:0] \$29 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) wire [63:0] \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [64:0] \$33 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) wire \$35 ; @@ -159338,11 +159338,11 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ output \alu_op__zero_a$11 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) reg [3:0] cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] \cr_a$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) wire is_cmp; @@ -159360,15 +159360,15 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \o$20 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) reg [64:0] \o$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$21 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *) wire oe; @@ -159378,32 +159378,32 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ reg so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) wire [63:0] target; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ca$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ov$24 ; reg [1:0] \xer_ov$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; reg xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$25 ; reg \xer_so$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; reg xer_so_ok; assign \$26 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) alu_op__oe__ok; assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o; assign \$29 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$30 ; - assign \$33 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; + assign \$33 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) o; assign \$35 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; assign \$37 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; assign \$39 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; @@ -159517,7 +159517,7 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) wire \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [64:0] \$22 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) wire \$24 ; @@ -159539,11 +159539,11 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, wire \$41 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) reg [3:0] cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] \cr_a$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) wire is_cmp; @@ -159789,15 +159789,15 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \o$14 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) wire [64:0] \o$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$15 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *) wire oe; @@ -159807,24 +159807,24 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, reg so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) wire [63:0] target; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ov$17 ; reg [1:0] \xer_ov$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; reg xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$18 ; reg \xer_so$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; reg xer_so_ok; assign \$19 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) mul_op__oe__ok; - assign \$22 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; + assign \$22 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) o; assign \$24 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; assign \$26 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; assign \$28 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; @@ -159922,7 +159922,7 @@ endmodule (* generator = "nMigen" *) module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, o_ok, cr_a, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \o$19 , \o_ok$20 , \cr_a$21 , cr_a_ok, \xer_ca$22 , xer_ca_ok, muxid); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [64:0] \$24 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) wire \$26 ; @@ -159940,11 +159940,11 @@ module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_ wire \$38 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) reg [3:0] cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] \cr_a$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) wire is_cmp; @@ -159962,15 +159962,15 @@ module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_ input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \o$19 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) wire [64:0] \o$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$20 ; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -160230,15 +160230,15 @@ module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_ output \sr_op__write_cr0$10 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) wire [63:0] target; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ca$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so; - assign \$24 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; + assign \$24 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) o; assign \$26 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; assign \$28 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; assign \$30 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; @@ -160285,7 +160285,7 @@ module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d wire [64:0] \$24 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) wire [63:0] \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [64:0] \$28 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) wire \$30 ; @@ -160303,11 +160303,11 @@ module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d wire \$42 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) reg [3:0] cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] \cr_a$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) wire is_cmp; @@ -160585,23 +160585,23 @@ module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \o$20 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) reg [64:0] \o$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$21 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) wire [63:0] target; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so; assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o; assign \$24 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$25 ; - assign \$28 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; + assign \$28 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) o; assign \$30 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; assign \$32 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; assign \$34 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; @@ -160660,7 +160660,7 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d wire [64:0] \$28 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) wire [63:0] \$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [64:0] \$32 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) wire \$34 ; @@ -160682,11 +160682,11 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d wire \$51 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) reg [3:0] cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] \cr_a$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) wire is_cmp; @@ -160964,15 +160964,15 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \o$20 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) reg [64:0] \o$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$21 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *) wire oe; @@ -160982,26 +160982,26 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d reg so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) wire [63:0] target; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ov$23 ; reg [1:0] \xer_ov$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; reg xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$24 ; reg \xer_so$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; reg xer_so_ok; assign \$25 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) logical_op__oe__ok; assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o; assign \$28 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$29 ; - assign \$32 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; + assign \$32 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) o; assign \$34 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; assign \$36 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; assign \$38 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; @@ -161423,10 +161423,10 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" *) reg ov; @@ -161446,13 +161446,13 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ wire [31:0] remainder_s32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" *) wire [63:0] remainder_s32_as_s64; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$20 ; assign \$21 = dividend_neg ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *) divisor_neg; assign \$23 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) quotient_root; @@ -162129,9 +162129,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu reg busy_l_r_busy; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg busy_l_s_busy; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire cyc_l_q_cyc; @@ -162159,9 +162159,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu wire \lds_dly$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire lds_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [47:0] ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input ldst_port0_addr_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) output ldst_port0_addr_ok_o; @@ -162170,21 +162170,21 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu output ldst_port0_busy_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) input [3:0] ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) input \ldst_port0_exc_$signal ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) input ldst_port0_is_ld_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) input ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] ldst_port0_ld_data_o; reg [63:0] ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output ldst_port0_ld_data_o_ok; reg ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input ldst_port0_st_data_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" *) reg [3:0] lenexp_addr_i; @@ -162394,7 +162394,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu 1'h1: \st_done_s_st_done$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \st_done_s_st_done$next = 1'h0; @@ -162413,7 +162413,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end \busy_delay$next = ldst_port0_busy_o; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \busy_delay$next = 1'h0; @@ -162699,7 +162699,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu \fsm_state$next = 2'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fsm_state$next = 2'h0; @@ -162718,7 +162718,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end \lsui_active_dly$next = lsui_active; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \lsui_active_dly$next = 1'h0; @@ -162790,7 +162790,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \adrok_l_s_addr_acked$next = 1'h0; @@ -162841,25 +162841,25 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] \cr_a$6 ; reg [3:0] \cr_a$6 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [3:0] \cr_a$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \cr_a_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [3:0] cr_b; @@ -163164,25 +163164,25 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ reg [6:0] \cr_op__insn_type$2$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [31:0] full_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [31:0] \full_cr$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [31:0] \full_cr$5 ; reg [31:0] \full_cr$5 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [31:0] \full_cr$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output full_cr_ok; reg full_cr_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \full_cr_ok$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \full_cr_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [3:0] main_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \main_cr_a$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [3:0] main_cr_b; @@ -163382,17 +163382,17 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ wire [6:0] \main_cr_op__insn_type$8 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [31:0] main_full_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [31:0] \main_full_cr$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_full_cr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \main_muxid$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] main_ra; @@ -163413,19 +163413,19 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -163508,7 +163508,7 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -163555,7 +163555,7 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ 2'b1?: { \o_ok$next , \o$next } = { \o_ok$21 , \o$20 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -163574,7 +163574,7 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ 2'b1?: { \full_cr_ok$next , \full_cr$5$next } = { \full_cr_ok$23 , \full_cr$22 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \full_cr_ok$next = 1'h0; @@ -163593,7 +163593,7 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ 2'b1?: { \cr_a_ok$next , \cr_a$6$next } = { \cr_a_ok$25 , \cr_a$24 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -163967,43 +163967,43 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i reg \br_op__lk$8 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg \br_op__lk$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [3:0] cr_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \fast1$10 ; reg [63:0] \fast1$10 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \fast1$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \fast1$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; reg fast1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fast1_ok$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \fast1_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \fast2$11 ; reg [63:0] \fast2$11 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \fast2$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \fast2$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast2_ok; reg fast2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fast2_ok$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \fast2_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [63:0] main_br_op__cia; @@ -164221,23 +164221,23 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i wire [3:0] main_cr_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] main_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \main_fast1$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_fast1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] main_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \main_fast2$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_fast2_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \main_muxid$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] main_nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_nia_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -164254,19 +164254,19 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] nia; reg [63:0] nia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \nia$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \nia$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output nia_ok; reg nia_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \nia_ok$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \nia_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -164362,7 +164362,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -164400,7 +164400,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: { \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -164422,7 +164422,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: { \fast1_ok$next , \fast1$10$next } = { \fast1_ok$36 , \fast1$35 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fast1_ok$next = 1'h0; @@ -164441,7 +164441,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: { \fast2_ok$next , \fast2$11$next } = { \fast2_ok$38 , \fast2$37 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fast2_ok$next = 1'h0; @@ -164460,7 +164460,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: { \nia_ok$next , \nia$next } = { \nia_ok$40 , \nia$39 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \nia_ok$next = 1'h0; @@ -164489,25 +164489,25 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \fast1$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \fast1$7 ; reg [63:0] \fast1$7 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \fast1$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; reg fast1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fast1_ok$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \fast1_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -164524,19 +164524,19 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -164554,41 +164554,41 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s input [63:0] ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \spr1$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \spr1$6 ; reg [63:0] \spr1$6 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \spr1$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spr1_ok; reg spr1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \spr1_ok$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \spr1_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] spr_main_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \spr_main_fast1$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire spr_main_fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] spr_main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \spr_main_muxid$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] spr_main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire spr_main_o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] spr_main_ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] spr_main_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \spr_main_spr1$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire spr_main_spr1_ok; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -164788,21 +164788,21 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s wire \spr_main_spr_op__is_32bit$15 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] spr_main_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \spr_main_xer_ca$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire spr_main_xer_ca_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] spr_main_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \spr_main_xer_ov$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire spr_main_xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire spr_main_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \spr_main_xer_so$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire spr_main_xer_so_ok; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -165112,51 +165112,51 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s reg \spr_op__is_32bit$5$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ca$10 ; reg [1:0] \xer_ca$10 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [1:0] \xer_ca$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \xer_ca$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; reg xer_ca_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ca_ok$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_ca_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \xer_ov$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ov$9 ; reg [1:0] \xer_ov$9 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [1:0] \xer_ov$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; reg xer_ov_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ov_ok$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_ov_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$8 ; reg \xer_so$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so_ok$next ; assign \$22 = \p_valid_i$21 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) @@ -165245,7 +165245,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -165293,7 +165293,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \o_ok$next , \o$next } = { \o_ok$30 , \o$29 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -165312,7 +165312,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \spr1_ok$next , \spr1$6$next } = { \spr1_ok$32 , \spr1$31 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \spr1_ok$next = 1'h0; @@ -165331,7 +165331,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \fast1_ok$next , \fast1$7$next } = { \fast1_ok$34 , \fast1$33 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fast1_ok$next = 1'h0; @@ -165350,7 +165350,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \xer_so_ok$next , \xer_so$8$next } = { \xer_so_ok$36 , \xer_so$35 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -165369,7 +165369,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \xer_ov_ok$next , \xer_ov$9$next } = { \xer_ov_ok$38 , \xer_ov$37 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -165388,7 +165388,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \xer_ca_ok$next , \xer_ca$10$next } = { \xer_ca_ok$40 , \xer_ca$39 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ca_ok$next = 1'h0; @@ -165867,23 +165867,23 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o wire \alu_op__zero_a$79 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg \alu_op__zero_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; reg [3:0] cr_a = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [3:0] \cr_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \cr_a_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [3:0] input_alu_op__data_len; @@ -166425,17 +166425,17 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o wire main_alu_op__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \main_alu_op__zero_a$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] main_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \main_muxid$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] main_ra; @@ -166443,17 +166443,17 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o wire [63:0] main_rb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] main_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \main_xer_ca$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] main_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire main_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \main_xer_so$65 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] muxid; @@ -166470,19 +166470,19 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -166500,53 +166500,53 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o input [63:0] ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ca; reg [1:0] xer_ca = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] \xer_ca$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \xer_ca$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [1:0] \xer_ca$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; reg xer_ca_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ca_ok$93 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_ca_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ov; reg [1:0] xer_ov = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \xer_ov$94 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [1:0] \xer_ov$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; reg xer_ov_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ov_ok$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_ov_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so; reg xer_so = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input \xer_so$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$97 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$98 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so_ok$next ; assign \$67 = \p_valid_i$66 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) @@ -166731,7 +166731,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$91 , \cr_a$90 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -166750,7 +166750,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$93 , \xer_ca$92 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ca_ok$next = 1'h0; @@ -166769,7 +166769,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$95 , \xer_ov$94 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -166788,7 +166788,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$97 , \xer_so$96 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -166806,7 +166806,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -166854,7 +166854,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -166880,7 +166880,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \o_ok$next , \o$next } = { \o_ok$89 , \o$88 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -166919,27 +166919,27 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; reg [3:0] cr_a = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [3:0] \cr_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \cr_a_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] input_muxid; @@ -167225,9 +167225,9 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \main_muxid$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] main_ra; @@ -167491,11 +167491,11 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, wire main_sr_op__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \main_sr_op__write_cr0$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] main_xer_ca; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire main_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \main_xer_so$62 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] muxid; @@ -167512,19 +167512,19 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -167979,43 +167979,43 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, wire \sr_op__write_cr0$76 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg \sr_op__write_cr0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ca; reg [1:0] xer_ca = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] \xer_ca$20 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] \xer_ca$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \xer_ca$94 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [1:0] \xer_ca$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; reg xer_ca_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ca_ok$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ca_ok$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_ca_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so; reg xer_so = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input \xer_so$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$93 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so_ok$next ; assign \$65 = \p_valid_i$64 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) @@ -168187,7 +168187,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$95 , \xer_ca$94 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ca_ok$next = 1'h0; @@ -168205,7 +168205,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -168252,7 +168252,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: { \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -168278,7 +168278,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -168297,7 +168297,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -168316,7 +168316,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -168359,9 +168359,9 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] dummy_fast1; @@ -169094,7 +169094,7 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -169655,29 +169655,29 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o reg \alu_op__zero_a$11$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \alu_op__zero_a$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] \cr_a$22 ; reg [3:0] \cr_a$22 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [3:0] \cr_a$22$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \cr_a_ok$23 ; reg \cr_a_ok$23 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \cr_a_ok$23$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$84 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -169694,23 +169694,23 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \o$20 ; reg [63:0] \o$20 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$20$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$21 ; reg \o_ok$21 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$21$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$82 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [3:0] output_alu_op__data_len; @@ -169972,41 +169972,41 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o wire output_alu_op__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \output_alu_op__zero_a$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] output_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \output_cr_a$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] output_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \output_muxid$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] output_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \output_o$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \output_o_ok$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] output_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \output_xer_ca$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] output_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \output_xer_ov$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \output_xer_so$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -170020,65 +170020,65 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ca$24 ; reg [1:0] \xer_ca$24 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [1:0] \xer_ca$24$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \xer_ca$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_ca_ok$25 ; reg \xer_ca_ok$25 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_ca_ok$25$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ca_ok$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ca_ok$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ov$26 ; reg [1:0] \xer_ov$26 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [1:0] \xer_ov$26$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \xer_ov$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_ov_ok$27 ; reg \xer_ov_ok$27 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_ov_ok$27$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ov_ok$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ov_ok$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$28 ; reg \xer_so$28 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so$28$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so_ok$29 ; reg \xer_so_ok$29 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so_ok$29$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$90 ; assign \$60 = \p_valid_i$59 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) @@ -170217,7 +170217,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -170265,7 +170265,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -170291,7 +170291,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \o_ok$21$next , \o$20$next } = { \o_ok$82 , \o$81 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$21$next = 1'h0; @@ -170310,7 +170310,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$84 , \cr_a$83 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$23$next = 1'h0; @@ -170329,7 +170329,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_ca_ok$25$next , \xer_ca$24$next } = { \xer_ca_ok$86 , \xer_ca$85 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ca_ok$25$next = 1'h0; @@ -170348,7 +170348,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_ov_ok$27$next , \xer_ov$26$next } = { \xer_ov_ok$88 , \xer_ov$87 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ov_ok$27$next = 1'h0; @@ -170367,7 +170367,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_so_ok$29$next , \xer_so$28$next } = { \xer_so_ok$90 , \xer_so$89 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$29$next = 1'h0; @@ -170400,29 +170400,29 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] \cr_a$21 ; reg [3:0] \cr_a$21 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [3:0] \cr_a$21$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \cr_a_ok$22 ; reg \cr_a_ok$22 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \cr_a_ok$22$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$74 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -170439,41 +170439,41 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \o$19 ; reg [63:0] \o$19 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$19$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \o_ok$20 ; reg \o_ok$20 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$20$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] output_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \output_cr_a$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] output_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \output_muxid$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] output_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \output_o$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \output_o_ok$44 ; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -170731,13 +170731,13 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, wire output_sr_op__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \output_sr_op__write_cr0$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] output_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \output_xer_ca$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_so; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -171186,31 +171186,31 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, reg \sr_op__write_cr0$10$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \sr_op__write_cr0$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ca$23 ; reg [1:0] \xer_ca$23 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [1:0] \xer_ca$23$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \xer_ca$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_ca_ok$24 ; reg \xer_ca_ok$24 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_ca_ok$24$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ca_ok$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ca_ok$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$48 ; assign \$51 = \p_valid_i$50 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) @@ -171332,7 +171332,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -171379,7 +171379,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: { \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -171405,7 +171405,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: { \o_ok$20$next , \o$19$next } = { \o_ok$72 , \o$71 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$20$next = 1'h0; @@ -171424,7 +171424,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: { \cr_a_ok$22$next , \cr_a$21$next } = { \cr_a_ok$74 , \cr_a$73 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$22$next = 1'h0; @@ -171443,7 +171443,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: { \xer_ca_ok$24$next , \xer_ca$23$next } = { \xer_ca_ok$76 , \xer_ca$75 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ca_ok$24$next = 1'h0; @@ -171473,69 +171473,69 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \fast1$11 ; reg [63:0] \fast1$11 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \fast1$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \fast1$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; reg fast1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fast1_ok$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \fast1_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \fast2$12 ; reg [63:0] \fast2$12 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \fast2$12$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \fast2$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast2_ok; reg fast2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \fast2_ok$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \fast2_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] main_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \main_fast1$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_fast1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] main_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \main_fast2$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] main_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_msr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \main_muxid$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] main_nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire main_o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] main_ra; @@ -171757,19 +171757,19 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, wire [7:0] main_trap_op__traptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [7:0] \main_trap_op__traptype$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] msr; reg [63:0] msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \msr$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \msr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output msr_ok; reg msr_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \msr_ok$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \msr_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -171786,33 +171786,33 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] nia; reg [63:0] nia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \nia$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \nia$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output nia_ok; reg nia_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \nia_ok$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \nia_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -172280,7 +172280,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -172333,7 +172333,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: { \o_ok$next , \o$next } = { \o_ok$39 , \o$38 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -172352,7 +172352,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: { \fast1_ok$next , \fast1$11$next } = { \fast1_ok$41 , \fast1$40 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fast1_ok$next = 1'h0; @@ -172371,7 +172371,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: { \fast2_ok$next , \fast2$12$next } = { \fast2_ok$43 , \fast2$42 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fast2_ok$next = 1'h0; @@ -172390,7 +172390,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: { \nia_ok$next , \nia$next } = { \nia_ok$45 , \nia$44 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \nia_ok$next = 1'h0; @@ -172409,7 +172409,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: { \msr_ok$next , \msr$next } = { \msr_ok$47 , \msr$46 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \msr_ok$next = 1'h0; @@ -172441,29 +172441,29 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [3:0] cr_a; reg [3:0] cr_a = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \cr_a$97 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [3:0] \cr_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \cr_a_ok$98 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \cr_a_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) input div_by_zero; @@ -172934,25 +172934,25 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \o$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \o_ok$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \o_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] output_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] \output_cr_a$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire [3:0] output_logical_op__data_len; @@ -173218,13 +173218,13 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type wire [1:0] output_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \output_muxid$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] output_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \output_o$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \output_o_ok$61 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) wire output_stage_div_by_zero; @@ -173500,33 +173500,33 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type wire [1:0] output_stage_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] \output_stage_muxid$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] output_stage_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_stage_o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) wire [63:0] output_stage_quotient_root; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) wire [191:0] output_stage_remainder; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] output_stage_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_stage_xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire output_stage_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \output_stage_xer_so$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] output_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \output_xer_ov$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \output_xer_so$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire output_xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; @@ -173552,41 +173552,41 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type wire [63:0] \rb$66 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) input [191:0] remainder; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] xer_ov; reg [1:0] xer_ov = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] \xer_ov$99 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [1:0] \xer_ov$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; reg xer_ov_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ov_ok$100 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_ov_ok$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_ov_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so$101 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$20 ; reg \xer_so$20 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so$20$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$102 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \xer_so_ok$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \xer_so_ok$next ; assign \$74 = \p_valid_i$73 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) @@ -173772,7 +173772,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: { \o_ok$next , \o$next } = { \o_ok$96 , \o$95 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -173791,7 +173791,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$98 , \cr_a$97 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -173810,7 +173810,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$100 , \xer_ov$99 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -173829,7 +173829,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: { \xer_so_ok$next , \xer_so$20$next } = { \xer_so_ok$102 , \xer_so$101 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -173847,7 +173847,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -173895,7 +173895,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -173958,9 +173958,9 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn wire \$63 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) wire \$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) input div_by_zero; @@ -174613,7 +174613,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn always @* begin if (\initial ) begin end \saved_state_q_bits_known$next = div_state_next_o_q_bits_known; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \saved_state_q_bits_known$next = 7'h00; @@ -174622,7 +174622,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn always @* begin if (\initial ) begin end \saved_state_dividend_quotient$next = div_state_next_o_dividend_quotient; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \saved_state_dividend_quotient$next = 128'h00000000000000000000000000000000; @@ -174690,7 +174690,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn \empty$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \empty$next = 1'h1; @@ -174742,7 +174742,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn { \logical_op__insn$46$next , \logical_op__data_len$45$next , \logical_op__is_signed$44$next , \logical_op__is_32bit$43$next , \logical_op__output_carry$42$next , \logical_op__write_cr0$41$next , \logical_op__invert_out$40$next , \logical_op__input_carry$39$next , \logical_op__zero_a$38$next , \logical_op__invert_in$37$next , \logical_op__oe__ok$36$next , \logical_op__oe__oe$35$next , \logical_op__rc__ok$34$next , \logical_op__rc__rc$33$next , \logical_op__imm_data__ok$32$next , \logical_op__imm_data__data$31$next , \logical_op__fn_unit$30$next , \logical_op__insn_type$29$next } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -174943,9 +174943,9 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) output div_by_zero; @@ -176354,7 +176354,7 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -176402,7 +176402,7 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty 2'b1?: { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -177843,9 +177843,9 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest10__data_i; @@ -177959,7 +177959,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src10__data_o$next = 4'h0; @@ -178016,7 +178016,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, 1'h1: \reg$next = w0__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -178056,7 +178056,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src20__data_o$next = 4'h0; @@ -178126,7 +178126,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src30__data_o$next = 4'h0; @@ -178196,7 +178196,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r0__data_o$next = 4'h0; @@ -178266,7 +178266,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r20__data_o$next = 4'h0; @@ -178316,9 +178316,9 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest10__data_i; @@ -178430,7 +178430,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src10__data_o$next = 2'h0; @@ -178512,7 +178512,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src20__data_o$next = 2'h0; @@ -178594,7 +178594,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src30__data_o$next = 2'h0; @@ -178676,7 +178676,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r0__data_o$next = 2'h0; @@ -178745,7 +178745,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d 1'h1: \reg$next = w0__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 2'h0; @@ -178770,9 +178770,9 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ reg [63:0] \cia0__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia0__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr10__data_i; @@ -178865,7 +178865,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cia0__data_o$next = 64'h0000000000000000; @@ -178947,7 +178947,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \msr0__data_o$next = 64'h0000000000000000; @@ -179029,7 +179029,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \sv0__data_o$next = 64'h0000000000000000; @@ -179098,7 +179098,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ 1'h1: \reg$next = d_wr10__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 64'h0000000000000000; @@ -179120,9 +179120,9 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest11__data_i; @@ -179236,7 +179236,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src11__data_o$next = 4'h0; @@ -179293,7 +179293,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, 1'h1: \reg$next = w1__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -179333,7 +179333,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src21__data_o$next = 4'h0; @@ -179403,7 +179403,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src31__data_o$next = 4'h0; @@ -179473,7 +179473,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r1__data_o$next = 4'h0; @@ -179543,7 +179543,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r21__data_o$next = 4'h0; @@ -179593,9 +179593,9 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest11__data_i; @@ -179707,7 +179707,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src11__data_o$next = 2'h0; @@ -179789,7 +179789,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src21__data_o$next = 2'h0; @@ -179871,7 +179871,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src31__data_o$next = 2'h0; @@ -179953,7 +179953,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r1__data_o$next = 2'h0; @@ -180022,7 +180022,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d 1'h1: \reg$next = w1__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 2'h0; @@ -180047,9 +180047,9 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ reg [63:0] \cia1__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia1__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr11__data_i; @@ -180142,7 +180142,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cia1__data_o$next = 64'h0000000000000000; @@ -180224,7 +180224,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \msr1__data_o$next = 64'h0000000000000000; @@ -180306,7 +180306,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \sv1__data_o$next = 64'h0000000000000000; @@ -180375,7 +180375,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ 1'h1: \reg$next = d_wr11__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 64'h0000000000000000; @@ -180397,9 +180397,9 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest12__data_i; @@ -180513,7 +180513,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src12__data_o$next = 4'h0; @@ -180570,7 +180570,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, 1'h1: \reg$next = w2__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -180610,7 +180610,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src22__data_o$next = 4'h0; @@ -180680,7 +180680,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src32__data_o$next = 4'h0; @@ -180750,7 +180750,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r2__data_o$next = 4'h0; @@ -180820,7 +180820,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r22__data_o$next = 4'h0; @@ -180870,9 +180870,9 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest12__data_i; @@ -180984,7 +180984,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src12__data_o$next = 2'h0; @@ -181066,7 +181066,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src22__data_o$next = 2'h0; @@ -181148,7 +181148,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src32__data_o$next = 2'h0; @@ -181230,7 +181230,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r2__data_o$next = 2'h0; @@ -181299,7 +181299,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d 1'h1: \reg$next = w2__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 2'h0; @@ -181324,9 +181324,9 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ reg [63:0] \cia2__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia2__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr12__data_i; @@ -181419,7 +181419,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cia2__data_o$next = 64'h0000000000000000; @@ -181501,7 +181501,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \msr2__data_o$next = 64'h0000000000000000; @@ -181583,7 +181583,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \sv2__data_o$next = 64'h0000000000000000; @@ -181652,7 +181652,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ 1'h1: \reg$next = d_wr12__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 64'h0000000000000000; @@ -181674,9 +181674,9 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest13__data_i; @@ -181790,7 +181790,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src13__data_o$next = 4'h0; @@ -181847,7 +181847,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, 1'h1: \reg$next = w3__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -181887,7 +181887,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src23__data_o$next = 4'h0; @@ -181957,7 +181957,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src33__data_o$next = 4'h0; @@ -182027,7 +182027,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r3__data_o$next = 4'h0; @@ -182097,7 +182097,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r23__data_o$next = 4'h0; @@ -182149,9 +182149,9 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest14__data_i; @@ -182265,7 +182265,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src14__data_o$next = 4'h0; @@ -182322,7 +182322,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, 1'h1: \reg$next = w4__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -182362,7 +182362,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src24__data_o$next = 4'h0; @@ -182432,7 +182432,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src34__data_o$next = 4'h0; @@ -182502,7 +182502,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r4__data_o$next = 4'h0; @@ -182572,7 +182572,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r24__data_o$next = 4'h0; @@ -182624,9 +182624,9 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest15__data_i; @@ -182740,7 +182740,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src15__data_o$next = 4'h0; @@ -182797,7 +182797,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, 1'h1: \reg$next = w5__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -182837,7 +182837,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src25__data_o$next = 4'h0; @@ -182907,7 +182907,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src35__data_o$next = 4'h0; @@ -182977,7 +182977,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r5__data_o$next = 4'h0; @@ -183047,7 +183047,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r25__data_o$next = 4'h0; @@ -183099,9 +183099,9 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest16__data_i; @@ -183215,7 +183215,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src16__data_o$next = 4'h0; @@ -183272,7 +183272,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, 1'h1: \reg$next = w6__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -183312,7 +183312,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src26__data_o$next = 4'h0; @@ -183382,7 +183382,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src36__data_o$next = 4'h0; @@ -183452,7 +183452,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r6__data_o$next = 4'h0; @@ -183522,7 +183522,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r26__data_o$next = 4'h0; @@ -183574,9 +183574,9 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest17__data_i; @@ -183690,7 +183690,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src17__data_o$next = 4'h0; @@ -183747,7 +183747,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, 1'h1: \reg$next = w7__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -183787,7 +183787,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src27__data_o$next = 4'h0; @@ -183857,7 +183857,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src37__data_o$next = 4'h0; @@ -183927,7 +183927,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r7__data_o$next = 4'h0; @@ -183997,7 +183997,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r27__data_o$next = 4'h0; @@ -184055,9 +184055,9 @@ module req_l(coresync_rst, q_req, s_req, r_req, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -184086,7 +184086,7 @@ module req_l(coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 5'h00; @@ -184117,9 +184117,9 @@ module \req_l$103 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -184148,7 +184148,7 @@ module \req_l$103 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -184179,9 +184179,9 @@ module \req_l$12 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -184210,7 +184210,7 @@ module \req_l$12 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -184241,9 +184241,9 @@ module \req_l$121 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -184272,7 +184272,7 @@ module \req_l$121 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -184303,9 +184303,9 @@ module \req_l$25 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -184334,7 +184334,7 @@ module \req_l$25 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -184365,9 +184365,9 @@ module \req_l$41 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -184396,7 +184396,7 @@ module \req_l$41 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 5'h00; @@ -184427,9 +184427,9 @@ module \req_l$57 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [1:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [1:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [1:0] q_int = 2'h0; @@ -184458,7 +184458,7 @@ module \req_l$57 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 2'h0; @@ -184489,9 +184489,9 @@ module \req_l$69 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -184520,7 +184520,7 @@ module \req_l$69 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 6'h00; @@ -184551,9 +184551,9 @@ module \req_l$86 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -184582,7 +184582,7 @@ module \req_l$86 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -184607,9 +184607,9 @@ module reset_l(coresync_rst, s_reset, r_reset, q_reset, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -184635,7 +184635,7 @@ module reset_l(coresync_rst, s_reset, r_reset, q_reset, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -184660,9 +184660,9 @@ module \reset_l$131 (coresync_rst, s_reset, r_reset, q_reset, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -184688,7 +184688,7 @@ module \reset_l$131 (coresync_rst, s_reset, r_reset, q_reset, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185310,9 +185310,9 @@ module rok_l(coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185341,7 +185341,7 @@ module rok_l(coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185372,9 +185372,9 @@ module \rok_l$105 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185403,7 +185403,7 @@ module \rok_l$105 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185434,9 +185434,9 @@ module \rok_l$123 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185465,7 +185465,7 @@ module \rok_l$123 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185496,9 +185496,9 @@ module \rok_l$14 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185527,7 +185527,7 @@ module \rok_l$14 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185558,9 +185558,9 @@ module \rok_l$27 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185589,7 +185589,7 @@ module \rok_l$27 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185620,9 +185620,9 @@ module \rok_l$43 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185651,7 +185651,7 @@ module \rok_l$43 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185682,9 +185682,9 @@ module \rok_l$59 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185713,7 +185713,7 @@ module \rok_l$59 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185744,9 +185744,9 @@ module \rok_l$71 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185775,7 +185775,7 @@ module \rok_l$71 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185806,9 +185806,9 @@ module \rok_l$88 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185837,7 +185837,7 @@ module \rok_l$88 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186258,9 +186258,9 @@ module rst_l(coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186289,7 +186289,7 @@ module rst_l(coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186320,9 +186320,9 @@ module \rst_l$104 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186351,7 +186351,7 @@ module \rst_l$104 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186382,9 +186382,9 @@ module \rst_l$122 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186413,7 +186413,7 @@ module \rst_l$122 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186444,9 +186444,9 @@ module \rst_l$129 (coresync_rst, s_rst, r_rst, q_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186475,7 +186475,7 @@ module \rst_l$129 (coresync_rst, s_rst, r_rst, q_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186506,9 +186506,9 @@ module \rst_l$13 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186537,7 +186537,7 @@ module \rst_l$13 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186568,9 +186568,9 @@ module \rst_l$26 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186599,7 +186599,7 @@ module \rst_l$26 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186630,9 +186630,9 @@ module \rst_l$42 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186661,7 +186661,7 @@ module \rst_l$42 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186692,9 +186692,9 @@ module \rst_l$58 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186723,7 +186723,7 @@ module \rst_l$58 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186754,9 +186754,9 @@ module \rst_l$70 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186785,7 +186785,7 @@ module \rst_l$70 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186816,9 +186816,9 @@ module \rst_l$87 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186847,7 +186847,7 @@ module \rst_l$87 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -187424,13 +187424,13 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif wire alu_pulse; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) wire [2:0] alu_pulsem; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [3:0] alu_shift_rot0_cr_a; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_shift_rot0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_shift_rot0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_shift_rot0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_shift_rot0_p_ready_o; @@ -187604,7 +187604,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif reg alu_shift_rot0_sr_op__write_cr0 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg \alu_shift_rot0_sr_op__write_cr0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] alu_shift_rot0_xer_ca; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] \alu_shift_rot0_xer_ca$1 ; @@ -187618,11 +187618,11 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -187679,7 +187679,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [1:0] dest3_o; reg [1:0] dest3_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -187907,7 +187907,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif wire src_sel; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; assign \$100 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; assign \$102 = \$98 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$100 ; @@ -188151,7 +188151,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -188160,7 +188160,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$64 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -188169,7 +188169,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -188178,7 +188178,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -188187,7 +188187,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -188196,7 +188196,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -188205,7 +188205,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 5'h00; @@ -188214,7 +188214,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 5'h1f; @@ -188223,7 +188223,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \req_l_s_req$next = \$66 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 3'h0; @@ -188232,7 +188232,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \req_l_r_req$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 3'h7; @@ -188263,7 +188263,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \alu_shift_rot0_sr_op__insn$next , \alu_shift_rot0_sr_op__is_signed$next , \alu_shift_rot0_sr_op__is_32bit$next , \alu_shift_rot0_sr_op__output_cr$next , \alu_shift_rot0_sr_op__input_cr$next , \alu_shift_rot0_sr_op__output_carry$next , \alu_shift_rot0_sr_op__input_carry$next , \alu_shift_rot0_sr_op__invert_in$next , \alu_shift_rot0_sr_op__write_cr0$next , \alu_shift_rot0_sr_op__oe__ok$next , \alu_shift_rot0_sr_op__oe__oe$next , \alu_shift_rot0_sr_op__rc__ok$next , \alu_shift_rot0_sr_op__rc__rc$next , \alu_shift_rot0_sr_op__imm_data__ok$next , \alu_shift_rot0_sr_op__imm_data__data$next , \alu_shift_rot0_sr_op__fn_unit$next , \alu_shift_rot0_sr_op__insn_type$next } = { oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -188292,7 +188292,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -188314,7 +188314,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -188336,7 +188336,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \data_r2__xer_ca_ok$next , \data_r2__xer_ca$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__xer_ca_ok$next = 1'h0; @@ -188395,7 +188395,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$90 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -188404,7 +188404,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$92 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -188443,7 +188443,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \prev_wr_go$next = \$20 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 3'h0; @@ -188487,23 +188487,23 @@ endmodule (* generator = "nMigen" *) module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr1__addr$1 , spr1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [3:0] memory_r_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [63:0] memory_r_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [3:0] memory_w_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [63:0] memory_w_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire memory_w_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg ren_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] spr1__addr; @@ -188543,7 +188543,7 @@ module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr always @* begin if (\initial ) begin end \ren_delay$next = spr1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 1'h0; @@ -188552,9 +188552,9 @@ module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr always @* begin if (\initial ) begin end spr1__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" *) casez (ren_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" */ 1'h1: spr1__data_o = memory_r_data; endcase @@ -188731,7 +188731,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, wire alu_pulse; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) wire [5:0] alu_pulsem; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_spr0_fast1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] \alu_spr0_fast1$2 ; @@ -188739,7 +188739,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, wire alu_spr0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_spr0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_spr0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_spr0_p_ready_o; @@ -188747,7 +188747,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, wire alu_spr0_p_valid_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] alu_spr0_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_spr0_spr1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] \alu_spr0_spr1$1 ; @@ -188857,15 +188857,15 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, reg alu_spr0_spr_op__is_32bit = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg \alu_spr0_spr_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] alu_spr0_xer_ca; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] \alu_spr0_xer_ca$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [1:0] alu_spr0_xer_ov; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [1:0] \alu_spr0_xer_ov$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire alu_spr0_xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire \alu_spr0_xer_so$3 ; @@ -188877,9 +188877,9 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -188969,9 +188969,9 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [1:0] dest6_o; reg [1:0] dest6_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -189123,7 +189123,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, reg \rst_l_s_rst$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) wire rst_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spr1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [63:0] src1_i; @@ -189173,11 +189173,11 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, reg [1:0] \src_r5$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; assign \$100 = alu_spr0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; @@ -189410,7 +189410,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -189419,7 +189419,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -189428,7 +189428,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -189437,7 +189437,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -189446,7 +189446,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -189455,7 +189455,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -189464,7 +189464,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 6'h00; @@ -189473,7 +189473,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 6'h3f; @@ -189482,7 +189482,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$70 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 6'h00; @@ -189491,7 +189491,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$72 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 6'h3f; @@ -189526,7 +189526,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -189548,7 +189548,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r1__spr1_ok$next , \data_r1__spr1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__spr1_ok$next = 1'h0; @@ -189570,7 +189570,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r2__fast1_ok$next , \data_r2__fast1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__fast1_ok$next = 1'h0; @@ -189592,7 +189592,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r3__xer_so_ok$next = 1'h0; @@ -189614,7 +189614,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r4__xer_ov_ok$next , \data_r4__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r4__xer_ov_ok$next = 1'h0; @@ -189636,7 +189636,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r5__xer_ca_ok$next , \data_r5__xer_ca$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r5__xer_ca_ok$next = 1'h0; @@ -189705,7 +189705,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$98 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -189714,7 +189714,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$100 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -189783,7 +189783,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$24 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 6'h00; @@ -189842,20 +189842,20 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b wire \$23 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \fast1$7 ; reg [63:0] \fast1$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; reg fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; reg o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) @@ -189864,10 +189864,10 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b wire [9:0] spr; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [63:0] \spr1$6 ; reg [63:0] \spr1$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spr1_ok; reg spr1_ok; (* enum_base_type = "Function" *) @@ -190068,26 +190068,26 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b output \spr_op__is_32bit$5 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ca$10 ; reg [1:0] \xer_ca$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ca_ok; reg xer_ca_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [1:0] \xer_ov$9 ; reg [1:0] \xer_ov$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_ov_ok; reg xer_ov_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output \xer_so$8 ; reg \xer_so$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output xer_so_ok; reg xer_so_ok; assign \$11 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; @@ -190357,13 +190357,13 @@ endmodule (* generator = "nMigen" *) module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] fast_o; reg [2:0] fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast_o_ok; reg fast_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:75" *) input [9:0] spr_i; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -190479,330 +190479,330 @@ module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [9:0] spr_o; reg [9:0] spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spr_o_ok; reg spr_o_ok; always @* begin if (\initial ) begin end fast_o = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: fast_o = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: fast_o = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: fast_o = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: fast_o = 3'h6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: fast_o = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: fast_o = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: fast_o = 3'h7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: fast_o = 3'h2; endcase @@ -190810,321 +190810,321 @@ module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end fast_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: fast_o_ok = 1'h1; endcase @@ -191132,345 +191132,345 @@ module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end spr_o = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: spr_o = 10'h001; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: spr_o = 10'h004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: spr_o = 10'h005; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: spr_o = 10'h006; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: spr_o = 10'h007; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: spr_o = 10'h00b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: spr_o = 10'h00c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: spr_o = 10'h00d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: spr_o = 10'h00e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: spr_o = 10'h00f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: spr_o = 10'h010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: spr_o = 10'h011; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: spr_o = 10'h012; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: spr_o = 10'h013; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: spr_o = 10'h014; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: spr_o = 10'h015; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: spr_o = 10'h016; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: spr_o = 10'h017; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: spr_o = 10'h018; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: spr_o = 10'h019; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: spr_o = 10'h01a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: spr_o = 10'h01b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: spr_o = 10'h01c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: spr_o = 10'h01d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: spr_o = 10'h01e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: spr_o = 10'h01f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: spr_o = 10'h020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: spr_o = 10'h021; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: spr_o = 10'h023; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: spr_o = 10'h024; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: spr_o = 10'h025; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: spr_o = 10'h026; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: spr_o = 10'h027; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: spr_o = 10'h028; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: spr_o = 10'h029; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: spr_o = 10'h02a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: spr_o = 10'h02b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: spr_o = 10'h02c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: spr_o = 10'h02d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: spr_o = 10'h02e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: spr_o = 10'h02f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: spr_o = 10'h030; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: spr_o = 10'h031; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: spr_o = 10'h032; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: spr_o = 10'h033; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: spr_o = 10'h034; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: spr_o = 10'h035; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: spr_o = 10'h036; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: spr_o = 10'h037; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: spr_o = 10'h038; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: spr_o = 10'h039; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: spr_o = 10'h03a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: spr_o = 10'h03b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: spr_o = 10'h03c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: spr_o = 10'h03d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: spr_o = 10'h03e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: spr_o = 10'h03f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: spr_o = 10'h040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: spr_o = 10'h041; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d1: spr_o = 10'h042; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: spr_o = 10'h043; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: spr_o = 10'h044; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: spr_o = 10'h045; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: spr_o = 10'h046; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: spr_o = 10'h047; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: spr_o = 10'h048; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: spr_o = 10'h049; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: spr_o = 10'h04a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: spr_o = 10'h04b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: spr_o = 10'h04c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: spr_o = 10'h04d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: spr_o = 10'h04e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: spr_o = 10'h04f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: spr_o = 10'h050; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: spr_o = 10'h051; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: spr_o = 10'h052; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: spr_o = 10'h053; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: spr_o = 10'h054; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: spr_o = 10'h055; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: spr_o = 10'h056; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: spr_o = 10'h057; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: spr_o = 10'h058; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: spr_o = 10'h059; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: spr_o = 10'h05a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: spr_o = 10'h05b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: spr_o = 10'h05c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: spr_o = 10'h05d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: spr_o = 10'h05e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: spr_o = 10'h05f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: spr_o = 10'h060; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: spr_o = 10'h061; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: spr_o = 10'h062; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: spr_o = 10'h063; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: spr_o = 10'h064; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: spr_o = 10'h065; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: spr_o = 10'h066; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: spr_o = 10'h067; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h330: spr_o = 10'h069; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h337: spr_o = 10'h06a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h350: spr_o = 10'h06b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h351: spr_o = 10'h06c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h357: spr_o = 10'h06d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h380: spr_o = 10'h06e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h382: spr_o = 10'h06f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h3ff: spr_o = 10'h070; endcase @@ -191478,345 +191478,345 @@ module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end spr_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d1: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h330: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h337: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h350: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h351: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h357: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h380: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h382: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h3ff: spr_o_ok = 1'h1; endcase @@ -191827,13 +191827,13 @@ endmodule (* generator = "nMigen" *) module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [2:0] fast_o; reg [2:0] fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast_o_ok; reg fast_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:75" *) input [9:0] spr_i; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -191949,330 +191949,330 @@ module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output [9:0] spr_o; reg [9:0] spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output spr_o_ok; reg spr_o_ok; always @* begin if (\initial ) begin end fast_o = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: fast_o = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: fast_o = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: fast_o = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: fast_o = 3'h6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: fast_o = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: fast_o = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: fast_o = 3'h7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: fast_o = 3'h2; endcase @@ -192280,321 +192280,321 @@ module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end fast_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: fast_o_ok = 1'h1; endcase @@ -192602,345 +192602,345 @@ module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end spr_o = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: spr_o = 10'h001; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: spr_o = 10'h004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: spr_o = 10'h005; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: spr_o = 10'h006; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: spr_o = 10'h007; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: spr_o = 10'h00b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: spr_o = 10'h00c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: spr_o = 10'h00d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: spr_o = 10'h00e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: spr_o = 10'h00f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: spr_o = 10'h010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: spr_o = 10'h011; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: spr_o = 10'h012; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: spr_o = 10'h013; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: spr_o = 10'h014; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: spr_o = 10'h015; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: spr_o = 10'h016; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: spr_o = 10'h017; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: spr_o = 10'h018; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: spr_o = 10'h019; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: spr_o = 10'h01a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: spr_o = 10'h01b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: spr_o = 10'h01c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: spr_o = 10'h01d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: spr_o = 10'h01e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: spr_o = 10'h01f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: spr_o = 10'h020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: spr_o = 10'h021; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: spr_o = 10'h023; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: spr_o = 10'h024; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: spr_o = 10'h025; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: spr_o = 10'h026; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: spr_o = 10'h027; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: spr_o = 10'h028; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: spr_o = 10'h029; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: spr_o = 10'h02a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: spr_o = 10'h02b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: spr_o = 10'h02c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: spr_o = 10'h02d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: spr_o = 10'h02e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: spr_o = 10'h02f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: spr_o = 10'h030; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: spr_o = 10'h031; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: spr_o = 10'h032; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: spr_o = 10'h033; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: spr_o = 10'h034; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: spr_o = 10'h035; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: spr_o = 10'h036; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: spr_o = 10'h037; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: spr_o = 10'h038; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: spr_o = 10'h039; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: spr_o = 10'h03a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: spr_o = 10'h03b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: spr_o = 10'h03c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: spr_o = 10'h03d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: spr_o = 10'h03e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: spr_o = 10'h03f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: spr_o = 10'h040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: spr_o = 10'h041; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d1: spr_o = 10'h042; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: spr_o = 10'h043; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: spr_o = 10'h044; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: spr_o = 10'h045; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: spr_o = 10'h046; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: spr_o = 10'h047; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: spr_o = 10'h048; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: spr_o = 10'h049; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: spr_o = 10'h04a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: spr_o = 10'h04b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: spr_o = 10'h04c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: spr_o = 10'h04d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: spr_o = 10'h04e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: spr_o = 10'h04f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: spr_o = 10'h050; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: spr_o = 10'h051; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: spr_o = 10'h052; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: spr_o = 10'h053; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: spr_o = 10'h054; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: spr_o = 10'h055; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: spr_o = 10'h056; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: spr_o = 10'h057; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: spr_o = 10'h058; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: spr_o = 10'h059; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: spr_o = 10'h05a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: spr_o = 10'h05b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: spr_o = 10'h05c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: spr_o = 10'h05d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: spr_o = 10'h05e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: spr_o = 10'h05f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: spr_o = 10'h060; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: spr_o = 10'h061; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: spr_o = 10'h062; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: spr_o = 10'h063; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: spr_o = 10'h064; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: spr_o = 10'h065; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: spr_o = 10'h066; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: spr_o = 10'h067; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h330: spr_o = 10'h069; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h337: spr_o = 10'h06a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h350: spr_o = 10'h06b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h351: spr_o = 10'h06c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h357: spr_o = 10'h06d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h380: spr_o = 10'h06e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h382: spr_o = 10'h06f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h3ff: spr_o = 10'h070; endcase @@ -192948,345 +192948,345 @@ module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end spr_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d1: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h330: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h337: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h350: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h351: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h357: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h380: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h382: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h3ff: spr_o_ok = 1'h1; endcase @@ -193313,9 +193313,9 @@ module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -193344,7 +193344,7 @@ module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -193375,9 +193375,9 @@ module \src_l$10 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -193406,7 +193406,7 @@ module \src_l$10 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 6'h00; @@ -193437,9 +193437,9 @@ module \src_l$101 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -193468,7 +193468,7 @@ module \src_l$101 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -193499,9 +193499,9 @@ module \src_l$119 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -193530,7 +193530,7 @@ module \src_l$119 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 5'h00; @@ -193561,9 +193561,9 @@ module \src_l$127 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -193592,7 +193592,7 @@ module \src_l$127 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -193623,9 +193623,9 @@ module \src_l$23 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -193654,7 +193654,7 @@ module \src_l$23 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -193685,9 +193685,9 @@ module \src_l$39 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -193716,7 +193716,7 @@ module \src_l$39 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -193747,9 +193747,9 @@ module \src_l$55 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -193778,7 +193778,7 @@ module \src_l$55 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -193809,9 +193809,9 @@ module \src_l$67 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -193840,7 +193840,7 @@ module \src_l$67 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 6'h00; @@ -193871,9 +193871,9 @@ module \src_l$84 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -193902,7 +193902,7 @@ module \src_l$84 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -193933,9 +193933,9 @@ module st_active(coresync_rst, r_st_active, s_st_active, q_st_active, coresync_c wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -193964,7 +193964,7 @@ module st_active(coresync_rst, r_st_active, s_st_active, q_st_active, coresync_c always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -193995,9 +193995,9 @@ module st_done(coresync_rst, s_st_done, r_st_done, q_st_done, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -194026,7 +194026,7 @@ module st_done(coresync_rst, s_st_done, r_st_done, q_st_done, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -194064,9 +194064,9 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data reg [63:0] cia__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] cia__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] data_i; @@ -194165,17 +194165,17 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data wire reg_2_sv2__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire reg_2_sv2__wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] ren_delay = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$12 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$12$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$19 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$19$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] state_nia_wen; @@ -194262,7 +194262,7 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data always @* begin if (\initial ) begin end \ren_delay$19$next = sv__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$19$next = 3'h0; @@ -194271,9 +194271,9 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data always @* begin if (\initial ) begin end sv__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$20 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: sv__data_o = \$24 ; endcase @@ -194281,7 +194281,7 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data always @* begin if (\initial ) begin end \ren_delay$next = cia__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 3'h0; @@ -194290,9 +194290,9 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data always @* begin if (\initial ) begin end cia__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$6 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: cia__data_o = \$10 ; endcase @@ -194300,7 +194300,7 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data always @* begin if (\initial ) begin end \ren_delay$12$next = msr__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$12$next = 3'h0; @@ -194309,9 +194309,9 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data always @* begin if (\initial ) begin end msr__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$13 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: msr__data_o = \$17 ; endcase @@ -194357,9 +194357,9 @@ module sto_l(coresync_rst, s_sto, r_sto, q_sto, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -194388,7 +194388,7 @@ module sto_l(coresync_rst, s_sto, r_sto, q_sto, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -194411,11 +194411,11 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t output TAP_bus__tdo; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) output busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) input core_bigendian_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -194703,25 +194703,25 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t input ics_wb__we; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *) input [15:0] int_level_i; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) input jtag_wb__ack; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output [29:0] jtag_wb__adr; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__cyc; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) input [31:0] jtag_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output [31:0] jtag_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) input jtag_wb__err; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output [3:0] jtag_wb__sel; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__stb; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *) input memerr_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input mspi0_clk__core__o; @@ -194755,13 +194755,13 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t output mtwi_sda__pad__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output mtwi_sda__pad__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] pc_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input pc_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" *) output [63:0] pc_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -195047,7 +195047,7 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t input sdr_we_n__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output sdr_we_n__pad__o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) wire ti_coresync_clk; ti ti ( .TAP_bus__tck(TAP_bus__tck), @@ -195368,275 +195368,263 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti" *) (* generator = "nMigen" *) -module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__cyc, jtag_wb__we, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, coresync_clk); +module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$100 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) wire \$102 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) wire [64:0] \$104 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) wire [64:0] \$105 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *) wire [31:0] \$107 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) wire [6:0] \$108 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *) wire [31:0] \$111 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) wire [64:0] \$112 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) wire [64:0] \$113 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) wire [6:0] \$115 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$118 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$122 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$124 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$126 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$128 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) wire \$130 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$132 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$134 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) wire [7:0] \$136 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) wire [7:0] \$137 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) wire [7:0] \$139 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) wire [7:0] \$140 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$142 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$144 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$146 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$148 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$150 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) wire \$154 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) wire \$156 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" *) wire \$158 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$160 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$162 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$164 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) wire \$166 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$168 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$170 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$172 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$174 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$176 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$178 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$180 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$182 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$184 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$186 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$188 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$190 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$192 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$194 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) wire \$196 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - wire \$198 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:842" *) + wire [2:0] \$197 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$200 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$202 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$204 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$206 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$208 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) - wire [2:0] \$209 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) + wire \$210 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) wire \$212 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$214 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$216 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$218 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$220 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$222 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$224 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$226 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$228 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) wire \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) wire \$230 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - wire \$232 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:840" *) + wire [2:0] \$231 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) wire \$234 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) wire \$236 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) wire \$238 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$240 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$242 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) - wire [2:0] \$243 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) + wire \$244 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$246 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$248 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:905" *) wire \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$250 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" *) wire \$252 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) - wire \$254 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) + wire [63:0] \$254 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:837" *) wire \$256 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) wire \$258 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) wire \$260 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) - wire \$262 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:700" *) - wire \$264 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) - wire [63:0] \$266 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *) - wire \$268 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] \$262 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] \$264 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" *) + wire [64:0] \$266 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" *) + wire [64:0] \$267 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1141" *) + wire [64:0] \$269 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:906" *) wire [2:0] \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) - wire \$270 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) - wire \$272 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - wire [63:0] \$274 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - wire [63:0] \$276 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *) - wire [64:0] \$278 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *) - wire [64:0] \$279 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1141" *) + wire [64:0] \$270 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:906" *) wire [2:0] \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *) - wire [64:0] \$281 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *) - wire [64:0] \$282 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" *) wire \$34 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$36 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) - wire \$40 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) - wire \$48 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) wire \$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) wire \$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] \$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) wire \$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) wire \$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) wire \$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) wire \$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) wire \$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) wire \$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) wire \$94 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) wire \$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$98 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tck; @@ -195646,15 +195634,15 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db output TAP_bus__tdo; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) output busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:101" *) reg [7:0] core_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:101" *) reg [7:0] \core_asmcode$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) input core_bigendian_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *) reg \core_bigendian_i$10 = 1'h0; @@ -195664,53 +195652,53 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db wire [63:0] core_cia__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [2:0] core_cia__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:44" *) reg [63:0] core_core_core_cia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:44" *) reg [63:0] \core_core_core_cia$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [7:0] core_core_core_cr_rd = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [7:0] \core_core_core_cr_rd$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_core_cr_rd_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_core_cr_rd_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [7:0] core_core_core_cr_wr = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [7:0] \core_core_core_cr_wr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$3 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$4 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$6 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) reg \core_core_core_exc_$signal$next ; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -195727,21 +195715,21 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:49" *) reg [13:0] core_core_core_fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:49" *) reg [13:0] \core_core_core_fn_unit$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) reg [1:0] core_core_core_input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) reg [1:0] \core_core_core_input_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) reg [31:0] core_core_core_insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) reg [31:0] \core_core_core_insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -195818,145 +195806,145 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:48" *) reg [6:0] core_core_core_insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:48" *) reg [6:0] \core_core_core_insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) reg core_core_core_is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) reg \core_core_core_is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:43" *) reg [63:0] core_core_core_msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:43" *) reg [63:0] \core_core_core_msr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_core_oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_core_oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_core_oe_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_core_oe_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_core_rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_core_rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_core_rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_core_rc_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) reg [12:0] core_core_core_trapaddr = 13'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) reg [12:0] \core_core_core_trapaddr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:54" *) reg [7:0] core_core_core_traptype = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:54" *) reg [7:0] \core_core_core_traptype$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] core_core_cr_in1 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] \core_core_cr_in1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_cr_in1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_cr_in1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] core_core_cr_in2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] \core_core_cr_in2$1 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] \core_core_cr_in2$1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] \core_core_cr_in2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_cr_in2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_cr_in2_ok$2 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_cr_in2_ok$2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_cr_in2_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] core_core_cr_out = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] \core_core_cr_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_cr_wr_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_cr_wr_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) reg [6:0] core_core_dststep = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) reg [6:0] \core_core_dststep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] core_core_ea = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] \core_core_ea$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [2:0] core_core_fast1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [2:0] \core_core_fast1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_fast1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_fast1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [2:0] core_core_fast2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [2:0] \core_core_fast2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_fast2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_fast2_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [2:0] core_core_fasto1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [2:0] \core_core_fasto1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [2:0] core_core_fasto2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [2:0] \core_core_fasto2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) reg core_core_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) reg \core_core_lk$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) reg [6:0] core_core_maxvl = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) reg [6:0] \core_core_maxvl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) reg [63:0] core_core_pc = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) reg [63:0] \core_core_pc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] core_core_reg1 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] \core_core_reg1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_reg1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_reg1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] core_core_reg2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] \core_core_reg2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_reg2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_reg2_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] core_core_reg3 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] \core_core_reg3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_reg3_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_reg3_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] core_core_rego = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [6:0] \core_core_rego$next ; (* enum_base_type = "SPR" *) (* enum_value_0000010010 = "DSISR" *) @@ -195970,13 +195958,13 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db (* enum_value_1011000000 = "SVSTATE" *) (* enum_value_1011010000 = "PRTBL" *) (* enum_value_1011010001 = "SVSRR0" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [9:0] core_core_spr1 = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [9:0] \core_core_spr1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_core_spr1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_core_spr1_ok$next ; (* enum_base_type = "SPR" *) (* enum_value_0000010010 = "DSISR" *) @@ -195990,39 +195978,39 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db (* enum_value_1011000000 = "SVSTATE" *) (* enum_value_1011010000 = "PRTBL" *) (* enum_value_1011010001 = "SVSRR0" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [9:0] core_core_spro = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg [9:0] \core_core_spro$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) reg [6:0] core_core_srcstep = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) reg [6:0] \core_core_srcstep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) reg [1:0] core_core_subvl = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) reg [1:0] \core_core_subvl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) reg [1:0] core_core_svstep = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) reg [1:0] \core_core_svstep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) wire core_core_terminate_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) reg [6:0] core_core_vl = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) reg [6:0] \core_core_vl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:111" *) reg [2:0] core_core_xer_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:111" *) reg [2:0] \core_core_xer_in$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *) wire core_corebusy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) wire core_coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_cr_out_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_cr_out_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) wire core_cu_ad__go_i; @@ -196036,9 +196024,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg [63:0] core_data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [63:0] \core_data_i$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *) reg [63:0] core_dec = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *) reg [63:0] \core_dec$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [4:0] core_dmi__addr; @@ -196046,21 +196034,21 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db wire [63:0] core_dmi__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg core_dmi__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_ea_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_ea_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *) reg core_eint = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *) reg \core_eint$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_fasto1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_fasto1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_fasto2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_fasto2_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [31:0] core_full_rd2__data_o; @@ -196086,9 +196074,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg core_issue_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" *) reg core_ivalid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) reg [63:0] core_msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) reg [63:0] \core_msr$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] core_msr__data_o; @@ -196098,18 +196086,16 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg [31:0] core_raw_insn_i = 32'd0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *) reg [31:0] \core_raw_insn_i$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_rego_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_rego_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg core_spro_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) reg \core_spro_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [2:0] core_state_nia_wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) - reg core_stopped_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] core_sv__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) @@ -196124,11 +196110,11 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg [2:0] core_wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [2:0] \core_wen$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:112" *) reg core_xer_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:112" *) reg \core_xer_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg cu_st__rel_o_dly = 1'h0; @@ -196136,57 +196122,57 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db wire \cu_st__rel_o_dly$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire cu_st__rel_o_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) reg [6:0] cur_cur_dststep = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) reg [6:0] \cur_cur_dststep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) reg [6:0] cur_cur_maxvl = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) reg [6:0] \cur_cur_maxvl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) reg [6:0] cur_cur_srcstep = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) reg [6:0] \cur_cur_srcstep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) reg [1:0] cur_cur_subvl = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) reg [1:0] \cur_cur_subvl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) reg [1:0] cur_cur_svstep = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) reg [1:0] \cur_cur_svstep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) reg [6:0] cur_cur_vl = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) reg [6:0] \cur_cur_vl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1080" *) reg d_cr_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1080" *) reg \d_cr_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" *) reg d_reg_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" *) reg \d_reg_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1090" *) reg d_xer_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1090" *) reg \d_xer_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) wire [6:0] dbg_core_dbg_core_dbg_dststep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) wire [6:0] dbg_core_dbg_core_dbg_maxvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) wire [6:0] dbg_core_dbg_core_dbg_srcstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) wire [1:0] dbg_core_dbg_core_dbg_subvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) wire [1:0] dbg_core_dbg_core_dbg_svstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) wire [6:0] dbg_core_dbg_core_dbg_vl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) wire [63:0] dbg_core_dbg_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) wire [63:0] dbg_core_dbg_pc; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" *) wire dbg_core_rst_o; @@ -196254,87 +196240,87 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db output dbus__stb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) output dbus__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:101" *) wire [7:0] dec2_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:466" *) wire dec2_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:44" *) wire [63:0] dec2_cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] dec2_cr_in1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_cr_in1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] dec2_cr_in2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] \dec2_cr_in2$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_cr_in2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire \dec2_cr_in2_ok$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] dec2_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_cr_out_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [7:0] dec2_cr_rd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_cr_rd_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [7:0] dec2_cr_wr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_cr_wr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *) reg [63:0] dec2_cur_dec = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *) reg [63:0] \dec2_cur_dec$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *) reg dec2_cur_eint = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *) reg \dec2_cur_eint$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) reg [63:0] dec2_cur_msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) reg [63:0] \dec2_cur_msr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) reg [63:0] dec2_cur_pc = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) reg [63:0] \dec2_cur_pc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] dec2_ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_ea_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:13" *) wire \dec2_exc_$signal$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec2_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec2_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec2_fasto1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_fasto1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [2:0] dec2_fasto2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_fasto2_ok; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -196351,15 +196337,15 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db (* enum_value_00100000000000 = "MMU" *) (* enum_value_01000000000000 = "SV" *) (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:49" *) wire [13:0] dec2_fn_unit; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) wire [1:0] dec2_input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) wire [31:0] dec2_insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -196436,41 +196422,41 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:48" *) wire [6:0] dec2_insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) wire dec2_is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) wire dec2_lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:43" *) wire [63:0] dec2_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_oe_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) reg [31:0] dec2_raw_opcode_in = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:465" *) reg [31:0] \dec2_raw_opcode_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_rc_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] dec2_reg1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_reg1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] dec2_reg2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_reg2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] dec2_reg3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_reg3_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [6:0] dec2_rego; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_rego_ok; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -196586,9 +196572,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [9:0] dec2_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_spr1_ok; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -196704,23 +196690,23 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [9:0] dec2_spro; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire dec2_spro_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:713" *) wire dec2_sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) wire [12:0] dec2_trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:54" *) wire [7:0] dec2_traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:111" *) wire [2:0] dec2_xer_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:112" *) wire dec2_xer_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:904" *) reg [1:0] delay = 2'h3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:904" *) reg [1:0] \delay$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output eint_0__core__i; @@ -196734,33 +196720,33 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db output eint_2__core__i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input eint_2__pad__i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) reg exec_fsm_state = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) reg \exec_fsm_state$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1000" *) reg exec_insn_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:955" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:999" *) reg exec_insn_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:960" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1004" *) reg exec_pc_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:959" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1003" *) reg exec_pc_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) reg [1:0] fetch_fsm_state = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) reg [1:0] \fetch_fsm_state$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:944" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:988" *) reg fetch_insn_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:987" *) reg fetch_insn_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:940" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:984" *) reg fetch_pc_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:939" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:983" *) reg fetch_pc_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) reg [1:0] fsm_state = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) reg [1:0] \fsm_state$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output gpio_e10__core__i; @@ -197010,17 +196996,17 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg imem_f_valid_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) wire imem_wb_icache_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:268" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:269" *) reg insn_done; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *) input [15:0] int_level_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:698" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *) reg is_last; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:933" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *) wire is_svp64_mode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) reg [2:0] issue_fsm_state = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) reg [2:0] \issue_fsm_state$next ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) reg jtag_dmi0__ack_o = 1'h0; @@ -197038,21 +197024,21 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db wire jtag_dmi0__req_i; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) wire jtag_dmi0__we_i; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) input jtag_wb__ack; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output [29:0] jtag_wb__adr; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__cyc; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) input [31:0] jtag_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output [31:0] jtag_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output [3:0] jtag_wb__sel; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__stb; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__we; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input mspi0_clk__core__o; @@ -197070,9 +197056,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db input mspi0_mosi__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output mspi0_mosi__pad__o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" *) reg msr_read = 1'h1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" *) reg \msr_read$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input mtwi_scl__core__o; @@ -197090,57 +197076,57 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db output mtwi_sda__pad__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output mtwi_sda__pad__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" *) reg [63:0] new_dec; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) reg [6:0] new_svstate_dststep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) reg [6:0] new_svstate_maxvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) reg [6:0] new_svstate_srcstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) reg [1:0] new_svstate_subvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) reg [1:0] new_svstate_svstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) reg [6:0] new_svstate_vl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1096" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1140" *) reg [63:0] new_tb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" *) wire [6:0] next_dststep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:546" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" *) wire [6:0] next_srcstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:922" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" *) reg [63:0] nia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:922" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" *) reg [63:0] \nia$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) reg [63:0] pc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:901" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:945" *) reg pc_changed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:901" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:945" *) reg \pc_changed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input [63:0] pc_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) input pc_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" *) output [63:0] pc_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg pc_ok_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg \pc_ok_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:898" *) wire por_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:992" *) wire pred_insn_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" *) reg pred_insn_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:996" *) reg pred_mask_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:951" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:995" *) wire pred_mask_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -197426,23 +197412,23 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db input sdr_we_n__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output sdr_we_n__pad__o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:902" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" *) reg sv_changed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:902" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" *) reg \sv_changed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) reg [63:0] svstate; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [31:0] svstate_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire svstate_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg svstate_ok_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg \svstate_ok_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:903" *) wire ti_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) reg update_svstate; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) wire xics_icp_core_irq_o; @@ -197454,133 +197440,127 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db wire [7:0] xics_ics_icp_o_pri; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *) wire [3:0] xics_ics_icp_o_src; - assign \$100 = \$98 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; - assign \$102 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read; - assign \$105 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) 3'h4; + assign \$100 = \$98 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) is_last; + assign \$102 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read; + assign \$105 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) 3'h4; assign \$108 = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20; assign \$107 = imem_f_instr_o >> \$108 ; - assign \$113 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) 3'h4; + assign \$113 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) 3'h4; assign \$115 = \$112 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20; assign \$111 = imem_f_instr_o >> \$115 ; - assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$120 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$122 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$120 ; - assign \$124 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$126 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$126 ; - assign \$130 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; - assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; - assign \$134 = \$132 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; - assign \$137 = cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) 1'h1; - assign \$140 = cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) 1'h1; - assign \$142 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$144 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$146 = \$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$144 ; - assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$150 ; - assign \$154 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; - assign \$156 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$154 ; - assign \$158 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *) is_svp64_mode; - assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$162 ; - assign \$166 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; - assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; - assign \$170 = \$168 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; - assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$174 ; - assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$180 ; - assign \$184 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$186 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$188 = \$184 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$186 ; - assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$192 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$194 = \$190 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$192 ; - assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$198 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$200 = \$196 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$198 ; - assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$204 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$206 = \$202 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$204 ; - assign \$209 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) 1'h1; - assign \$208 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$209 ; - assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$214 ; - assign \$218 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$220 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$222 = \$218 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$220 ; - assign \$224 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; - assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; - assign \$228 = \$226 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; - assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$232 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$234 = \$230 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$232 ; - assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$238 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read; - assign \$240 = \$236 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$238 ; - assign \$243 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) 3'h4; - assign \$242 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$243 ; - assign \$246 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; - assign \$248 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$246 ; - assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o; - assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$256 = \$252 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$254 ; - assign \$258 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$25 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *) 1'h0; - assign \$260 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$262 = \$258 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$260 ; - assign \$264 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:700" *) cur_cur_vl; - assign \$266 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; - assign \$268 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *) 7'h01; - assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o; - assign \$272 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o; - assign \$274 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o; - assign \$276 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o; - assign \$279 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *) 1'h1; - assign \$282 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *) 1'h1; - assign \$28 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *) 1'h1; - assign \$30 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) dbg_core_rst_o; - assign \$32 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) rst; - assign \$34 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) \$32 ; + assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) dbg_core_stop_o; + assign \$120 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_coresync_rst; + assign \$122 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) \$120 ; + assign \$124 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) dbg_core_stop_o; + assign \$126 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) core_coresync_rst; + assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) \$126 ; + assign \$130 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) sv_changed; + assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) 1'h0; + assign \$134 = \$132 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) is_last; + assign \$137 = cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) 1'h1; + assign \$140 = cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) 1'h1; + assign \$142 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) dbg_core_stop_o; + assign \$144 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_coresync_rst; + assign \$146 = \$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) \$144 ; + assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) dbg_core_stop_o; + assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_coresync_rst; + assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) \$150 ; + assign \$154 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) 1'h0; + assign \$156 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) \$154 ; + assign \$158 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" *) is_svp64_mode; + assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) dbg_core_stop_o; + assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) core_coresync_rst; + assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) \$162 ; + assign \$166 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) sv_changed; + assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) 1'h0; + assign \$170 = \$168 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) is_last; + assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) dbg_core_stop_o; + assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_coresync_rst; + assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) \$174 ; + assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) dbg_core_stop_o; + assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) core_coresync_rst; + assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) \$180 ; + assign \$184 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) dbg_core_stop_o; + assign \$186 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_coresync_rst; + assign \$188 = \$184 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) \$186 ; + assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) dbg_core_stop_o; + assign \$192 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) core_coresync_rst; + assign \$194 = \$190 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) \$192 ; + assign \$197 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:842" *) 1'h1; + assign \$196 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$197 ; + assign \$200 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) dbg_core_stop_o; + assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_coresync_rst; + assign \$204 = \$200 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) \$202 ; + assign \$206 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) dbg_core_stop_o; + assign \$208 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) core_coresync_rst; + assign \$210 = \$206 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) \$208 ; + assign \$212 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) sv_changed; + assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) 1'h0; + assign \$216 = \$214 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) is_last; + assign \$218 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) dbg_core_stop_o; + assign \$220 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_coresync_rst; + assign \$222 = \$218 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) \$220 ; + assign \$224 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) dbg_core_stop_o; + assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) core_coresync_rst; + assign \$228 = \$224 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) \$226 ; + assign \$231 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:840" *) 3'h4; + assign \$230 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$231 ; + assign \$234 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) 1'h0; + assign \$236 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) \$234 ; + assign \$238 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) core_corebusy_o; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read; + assign \$240 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) dbg_core_stop_o; + assign \$242 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) core_coresync_rst; + assign \$244 = \$240 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) \$242 ; + assign \$246 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) dbg_core_stop_o; + assign \$248 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) core_coresync_rst; + assign \$250 = \$246 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) \$248 ; + assign \$252 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" *) cur_cur_vl; + assign \$254 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; + assign \$256 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:837" *) 7'h01; + assign \$258 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) core_corebusy_o; + assign \$25 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:905" *) 1'h0; + assign \$260 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) core_corebusy_o; + assign \$262 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o; + assign \$264 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o; + assign \$267 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" *) 1'h1; + assign \$270 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1141" *) 1'h1; + assign \$28 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:906" *) 1'h1; + assign \$30 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" *) dbg_core_rst_o; + assign \$32 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" *) rst; + assign \$34 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" *) \$32 ; assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly; assign \$38 = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$36 ; - assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) pc_i_ok; - assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$48 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$50 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) svstate_i_ok; - assign \$52 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$54 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) svstate_i; - assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$58 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$60 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$62 = \$58 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$60 ; - assign \$64 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; - assign \$66 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$64 ; - assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$70 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$72 = \$68 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$70 ; - assign \$74 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; - assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; - assign \$78 = \$76 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; - assign \$80 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$82 ; - assign \$86 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; - assign \$88 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$86 ; - assign \$90 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; - assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; - assign \$94 = \$90 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$92 ; - assign \$96 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; - assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; + assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) pc_i_ok; + assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$48 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$50 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) svstate_i_ok; + assign \$52 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$54 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) svstate_i; + assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$58 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) dbg_core_stop_o; + assign \$60 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_coresync_rst; + assign \$62 = \$58 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) \$60 ; + assign \$64 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) 1'h0; + assign \$66 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) \$64 ; + assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) dbg_core_stop_o; + assign \$70 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) core_coresync_rst; + assign \$72 = \$68 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) \$70 ; + assign \$74 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) sv_changed; + assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) 1'h0; + assign \$78 = \$76 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) is_last; + assign \$80 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) dbg_core_stop_o; + assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_coresync_rst; + assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) \$82 ; + assign \$86 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) 1'h0; + assign \$88 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) \$86 ; + assign \$90 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) dbg_core_stop_o; + assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) core_coresync_rst; + assign \$94 = \$90 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) \$92 ; + assign \$96 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) sv_changed; + assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) 1'h0; always @(posedge clk) fsm_state <= \fsm_state$next ; always @(posedge clk) @@ -198321,7 +198301,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \dbg_dmi_addr_i$next = jtag_dmi0__addr_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dbg_dmi_addr_i$next = 4'h0; @@ -198330,7 +198310,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \dbg_dmi_req_i$next = jtag_dmi0__req_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dbg_dmi_req_i$next = 1'h0; @@ -198348,34 +198328,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db \core_core_srcstep$next = core_core_srcstep; \core_core_vl$next = core_core_vl; \core_core_maxvl$next = core_core_maxvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: { \core_core_maxvl$next , \core_core_vl$next , \core_core_srcstep$next , \core_core_dststep$next , \core_core_subvl$next , \core_core_svstep$next , \core_dec$next , \core_eint$next , \core_msr$next , \core_core_pc$next } = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep, dec2_cur_dec, dec2_cur_eint, dec2_cur_msr, dec2_cur_pc }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -198395,34 +198375,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_raw_insn_i$next = core_raw_insn_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: \core_raw_insn_i$next = dec2_raw_opcode_in; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \core_raw_insn_i$next = 32'd0; @@ -198431,34 +198411,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_bigendian_i$10$next = \core_bigendian_i$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: \core_bigendian_i$10$next = core_bigendian_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \core_bigendian_i$10$next = 1'h0; @@ -198467,34 +198447,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_sv_a_nz$next = core_sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: \core_sv_a_nz$next = dec2_sv_a_nz; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \core_sv_a_nz$next = 1'h0; @@ -198503,34 +198483,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end exec_insn_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: exec_insn_valid_i = 1'h1; endcase @@ -198539,42 +198519,42 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end exec_pc_ready_i = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) - casez (\$256 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) + casez (\$244 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ 1'h1: exec_pc_ready_i = 1'h1; endcase @@ -198584,48 +198564,48 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end is_last = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) - casez (\$262 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) + casez (\$250 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" */ 1'h1: - is_last = \$264 ; + is_last = \$252 ; endcase endcase endcase @@ -198633,9 +198613,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_wen$11 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" */ 1'h1: \core_wen$11 = 3'h4; endcase @@ -198643,20 +198623,20 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_data_i$12 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" */ 1'h1: - \core_data_i$12 = \$266 ; + \core_data_i$12 = \$254 ; endcase end always @* begin if (\initial ) begin end exec_insn_ready_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:826" */ 1'h0: exec_insn_ready_o = 1'h1; endcase @@ -198665,23 +198645,23 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end core_ivalid_i = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:826" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ 1'h1: core_ivalid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *) - casez (\$268 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:837" *) + casez (\$256 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:837" */ 1'h1: core_ivalid_i = 1'h1; endcase @@ -198690,14 +198670,14 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_issue_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:826" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ 1'h1: core_issue_i = 1'h1; endcase @@ -198707,33 +198687,33 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end \exec_fsm_state$next = exec_fsm_state; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:826" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ 1'h1: \exec_fsm_state$next = 1'h1; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) - casez (\$270 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + casez (\$258 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" *) casez (exec_pc_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" */ 1'h1: \exec_fsm_state$next = 1'h0; endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \exec_fsm_state$next = 1'h0; @@ -198743,18 +198723,18 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end exec_pc_valid_o = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:826" */ 1'h0: /* empty */; /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) - casez (\$272 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + casez (\$260 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" */ 1'h1: exec_pc_valid_o = 1'h1; endcase @@ -198763,9 +198743,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_dmi__addr = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1062" *) casez (dbg_d_gpr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1062" */ 1'h1: core_dmi__addr = dbg_d_gpr_addr[4:0]; endcase @@ -198773,9 +198753,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_dmi__ren = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1062" *) casez (dbg_d_gpr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1062" */ 1'h1: core_dmi__ren = 1'h1; endcase @@ -198783,7 +198763,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \d_reg_delay$next = dbg_d_gpr_req; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \d_reg_delay$next = 1'h0; @@ -198792,9 +198772,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_d_gpr_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" *) casez (d_reg_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 1'h1: dbg_d_gpr_data = core_dmi__data_o; endcase @@ -198802,9 +198782,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_d_gpr_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" *) casez (d_reg_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 1'h1: dbg_d_gpr_ack = 1'h1; endcase @@ -198812,9 +198792,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_full_rd2__ren = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" *) casez (dbg_d_cr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ 1'h1: core_full_rd2__ren = 8'hff; endcase @@ -198822,7 +198802,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \d_cr_delay$next = dbg_d_cr_req; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \d_cr_delay$next = 1'h0; @@ -198831,19 +198811,19 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_d_cr_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1082" *) casez (d_cr_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1082" */ 1'h1: - dbg_d_cr_data = \$274 ; + dbg_d_cr_data = \$262 ; endcase end always @* begin if (\initial ) begin end dbg_d_cr_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1082" *) casez (d_cr_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1082" */ 1'h1: dbg_d_cr_ack = 1'h1; endcase @@ -198851,9 +198831,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_full_rd__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1088" *) casez (dbg_d_xer_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1088" */ 1'h1: core_full_rd__ren = 3'h7; endcase @@ -198861,7 +198841,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \d_xer_delay$next = dbg_d_xer_req; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \d_xer_delay$next = 1'h0; @@ -198870,19 +198850,19 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_d_xer_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1092" *) casez (d_xer_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1092" */ 1'h1: - dbg_d_xer_data = \$276 ; + dbg_d_xer_data = \$264 ; endcase end always @* begin if (\initial ) begin end dbg_d_xer_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1092" *) casez (d_xer_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1092" */ 1'h1: dbg_d_xer_ack = 1'h1; endcase @@ -198890,18 +198870,18 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_issue__addr = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1116" */ 2'h0: core_issue__addr = 3'h6; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" */ 2'h2: core_issue__addr = 3'h7; endcase @@ -198909,18 +198889,18 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_issue__ren = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1116" */ 2'h0: core_issue__ren = 1'h1; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" */ 2'h2: core_issue__ren = 1'h1; endcase @@ -198928,26 +198908,26 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1116" */ 2'h0: \fsm_state$next = 2'h1; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" */ 2'h1: \fsm_state$next = 2'h2; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" */ 2'h2: \fsm_state$next = 2'h3; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1139" */ 2'h3: \fsm_state$next = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \fsm_state$next = 2'h0; @@ -198956,38 +198936,38 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end new_dec = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1116" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" */ 2'h1: - new_dec = \$278 [63:0]; + new_dec = \$266 [63:0]; endcase end always @* begin if (\initial ) begin end \core_issue__addr$13 = 3'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1116" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" */ 2'h1: \core_issue__addr$13 = 3'h6; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1139" */ 2'h3: \core_issue__addr$13 = 3'h7; endcase @@ -198996,22 +198976,22 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end core_issue__wen = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1116" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" */ 2'h1: core_issue__wen = 1'h1; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1139" */ 2'h3: core_issue__wen = 1'h1; endcase @@ -199020,22 +199000,22 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end core_issue__data_i = 64'h0000000000000000; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1116" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" */ 2'h1: core_issue__data_i = new_dec; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1139" */ 2'h3: core_issue__data_i = new_tb; endcase @@ -199044,24 +199024,24 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end new_tb = 64'h0000000000000000; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1116" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1139" */ 2'h3: - new_tb = \$281 [63:0]; + new_tb = \$269 [63:0]; endcase end always @* begin @@ -199076,20 +199056,20 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db \cur_cur_vl$next = cur_cur_vl; \cur_cur_maxvl$next = cur_cur_maxvl; \dec2_cur_eint$next = xics_icp_core_irq_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:896" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:940" *) casez (core_coresync_rst) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:896" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:940" */ 1'h1: { \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next , \dec2_cur_dec$next , \dec2_cur_eint$next , \dec2_cur_msr$next , \dec2_cur_pc$next } = 225'h000000000000000000000000000000000000000000000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: begin \dec2_cur_pc$next = pc; @@ -199097,33 +199077,33 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db end endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) casez (\$23 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" */ 1'h1: \dec2_cur_msr$next = core_msr__data_o; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" */ 1'h1: { \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next } = { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1116" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" */ 2'h1: \dec2_cur_dec$next = new_dec; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -199143,7 +199123,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \dbg_dmi_we_i$next = jtag_dmi0__we_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dbg_dmi_we_i$next = 1'h0; @@ -199152,13 +199132,13 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \pc_ok_delay$next = pc_ok_delay; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$40 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: \pc_ok_delay$next = \$42 ; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \pc_ok_delay$next = 1'h0; @@ -199167,7 +199147,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \dbg_dmi_din$next = jtag_dmi0__din; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dbg_dmi_din$next = 64'h0000000000000000; @@ -199176,20 +199156,20 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end pc = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$44 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: begin - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" */ 1'h1: pc = pc_i; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:75" *) casez (pc_ok_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:75" */ 1'h1: pc = core_cia__data_o; endcase @@ -199199,17 +199179,17 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_cia__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$46 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" */ default: core_cia__ren = 3'h1; endcase @@ -199218,13 +199198,13 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \svstate_ok_delay$next = svstate_ok_delay; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$48 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: \svstate_ok_delay$next = \$50 ; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \svstate_ok_delay$next = 1'h0; @@ -199233,20 +199213,20 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end svstate = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$52 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: begin - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" */ 1'h1: svstate = \$54 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:75" *) casez (svstate_ok_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:75" */ 1'h1: svstate = core_sv__data_o; endcase @@ -199256,17 +199236,17 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_sv__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$56 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" */ default: core_sv__ren = 3'h4; endcase @@ -199276,87 +199256,87 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end core_wen = 3'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) casez (\$62 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:613" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:613" */ 1'h1: core_wen = 3'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) casez (\$66 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" */ 1'h1: core_wen = 3'h1; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) casez (\$72 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) casez ({ \$78 , \$74 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 2'b1?: core_wen = 3'h1; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ 1'h1: core_wen = 3'h1; endcase @@ -199367,87 +199347,87 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end core_data_i = 64'h0000000000000000; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) casez (\$84 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:613" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:613" */ 1'h1: core_data_i = pc_i; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) casez (\$88 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" */ 1'h1: core_data_i = nia; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) casez (\$94 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) casez ({ \$100 , \$96 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 2'b1?: core_data_i = nia; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ 1'h1: core_data_i = pc_i; endcase @@ -199457,14 +199437,14 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_msr__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: core_msr__ren = 3'h2; endcase @@ -199473,7 +199453,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \jtag_dmi0__ack_o$next = dbg_dmi_ack_o; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_dmi0__ack_o$next = 1'h0; @@ -199482,10 +199462,10 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end fetch_pc_ready_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: fetch_pc_ready_o = 1'h1; endcase @@ -199493,14 +199473,14 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end imem_a_pc_i = 48'h000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: imem_a_pc_i = pc[47:0]; endcase @@ -199509,32 +199489,32 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end imem_a_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: imem_a_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ 1'h1: imem_a_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ 2'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 1'h1: imem_a_valid_i = 1'h1; endcase @@ -199543,7 +199523,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \jtag_dmi0__dout$next = dbg_dmi_dout; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_dmi0__dout$next = 64'h0000000000000000; @@ -199552,32 +199532,32 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end imem_f_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: imem_f_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ 1'h1: imem_f_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ 2'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 1'h1: imem_f_valid_i = 1'h1; endcase @@ -199586,28 +199566,28 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \msr_read$next = msr_read; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: \msr_read$next = 1'h0; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) casez (\$102 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" */ 1'h1: \msr_read$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \msr_read$next = 1'h1; @@ -199617,54 +199597,54 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end \fetch_fsm_state$next = fetch_fsm_state; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: \fetch_fsm_state$next = 2'h1; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */ default: \fetch_fsm_state$next = 2'h2; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ 2'h3: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:362" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */ default: \fetch_fsm_state$next = 2'h2; endcase /* \nmigen.decoding = "INSN_READY/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" */ 2'h2: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387" *) casez (fetch_insn_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387" */ 1'h1: \fetch_fsm_state$next = 2'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \fetch_fsm_state$next = 2'h0; @@ -199673,33 +199653,33 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \nia$next = nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: /* empty */; /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */ default: \nia$next = \$104 [63:0]; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:994" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" *) casez (core_coresync_rst) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:994" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" */ 1'h1: \nia$next = 64'h0000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \nia$next = 64'h0000000000000000; @@ -199708,35 +199688,35 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \dec2_raw_opcode_in$next = dec2_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: /* empty */; /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */ default: \dec2_raw_opcode_in$next = \$107 ; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ 2'h3: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:362" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */ default: \dec2_raw_opcode_in$next = \$111 ; endcase @@ -199746,22 +199726,22 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end fetch_insn_valid_o = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: /* empty */; /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: /* empty */; /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ 2'h3: /* empty */; /* \nmigen.decoding = "INSN_READY/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" */ 2'h2: fetch_insn_valid_o = 1'h1; endcase @@ -199770,75 +199750,75 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) casez (\$122 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" */ 1'h1: { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) casez (\$128 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) casez ({ \$134 , \$130 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 2'b1?: begin new_svstate_srcstep = 7'h00; new_svstate_dststep = 7'h00; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" */ default: begin new_svstate_srcstep = next_srcstep; @@ -199846,11 +199826,11 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db end endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" */ 1'h1: { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i; endcase @@ -199860,14 +199840,14 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end fetch_pc_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) casez (\$146 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */ 1'h1: fetch_pc_valid_i = 1'h1; endcase @@ -199877,224 +199857,166 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end \issue_fsm_state$next = issue_fsm_state; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) casez (\$152 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (fetch_pc_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" */ 1'h1: \issue_fsm_state$next = 3'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) casez (\$156 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" */ 1'h1: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:638" */ default: \issue_fsm_state$next = 3'h2; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:601" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:646" *) casez (pred_insn_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:601" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:646" */ 1'h1: \issue_fsm_state$next = 3'h4; endcase /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:651" *) casez (pred_mask_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:651" */ 1'h1: \issue_fsm_state$next = 3'h5; endcase /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" *) casez (\$158 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" */ 1'h1: \issue_fsm_state$next = 3'h2; endcase /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: \issue_fsm_state$next = 3'h6; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" *) casez (exec_insn_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */ 1'h1: \issue_fsm_state$next = 3'h7; endcase /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) casez (\$164 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) casez ({ \$170 , \$166 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" */ 2'b?1: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 2'b1?: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" */ default: \issue_fsm_state$next = 3'h5; endcase endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \issue_fsm_state$next = 3'h0; endcase end - always @* begin - if (\initial ) begin end - core_stopped_i = 1'h0; - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) - casez (issue_fsm_state) - /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ - 3'h0: - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$176 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ - 1'h1: - /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ - default: - core_stopped_i = 1'h1; - endcase - /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ - 3'h1: - /* empty */; - /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ - 3'h3: - /* empty */; - /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ - 3'h4: - /* empty */; - /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ - 3'h5: - /* empty */; - /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ - 3'h2: - /* empty */; - /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ - 3'h6: - /* empty */; - /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ - 3'h7: - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) - casez (\$182 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ - 1'h1: - /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ - default: - core_stopped_i = 1'h1; - endcase - endcase - end always @* begin if (\initial ) begin end dbg_core_stopped_i = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$188 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) + casez (\$176 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ default: dbg_core_stopped_i = 1'h1; endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) - casez (\$194 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) + casez (\$182 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ default: dbg_core_stopped_i = 1'h1; endcase @@ -200104,92 +200026,92 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end \pc_changed$next = pc_changed; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$200 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) + casez (\$188 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:613" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:613" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) - casez (\$206 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) + casez (\$194 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase endcase (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:826" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ 1'h1: \pc_changed$next = 1'h0; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) - casez (\$208 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:842" *) + casez (\$196 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:842" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \pc_changed$next = 1'h0; @@ -200199,81 +200121,81 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end update_svstate = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$216 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) + casez (\$204 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" */ 1'h1: update_svstate = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) - casez (\$222 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) + casez (\$210 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:740" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) - casez ({ \$228 , \$224 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) + casez ({ \$216 , \$212 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 2'b1?: update_svstate = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" */ default: update_svstate = 1'h1; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" */ 1'h1: update_svstate = 1'h1; endcase @@ -200284,92 +200206,92 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db if (\initial ) begin end \sv_changed$next = sv_changed; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$234 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) + casez (\$222 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) - casez (\$240 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" *) + casez (\$228 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase endcase (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:826" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ 1'h1: \sv_changed$next = 1'h0; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) - casez (\$242 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:840" *) + casez (\$230 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:840" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sv_changed$next = 1'h0; @@ -200378,14 +200300,14 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end fetch_insn_ready_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: fetch_insn_ready_i = 1'h1; endcase @@ -200393,44 +200315,44 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end insn_done = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) - casez (\$248 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" *) + casez (\$236 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" */ 1'h1: insn_done = 1'h1; endcase endcase endcase (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:826" */ 1'h0: /* empty */; /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) - casez (\$250 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + casez (\$238 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" *) casez (exec_pc_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" */ 1'h1: insn_done = 1'h1; endcase @@ -200440,18 +200362,18 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end pred_insn_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: pred_insn_valid_i = 1'h1; endcase @@ -200459,22 +200381,22 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end pred_mask_ready_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: pred_mask_ready_i = 1'h1; endcase @@ -200540,34 +200462,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db \core_core_core_cr_wr$next = core_core_core_cr_wr; \core_core_cr_wr_ok$next = core_core_cr_wr_ok; \core_core_core_is_32bit$next = core_core_core_is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:719" */ 3'h2: { \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_$signal$9$next , \core_core_core_exc_$signal$8$next , \core_core_core_exc_$signal$7$next , \core_core_core_exc_$signal$6$next , \core_core_core_exc_$signal$5$next , \core_core_core_exc_$signal$4$next , \core_core_core_exc_$signal$3$next , \core_core_core_exc_$signal$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, \dec2_exc_$signal$22 , \dec2_exc_$signal$21 , \dec2_exc_$signal$20 , \dec2_exc_$signal$19 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal , dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_cia, dec2_msr, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$15 , \dec2_cr_in2$14 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -200604,9 +200526,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \delay$next = delay; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:905" *) casez (\$25 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:905" */ 1'h1: \delay$next = \$27 [1:0]; endcase @@ -200616,8 +200538,8 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db assign \$112 = \$113 ; assign \$136 = \$137 ; assign \$139 = \$140 ; - assign \$278 = \$279 ; - assign \$281 = \$282 ; + assign \$266 = \$267 ; + assign \$269 = \$270 ; assign dec2_sv_a_nz = 1'h0; assign svstate_i_ok = 1'h0; assign svstate_i = 32'd0; @@ -200799,23 +200721,23 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni wire alu_pulse; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) wire [4:0] alu_pulsem; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_trap0_fast1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] \alu_trap0_fast1$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_trap0_fast2; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] \alu_trap0_fast2$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_trap0_msr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_trap0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_trap0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_trap0_nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) wire [63:0] alu_trap0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_trap0_p_ready_o; @@ -200959,9 +200881,9 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -201040,15 +200962,15 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [63:0] dest5_o; reg [63:0] dest5_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output msr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:19" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -201475,7 +201397,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -201484,7 +201406,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -201493,7 +201415,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -201502,7 +201424,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -201511,7 +201433,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -201520,7 +201442,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -201529,7 +201451,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 4'h0; @@ -201538,7 +201460,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 4'hf; @@ -201547,7 +201469,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 5'h00; @@ -201556,7 +201478,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 5'h1f; @@ -201596,7 +201518,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -201618,7 +201540,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r1__fast1_ok$next , \data_r1__fast1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__fast1_ok$next = 1'h0; @@ -201640,7 +201562,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r2__fast2_ok$next , \data_r2__fast2$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__fast2_ok$next = 1'h0; @@ -201662,7 +201584,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r3__nia_ok$next , \data_r3__nia$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r3__nia_ok$next = 1'h0; @@ -201684,7 +201606,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r4__msr_ok$next , \data_r4__msr$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r4__msr_ok$next = 1'h0; @@ -201733,7 +201655,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -201742,7 +201664,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$91 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -201801,7 +201723,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 5'h00; @@ -201858,9 +201780,9 @@ module upd_l(coresync_rst, s_upd, r_upd, q_upd, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -201889,7 +201811,7 @@ module upd_l(coresync_rst, s_upd, r_upd, q_upd, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -201920,9 +201842,9 @@ module valid_l(coresync_rst, s_valid, q_valid, r_valid, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -201951,7 +201873,7 @@ module valid_l(coresync_rst, s_valid, q_valid, r_valid, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -201982,9 +201904,9 @@ module wri_l(coresync_rst, s_wri, r_wri, q_wri, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -202013,7 +201935,7 @@ module wri_l(coresync_rst, s_wri, r_wri, q_wri, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -202539,9 +202461,9 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, wire [1:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [1:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] data_i; @@ -202653,17 +202575,17 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, wire [1:0] reg_2_w2__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire reg_2_w2__wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] ren_delay = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$11 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$18 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$18$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [1:0] src1__data_o; @@ -202764,7 +202686,7 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end \ren_delay$18$next = src3__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$18$next = 3'h0; @@ -202773,9 +202695,9 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end src3__data_o = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$19 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src3__data_o = \$23 ; endcase @@ -202783,7 +202705,7 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end \ren_delay$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 3'h0; @@ -202792,9 +202714,9 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end src1__data_o = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$5 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src1__data_o = \$9 ; endcase @@ -202802,7 +202724,7 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end \ren_delay$11$next = src2__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$11$next = 3'h0; @@ -202811,9 +202733,9 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end src2__data_o = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$12 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src2__data_o = \$16 ; endcase @@ -202869,7 +202791,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, wire [31:0] be_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" *) reg [31:0] be_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) output core_irq_o; @@ -202925,7 +202847,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, reg [7:0] min_pri; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" *) reg [7:0] pending_priority; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *) reg wb_ack = 1'h0; @@ -202980,7 +202902,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, always @* begin if (\initial ) begin end { \wb_ack$next , \wb_rd_data$next , \irq$next , \mfrr$next , \cppr$next , \xisr$next } = { \wb_ack$6 , \wb_rd_data$5 , \irq$4 , \mfrr$3 , \cppr$2 , \xisr$1 }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -203081,7 +203003,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, always @* begin if (\initial ) begin end \core_irq_o$next = irq; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \core_irq_o$next = 1'h0; @@ -203379,7 +203301,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc wire [31:0] be_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" *) reg [31:0] be_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) reg [3:0] cur_idx0; @@ -203499,7 +203421,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc wire reg_is_debug; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" *) wire reg_is_xive; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" *) wire wb_valid; @@ -203776,7 +203698,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -203892,7 +203814,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc always @* begin if (\initial ) begin end \int_level_l$next = int_level_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \int_level_l$next = 16'h0000; @@ -204192,7 +204114,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc always @* begin if (\initial ) begin end \ics_wb__dat_r$next = { be_out[7:0], be_out[15:8], be_out[23:16], be_out[31:24] }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ics_wb__dat_r$next = 32'd0; @@ -204201,7 +204123,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc always @* begin if (\initial ) begin end \ics_wb__ack$next = wb_valid; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ics_wb__ack$next = 1'h0; -- 2.30.2