From 535b007f28af7cb46fe371c25af636459599bdf3 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 21 May 2020 08:57:30 +0000 Subject: [PATCH] vendor.xilinx_{7series,ultrascale}: don't use `write_verilog -decimal`. In commit 892cff05, `-decimal` was used when writing Verilog for Vivado targets because it treats (* keep=32'd1 *) and (* keep=1 *) differently in violation of Verilog LRM. However, it is possible to avoid that workaround by using (* keep="TRUE" *). Do that, and remove `-decimal` to avoid special-casing 32-bit constants. Refs #373. --- nmigen/vendor/xilinx_7series.py | 8 +++----- nmigen/vendor/xilinx_ultrascale.py | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index dec32a2..c9b44f1 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -66,15 +66,13 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): [ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}" {{emit_commands("sh")}} """, - # Vivado doesn't like constructs like (* keep = 32'd1 *), even though they mean the same - # thing as (* keep = 1 *); use -decimal to work around that. "{{name}}.v": r""" /* {{autogenerated}} */ - {{emit_verilog(["-decimal"])}} + {{emit_verilog()}} """, "{{name}}.debug.v": r""" /* {{autogenerated}} */ - {{emit_debug_verilog(["-decimal"])}} + {{emit_debug_verilog()}} """, "{{name}}.tcl": r""" # {{autogenerated}} @@ -181,7 +179,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): def add_clock_constraint(self, clock, frequency): super().add_clock_constraint(clock, frequency) - clock.attrs["keep"] = 1 + clock.attrs["keep"] = "TRUE" def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False): def get_dff(clk, d, q): diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py index 7445f4b..c144229 100644 --- a/nmigen/vendor/xilinx_ultrascale.py +++ b/nmigen/vendor/xilinx_ultrascale.py @@ -66,15 +66,13 @@ class XilinxUltraScalePlatform(TemplatedPlatform): [ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}" {{emit_commands("sh")}} """, - # Vivado doesn't like constructs like (* keep = 32'd1 *), even though they mean the same - # thing as (* keep = 1 *); use -decimal to work around that. "{{name}}.v": r""" /* {{autogenerated}} */ - {{emit_verilog(["-decimal"])}} + {{emit_verilog()}} """, "{{name}}.debug.v": r""" /* {{autogenerated}} */ - {{emit_debug_verilog(["-decimal"])}} + {{emit_debug_verilog()}} """, "{{name}}.tcl": r""" # {{autogenerated}} @@ -181,7 +179,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform): def add_clock_constraint(self, clock, frequency): super().add_clock_constraint(clock, frequency) - clock.attrs["keep"] = 1 + clock.attrs["keep"] = "TRUE" def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False): def get_dff(clk, d, q): -- 2.30.2