From 536782b0b7552c85e57687f205f22f04c67e1145 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 24 Oct 2017 11:42:31 +0000 Subject: [PATCH] amd/common: add GFX10 chips Acked-by: Bas Nieuwenhuizen --- src/amd/addrlib/src/amdgpu_asic_addr.h | 6 +++++- src/amd/common/ac_gpu_info.c | 10 ++++++++-- src/amd/common/ac_llvm_util.c | 9 ++++++++- src/amd/common/amd_family.h | 4 ++++ src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 4 +++- 5 files changed, 28 insertions(+), 5 deletions(-) diff --git a/src/amd/addrlib/src/amdgpu_asic_addr.h b/src/amd/addrlib/src/amdgpu_asic_addr.h index 3264e8ec98e..f02d367e6b4 100644 --- a/src/amd/addrlib/src/amdgpu_asic_addr.h +++ b/src/amd/addrlib/src/amdgpu_asic_addr.h @@ -94,7 +94,9 @@ #define AMDGPU_RAVEN_RANGE 0x01, 0x81 #define AMDGPU_RAVEN2_RANGE 0x81, 0xFF -#define AMDGPU_NAVI10_RANGE 0x01, 0xFF +#define AMDGPU_NAVI10_RANGE 0x01, 0x0A +#define AMDGPU_NAVI12_RANGE 0x0A, 0x14 +#define AMDGPU_NAVI14_RANGE 0x14, 0x28 #define AMDGPU_EXPAND_FIX(x) x #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max)) @@ -139,5 +141,7 @@ #define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2) #define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10) +#define ASICREV_IS_NAVI12(r) ASICREV_IS(r, NAVI12) +#define ASICREV_IS_NAVI14(r) ASICREV_IS(r, NAVI14) #endif // _AMDGPU_ASIC_ADDR_H diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index c51a442b540..e290cdc8ee5 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -323,7 +323,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->name = "RAVEN2"; } - if (info->family >= CHIP_VEGA10) + if (info->family >= CHIP_NAVI10) + info->chip_class = GFX10; + else if (info->family >= CHIP_VEGA10) info->chip_class = GFX9; else if (info->family >= CHIP_TONGA) info->chip_class = GFX8; @@ -413,7 +415,11 @@ bool ac_query_gpu_info(int fd, void *dev_p, fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n"); info->clock_crystal_freq = 1; } - info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */ + if (info->chip_class >= GFX10) { + info->tcc_cache_line_size = 128; + } else { + info->tcc_cache_line_size = 64; + } info->gb_addr_config = amdinfo->gb_addr_cfg; if (info->chip_class == GFX9) { info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg); diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c index 7ee9a490da0..c153d60d35b 100644 --- a/src/amd/common/ac_llvm_util.c +++ b/src/amd/common/ac_llvm_util.c @@ -133,6 +133,12 @@ const char *ac_get_llvm_processor_name(enum radeon_family family) return "gfx906"; case CHIP_RAVEN2: return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902"; + case CHIP_NAVI10: + return "gfx1010"; + case CHIP_NAVI12: + return "gfx1011"; + case CHIP_NAVI14: + return "gfx1012"; default: return ""; } @@ -149,8 +155,9 @@ static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, LLVMTargetRef target = ac_get_llvm_target(triple); snprintf(features, sizeof(features), - "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s", + "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s%s", HAVE_LLVM >= 0x0800 ? "" : ",+vgpr-spilling", + family >= CHIP_NAVI10 ? ",+wavefrontsize64,-wavefrontsize32" : "", tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "", tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "", tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "", diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h index acc7673bee1..7914f363230 100644 --- a/src/amd/common/amd_family.h +++ b/src/amd/common/amd_family.h @@ -97,6 +97,9 @@ enum radeon_family { CHIP_VEGA20, CHIP_RAVEN, CHIP_RAVEN2, + CHIP_NAVI10, + CHIP_NAVI12, + CHIP_NAVI14, CHIP_LAST, }; @@ -113,6 +116,7 @@ enum chip_class { GFX7, GFX8, GFX9, + GFX10, }; #endif diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index 562759a9210..11dcf942c12 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -65,7 +65,9 @@ static void handle_env_var_force_family(struct amdgpu_winsys *ws) ws->info.family = i; ws->info.name = "GCN-NOOP"; - if (i >= CHIP_VEGA10) + if (i >= CHIP_NAVI10) + ws->info.chip_class = GFX10; + else if (i >= CHIP_VEGA10) ws->info.chip_class = GFX9; else if (i >= CHIP_TONGA) ws->info.chip_class = GFX8; -- 2.30.2