From 5368a1c49ae9b6598415e21f9a13e775b1ebe438 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 19 Mar 2021 18:36:33 +0000 Subject: [PATCH] make dz consistent in SVP64 --- openpower/sv/ldst.mdwn | 6 +++--- openpower/sv/svp64.mdwn | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 57f55fd0f..49341eaa7 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -127,7 +127,7 @@ The table for [[sv/svp64]] for `immed(RA)` is: | 0-1 | 2 | 3 4 | description | | --- | --- |---------|-------------------------- | -| 00 | els | sz dz | normal mode | +| 00 | els | dz sz | normal mode | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | | 01 | inv | els RC1 | Rc=0: ffirst z/nonz | | 10 | N | dz els | sat mode: N=0/1 u/s | @@ -165,11 +165,11 @@ The modes for `RA+RB` indexed version are slightly different: | 0-1 | 2 | 3 4 | description | | --- | --- |---------|-------------------------- | -| 00 | 0 | sz dz | normal mode | +| 00 | 0 | dz sz | normal mode | | 00 | 1 | rsvd | reserved | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | | 01 | inv | dz RC1 | Rc=0: ffirst z/nonz | -| 10 | N | sz dz | sat mode: N=0/1 u/s | +| 10 | N | dz sz | sat mode: N=0/1 u/s | | 11 | inv | CR-bit | Rc=1: pred-result CR sel | | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz | diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 6d79709b7..9de64d899 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -202,12 +202,12 @@ The Mode table for operations except LD/ST is laid out as follows: | 0-1 | 2 | 3 4 | description | | --- | --- |---------|-------------------------- | -| 00 | 0 | sz dz | normal mode | +| 00 | 0 | dz sz | normal mode | | 00 | 1 | dz CRM | reduce mode (mapreduce), SUBVL=1 | | 00 | 1 | SVM CRM | subvector reduce mode, SUBVL>1 | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | | 01 | inv | dz RC1 | Rc=0: ffirst z/nonz | -| 10 | N | sz dz | sat mode: N=0/1 u/s | +| 10 | N | dz sz | sat mode: N=0/1 u/s | | 11 | inv | CR-bit | Rc=1: pred-result CR sel | | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz | -- 2.30.2