From 53694d6a8ea03556ccc633df2f3acbfea74e26eb Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 23 Dec 2020 12:39:13 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index df71ba5c3..0053bf3af 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -194,7 +194,7 @@ augmented to 7 bits in length. Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing. -## RM-2P-1S1D +## RM-2P-1S1D/2S | Field Name | Field bits | Description | |------------|------------|----------------------------| @@ -205,6 +205,8 @@ Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing. +`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2. + ## RM-2P-2S1D/1S2D The primary purpose for this encoding is for Twin Predication on LOAD -- 2.30.2