From 53741fc714dfe7ed353d96796fec37b43c33009c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Jul 2020 20:27:56 +0100 Subject: [PATCH] quick test showing how left/right mask work --- src/soc/fu/shift_rot/rotator.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/soc/fu/shift_rot/rotator.py b/src/soc/fu/shift_rot/rotator.py index 8a20b0ba..f5652ef6 100644 --- a/src/soc/fu/shift_rot/rotator.py +++ b/src/soc/fu/shift_rot/rotator.py @@ -1,10 +1,12 @@ # Manual translation and adaptation of rotator.vhdl from microwatt into nmigen # +from nmigen.compat.sim import run_simulation from nmigen import (Elaboratable, Signal, Module, Const, Cat, Repl, unsigned, signed) from soc.fu.shift_rot.rotl import ROTL from nmutil.extend import exts +from nmigen.back.pysim import Settle # note BE bit numbering @@ -160,3 +162,21 @@ class Rotator(Elaboratable): return m +if __name__ == '__main__': + + m = Module() + comb = m.d.comb + mr = Signal(64) + mb = Signal(6) + comb += mr.eq(left_mask(m, mb)) + + def loop(): + for i in range(64): + yield mb.eq(63-i) + yield Settle() + res = yield mr + print (i, hex(res)) + + run_simulation(m, [loop()], + vcd_name="test_mask.vcd") + -- 2.30.2