From 53763d71664e428f8cacd792e58a0f8ecafb1909 Mon Sep 17 00:00:00 2001 From: klehman Date: Thu, 9 Sep 2021 09:01:50 -0400 Subject: [PATCH] HDL int reg added --- src/soc/simple/test/teststate.py | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py index 6266868d..ad361b40 100644 --- a/src/soc/simple/test/teststate.py +++ b/src/soc/simple/test/teststate.py @@ -1,5 +1,4 @@ from openpower.decoder.power_enums import XER_bits -import copy class SimState: @@ -30,4 +29,17 @@ class SimState: def get_pc(self): self.pc = self.sim.pc.CIA.value -# class HDLState: + +class HDLState: + def __init__(self, core): + self.core = core + + def get_intregs(self): + self.intregs = [] + for i in range(32): + if self.core.regs.int.unary: + rval = yield self.core.regs.int.regs[i].reg + else: + rval = yield self.core.regs.int.memory_array[i] + self.intregs.append(rval) + print("class core int regs", list(map(hex, intregs))) -- 2.30.2