From 537bf9ac0210e40fe8a67d3f4c08f451616d050b Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Sun, 6 Aug 2017 19:04:57 +0000 Subject: [PATCH] target_attr_10.c: Add -mcpu=generic. 2017-08-06 Andrew Pinski * gcc.target/aarch64/target_attr_10.c: Add -mcpu=generic. * gcc.target/aarch64/target_attr_13.c: LIkewise. * gcc.target/aarch64/target_attr_15.c: LIkewise. * gcc.target/aarch64/target_attr_4.c: Likewise. * gcc.target/aarch64/target_attr_1.c: Add -march=armv8-a. * gcc.target/aarch64/target_attr_2.c: Likewise. * gcc.target/aarch64/target_attr_7.c: Likewise. * gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise. * gcc.target/aarch64/target_attr_crypto_ice_2.c: Likewise. * gcc.target/aarch64/target_attr_3.c: Add -mcpu=generic -march=armv8-a. From-SVN: r250904 --- gcc/testsuite/ChangeLog | 13 +++++++++++++ gcc/testsuite/gcc.target/aarch64/target_attr_1.c | 2 +- gcc/testsuite/gcc.target/aarch64/target_attr_10.c | 2 +- gcc/testsuite/gcc.target/aarch64/target_attr_13.c | 2 +- gcc/testsuite/gcc.target/aarch64/target_attr_15.c | 2 +- gcc/testsuite/gcc.target/aarch64/target_attr_2.c | 2 +- gcc/testsuite/gcc.target/aarch64/target_attr_3.c | 2 +- gcc/testsuite/gcc.target/aarch64/target_attr_4.c | 2 +- gcc/testsuite/gcc.target/aarch64/target_attr_7.c | 2 +- .../gcc.target/aarch64/target_attr_crypto_ice_1.c | 2 +- .../gcc.target/aarch64/target_attr_crypto_ice_2.c | 2 +- 11 files changed, 23 insertions(+), 10 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a6a2798e916..7d5352b3e29 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2017-08-06 Andrew Pinski + + * gcc.target/aarch64/target_attr_10.c: Add -mcpu=generic. + * gcc.target/aarch64/target_attr_13.c: LIkewise. + * gcc.target/aarch64/target_attr_15.c: LIkewise. + * gcc.target/aarch64/target_attr_4.c: Likewise. + * gcc.target/aarch64/target_attr_1.c: Add -march=armv8-a. + * gcc.target/aarch64/target_attr_2.c: Likewise. + * gcc.target/aarch64/target_attr_7.c: Likewise. + * gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise. + * gcc.target/aarch64/target_attr_crypto_ice_2.c: Likewise. + * gcc.target/aarch64/target_attr_3.c: Add -mcpu=generic -march=armv8-a. + 2017-08-06 Andrew Pinski * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: Pass diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_1.c index 0527d0c3d61..4a3a1ee233a 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_1.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx -dA" } */ +/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */ /* Test that cpu attribute overrides the command-line -mcpu. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_10.c b/gcc/testsuite/gcc.target/aarch64/target_attr_10.c index 6d0577178f0..18499047112 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_10.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=armv8-a+simd" } */ +/* { dg-options "-O2 -march=armv8-a+simd -mcpu=generic" } */ /* Using a SIMD intrinsic from a function tagged with nosimd should fail due to inlining rules. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_13.c b/gcc/testsuite/gcc.target/aarch64/target_attr_13.c index 0f81e9aa587..d5bee3a7b90 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_13.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_13.c @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-O2 -march=armv8-a+crc+crypto" } */ +/* { dg-options "-O2 -march=armv8-a+crc+crypto -mcpu=generic" } */ #include "arm_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_15.c b/gcc/testsuite/gcc.target/aarch64/target_attr_15.c index 2d8c7b955ce..108b372e4cc 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_15.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_15.c @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-march=armv8-a+crypto -save-temps" } */ +/* { dg-options "-march=armv8-a+crypto -mcpu=generic -save-temps" } */ /* Check that "+nothing" clears the ISA flags. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_2.c b/gcc/testsuite/gcc.target/aarch64/target_attr_2.c index 39bb6e7dd36..f84342d889f 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_2.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_2.c @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-O2 -mcpu=cortex-a57 -ftree-vectorize -fdump-tree-vect-all" } */ +/* { dg-options "-O2 -mcpu=cortex-a57 -march=armv8-a -ftree-vectorize -fdump-tree-vect-all" } */ /* The various ways to turn off simd availability should turn off vectorization. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_3.c b/gcc/testsuite/gcc.target/aarch64/target_attr_3.c index 9f9c27654f6..eacec5a6552 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_3.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -save-temps" } */ +/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -march=armv8-a -mcpu=generic -save-temps" } */ /* Check that the attribute overrides the command line option and the fix is applied once. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_4.c b/gcc/testsuite/gcc.target/aarch64/target_attr_4.c index d98ba42303f..e0114084800 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_4.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_4.c @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-O2 -march=armv8-a+nocrc -save-temps" } */ +/* { dg-options "-O2 -march=armv8-a+nocrc -mcpu=generic -save-temps" } */ #include "arm_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_7.c b/gcc/testsuite/gcc.target/aarch64/target_attr_7.c index 818d327705f..6067ffed30e 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_7.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx -dA" } */ +/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */ /* Make sure that #pragma overrides command line option and target attribute overrides the pragma. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c index 42f14c461a2..c74cc900f98 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx+nofp" } */ +/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c index d6e7b681832..d0a62b83351 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx+nofp" } */ +/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */ /* Make sure that we don't ICE when dealing with vector parameters in a simd-tagged function within a non-simd translation unit. */ -- 2.30.2