From 537d9ca6a39af4288e71c6e1c09b5104a203111b Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 Aug 2018 07:36:18 +0100
Subject: [PATCH] add SDRAM clock output

---
 src/spec/i_class.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/spec/i_class.py b/src/spec/i_class.py
index 37ad622..cee50e1 100644
--- a/src/spec/i_class.py
+++ b/src/spec/i_class.py
@@ -11,7 +11,7 @@ def pinspec():
         'A': (28, 4),
         'B': (18, 4),
         'C': (24, 1),
-        'D': (92, 1),
+        'D': (93, 1),
     }
     fixedpins = {
         'CTRL_SYS': [
@@ -106,7 +106,7 @@ def pinspec():
     ps.flexbus2("", ('C', 0), 0)
 
     ps.sdram1("", ('D', 0), 0)
-    ps.sdram3("", ('D', 35), 0)
+    ps.sdram3("", ('D', 36), 0)
 
     # Scenarios below can be spec'd out as either "find first interface"
     # by name/number e.g. SPI1, or as "find in bank/mux" which must be
-- 
2.30.2