From 53a83d79a22872c9813932e97331399ecff237f5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 21 Jun 2019 09:18:16 +0100 Subject: [PATCH] add to questions --- simple_v_extension/specification.mdwn | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index f76d8b8a9..d08ef3f03 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -2320,6 +2320,13 @@ Open Questions: * Is it necessary to stick to the RISC-V 1.5 format? Why not go with using the 15th bit to allow 80 + 16\*0bnnnn bits? Perhaps to be sane, limit to 256 bits (16 times 0-11). +* Could a "hint" be used to set which operations are parallel and which + are sequential? +* Could a new sub-instruction opcode format be used, one that does not + conform precisely to RISC-V rules, but *unpacks* to RISC-V opcodes? + no need for byte or bit-alignment +* Could a hardware compression algorithm be deployed? Quite likely, + because of the sub-execution context (sub-VLIW PC) ## Limitations on instructions. -- 2.30.2