From 53b3468780c349d6a17572cfe617495fa3b0a281 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 20 Sep 2019 19:36:19 +0000 Subject: [PATCH] hdl.mem: use 1 as reset value for ReadPort.en. This is necessary for consistency, since for transparent read ports, we currently do not support .en at all (it is fixed at 1) due to YosysHQ/yosys#760. Before this commit, changing port transparency would require adding or removing an assignment to .en, which is confusing and error-prone. Also, most read ports are always enabled, so this behavior is also convenient. --- nmigen/hdl/mem.py | 2 +- nmigen/test/test_hdl_mem.py | 1 + nmigen/test/test_sim.py | 3 +-- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py index 181e906..dfeee87 100644 --- a/nmigen/hdl/mem.py +++ b/nmigen/hdl/mem.py @@ -88,7 +88,7 @@ class ReadPort(Elaboratable): self.data = Signal(memory.width, name="{}_r_data".format(memory.name), src_loc_at=2) if self.domain != "comb" and not transparent: - self.en = Signal(name="{}_r_en".format(memory.name), src_loc_at=2) + self.en = Signal(name="{}_r_en".format(memory.name), src_loc_at=2, reset=1) else: self.en = Const(1) diff --git a/nmigen/test/test_hdl_mem.py b/nmigen/test/test_hdl_mem.py index 84e1aed..332dd5e 100644 --- a/nmigen/test/test_hdl_mem.py +++ b/nmigen/test/test_hdl_mem.py @@ -60,6 +60,7 @@ class MemoryTestCase(FHDLTestCase): self.assertEqual(rdport.transparent, False) self.assertEqual(len(rdport.en), 1) self.assertIsInstance(rdport.en, Signal) + self.assertEqual(rdport.en.reset, 1) def test_read_port_asynchronous(self): mem = Memory(width=8, depth=4) diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py index 7979e49..adfad0e 100644 --- a/nmigen/test/test_sim.py +++ b/nmigen/test/test_sim.py @@ -548,9 +548,8 @@ class SimulatorIntegrationTestCase(FHDLTestCase): def process(): yield self.wrport.data.eq(0x33) yield self.wrport.en.eq(1) - yield self.rdport.en.eq(1) yield - self.assertEqual((yield self.rdport.data), 0x00) + self.assertEqual((yield self.rdport.data), 0xaa) yield self.assertEqual((yield self.rdport.data), 0xaa) yield Delay(1e-6) # let comb propagate -- 2.30.2