From 53bab0e1b9a48ed8b43a43aafcacc44c66f13e48 Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Tue, 17 Oct 2023 14:37:46 +0100 Subject: [PATCH] added english language description for lwzupx instruction in the pifixedload.mdwm --- openpower/isa/pifixedload.mdwn | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn index f7528503..748b098e 100644 --- a/openpower/isa/pifixedload.mdwn +++ b/openpower/isa/pifixedload.mdwn @@ -202,6 +202,16 @@ Pseudo-code: RT <- [0] * 32 || MEM(EA, 4) RA <- (RA) + (RB) +Description: + + Let the effective address (EA) be the register RA. + The halfword in storage addressed by EA is loaded into RT[48:63]. + RT[0:47] are filled with a copy of bit 0 of the loaded halfword. + + The sum (RA) + (RB) is placed into register RA. + + If RA=0 or RA=RT, the instruction form is invalid. + Special Registers Altered: None -- 2.30.2