From 53befce7f2b35e69ad78b945fc06403c753480a5 Mon Sep 17 00:00:00 2001
From: Will Schmidt <will_schmidt@vnet.ibm.com>
Date: Tue, 10 Oct 2017 16:32:54 +0000
Subject: [PATCH] |-------* gcc.target/powerpc/fold-vec-splat-16.c: New
 |-------* gcc.target/powerpc/fold-vec-splat-32.c: New.

2017-10-10  Will Schmidt  <will_schmidt@vnet.ibm.com>

[testsuite]
|-------* gcc.target/powerpc/fold-vec-splat-16.c: New
|-------* gcc.target/powerpc/fold-vec-splat-32.c: New.
|-------* gcc.target/powerpc/fold-vec-splat-8.c: New.

From-SVN: r253591
---
 gcc/testsuite/ChangeLog                       |  6 +++
 .../gcc.target/powerpc/fold-vec-splat-16.c    | 46 +++++++++++++++++++
 .../gcc.target/powerpc/fold-vec-splat-32.c    | 46 +++++++++++++++++++
 .../gcc.target/powerpc/fold-vec-splat-8.c     | 46 +++++++++++++++++++
 4 files changed, 144 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-splat-16.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-splat-32.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 29b5277180e..e73439f2df1 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2017-10-10  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* gcc.target/powerpc/fold-vec-splat-16.c: New
+	* gcc.target/powerpc/fold-vec-splat-32.c: New.
+	* gcc.target/powerpc/fold-vec-splat-8.c: New.
+
 2017-10-10  Will Schmidt <will_schmidt@vnet.ibm.com>
 
 	* gcc.target/powerpc/fold-vec-splats-char.c: New.
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-16.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-16.c
new file mode 100644
index 00000000000..bb4a8d2fa55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-16.c
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_splat with int
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+vector signed short
+testss_1 ()
+{
+  return vec_splat_s16 (5);
+}
+
+vector signed short
+testss_2 ()
+{
+  return vec_splat_s16 (-5);
+}
+
+vector signed short
+testss_3 ()
+{
+  return vec_splat_s16 (15);
+}
+
+vector unsigned short
+testus_1 ()
+{
+  return vec_splat_u16 (5);
+}
+
+vector unsigned short
+testus_2 ()
+{
+  return vec_splat_u16 (-5);
+}
+
+vector unsigned short
+testus_3 ()
+{
+  return vec_splat_u16 (15);
+}
+
+/* { dg-final { scan-assembler-times "vspltish" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-32.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-32.c
new file mode 100644
index 00000000000..f59849edf3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-32.c
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_splat with int
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+testsi_1 ()
+{
+  return vec_splat_s32 (5);
+}
+
+vector signed int
+testsi_2 ()
+{
+  return vec_splat_s32 (-5);
+}
+
+vector signed int
+testsi_3 ()
+{
+ return vec_splat_s32 (15);
+}
+
+vector unsigned int
+testui_1 ()
+{
+  return vec_splat_u32 (5);
+}
+
+vector unsigned int
+testui_2 ()
+{
+  return vec_splat_u32 (-5);
+}
+
+vector unsigned int
+testui_3 ()
+{
+  return vec_splat_u32 (15);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c
new file mode 100644
index 00000000000..679fcb3bc5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_splat with int
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed char
+testsc_1 ()
+{
+  return vec_splat_s8 (5);
+}
+
+vector signed char
+testsc_2 ()
+{
+  return vec_splat_s8 (-5);
+}
+
+vector signed char
+testsc_3 ()
+{
+  return vec_splat_s8 (15);
+}
+
+vector unsigned char
+testuc_1 ()
+{
+  return vec_splat_u8 (5);
+}
+
+vector unsigned char
+testuc_2 ()
+{
+  return vec_splat_u8 (-5);
+}
+
+vector unsigned char
+testuc_3 ()
+{
+  return vec_splat_u8 (15);
+}
+
+/* { dg-final { scan-assembler-times "vspltisb" 6 } } */
-- 
2.30.2