From 53c378fd3f2359e9866b95eb42b2eac8034d8a74 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Jul 2020 21:20:30 +0100 Subject: [PATCH] add clock domain using snippet taken from random file --- src/soc/litex/sim.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/litex/sim.py b/src/soc/litex/sim.py index 1a4a2d66..8707ba00 100644 --- a/src/soc/litex/sim.py +++ b/src/soc/litex/sim.py @@ -4,8 +4,11 @@ # This file is Copyright (c) 2020 Dolu1990 # License: BSD +import os import argparse +from migen import ClockDomain + from litex.build.generic_platform import Pins, Subsignal from litex.build.sim import SimPlatform from litex.build.sim.config import SimConfig @@ -73,6 +76,12 @@ class SoCSMP(SoCCore): self.platform.name = "sim" self.add_constant("SIM") + self.clock_domains.cd_sys = ClockDomain() + self.comb += [ + self.cd_sys.clk.eq(platform.request("sys_clk")), + self.cd_sys.rst.eq(platform.request("sys_rst")) + ] + # SDRAM ---------------------------------------------------------- phy_settings = get_sdram_phy_settings( memtype = "DDR3", -- 2.30.2