From 53c4daaeccb6db2c380dd3751928473e666aaea5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Dec 2021 13:01:58 +0000 Subject: [PATCH] convert PortInterfaceBase to pass msr not msr_pr https://bugs.libre-soc.org/show_bug.cgi?id=756 --- src/soc/experiment/pimem.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 0c5ac8d8..58f6c4e8 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -260,7 +260,7 @@ class PortInterfaceBase(Elaboratable): comb += lenexp.len_i.eq(pi.data_len) comb += lenexp.addr_i.eq(lsbaddr) with m.If(pi.addr.ok & adrok_l.qn): - self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr) + self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, msr) comb += pi.addr_ok_o.eq(1) # acknowledge addr ok sync += adrok_l.s.eq(1) # and pull "ack" latch @@ -272,7 +272,7 @@ class PortInterfaceBase(Elaboratable): comb += lenexp.len_i.eq(pi.data_len) comb += lenexp.addr_i.eq(lsbaddr) with m.If(pi.addr.ok): - self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr, + self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, msr, pi.is_dcbz_i) with m.If(adrok_l.qn & self.pi.exc_o.happened==0): comb += pi.addr_ok_o.eq(1) # acknowledge addr ok -- 2.30.2