From 53c9d38e6caa4171c0b86222a9868751e137b00c Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Fri, 10 Jul 2020 16:13:40 +0200 Subject: [PATCH] Add more R/W operations in test_soc --- gram/test/test_soc.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py index 4d243b8..2c2fe43 100644 --- a/gram/test/test_soc.py +++ b/gram/test/test_soc.py @@ -170,11 +170,17 @@ class SocTestCase(FHDLTestCase): yield from wb_write(soc.bus, 0x10000000 >> 2, 0xF00DFACE, 0xF, 128) yield from wb_write(soc.bus, 0x10000004 >> 2, 0x12345678, 0xF, 128) + yield from wb_write(soc.bus, 0x10000008 >> 2, 0x00BA0BAB, 0xF, 128) res = yield from wb_read(soc.bus, 0x10000000 >> 2, 0xF, 128) self.assertEqual(res, 0xF00DFACE) + yield from wb_write(soc.bus, 0x10000008 >> 2, 0xCAFE1000, 0xF, 128) + res = yield from wb_read(soc.bus, 0x10000004 >> 2, 0xF, 128) self.assertEqual(res, 0x12345678) + res = yield from wb_read(soc.bus, 0x10000008 >> 2, 0xF, 128) + self.assertEqual(res, 0xCAFE1000) + runSimulation(m, process, "test_soc_interleaved_read_write.vcd") -- 2.30.2