From 53d9c188b8eb1fed28a914d175ecd88f4385af87 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Tue, 23 Mar 2021 20:25:33 +0100 Subject: [PATCH] Uodated doDesign for the latest ls180 (sram variant). --- experiments9/tsmc_c018/Makefile | 2 +- experiments9/tsmc_c018/coriolis2/settings.py | 4 ++-- experiments9/tsmc_c018/doDesign.py | 25 +++++++++++++------- 3 files changed, 19 insertions(+), 12 deletions(-) diff --git a/experiments9/tsmc_c018/Makefile b/experiments9/tsmc_c018/Makefile index c24742d..0d5756a 100755 --- a/experiments9/tsmc_c018/Makefile +++ b/experiments9/tsmc_c018/Makefile @@ -9,7 +9,7 @@ CORE = ls180 USE_CLOCKTREE = Yes USE_DEBUG = No - RM_CHIP = Yes + RM_CHIP = Yes VST_FLAGS = --vst-no-lowercase #NETLISTS = $(shell cat cells.lst) diff --git a/experiments9/tsmc_c018/coriolis2/settings.py b/experiments9/tsmc_c018/coriolis2/settings.py index 1142e7a..c3aac12 100644 --- a/experiments9/tsmc_c018/coriolis2/settings.py +++ b/experiments9/tsmc_c018/coriolis2/settings.py @@ -29,8 +29,8 @@ LibreSOCMem.setup() with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: cfg.misc.catchCore = False - cfg.misc.minTraceLevel = 14700 - cfg.misc.maxTraceLevel = 14800 + cfg.misc.minTraceLevel = 12300 + cfg.misc.maxTraceLevel = 12400 cfg.misc.info = False cfg.misc.paranoid = False cfg.misc.bug = False diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py index 928a6f0..bb6cd27 100644 --- a/experiments9/tsmc_c018/doDesign.py +++ b/experiments9/tsmc_c018/doDesign.py @@ -120,7 +120,8 @@ def scriptMain (**kw): #helpers.setTraceLevel( 550 ) #Breakpoint.setStopLevel( 99 ) rvalue = True - coreSize = u(5850.0) + #coreSize = u(37*90.0) + coreSize = u(61*90.0) chipBorder = u(2*214.0 + 10*13.0) ioSpecs = IoSpecs() #pinmuxFile = './non_generated/litex_pinpads.json' @@ -209,13 +210,13 @@ def scriptMain (**kw): ls180Conf.cfg.katana.vTracksReservedLocal = 3 ls180Conf.cfg.katana.hTracksReservedMin = 3 ls180Conf.cfg.katana.vTracksReservedMin = 1 - ls180Conf.cfg.block.spareSide = u(100) + ls180Conf.cfg.block.spareSide = u(9*13) ls180Conf.cfg.chip.supplyRailWidth = u(35) ls180Conf.cfg.chip.supplyRailPitch = u(90) ls180Conf.editor = editor ls180Conf.useSpares = True ls180Conf.useClockTree = True - ls180Conf.useHFNS = False + ls180Conf.useHFNS = True ls180Conf.bColumns = 2 ls180Conf.bRows = 2 ls180Conf.chipConf.name = 'chip' @@ -234,11 +235,17 @@ def scriptMain (**kw): chipBuilder.doChipFloorplan() with UpdateSession(): - tiPath = 'subckt_38695_test_issuer.subckt_1_ti.' - sramPaths = [ tiPath+'subckt_3695_sram4k_0.subckt_144_SPBlock_512W64B8W' - , tiPath+'subckt_3696_sram4k_1.subckt_144_SPBlock_512W64B8W' - , tiPath+'subckt_3697_sram4k_2.subckt_144_SPBlock_512W64B8W' - , tiPath+'subckt_3698_sram4k_3.subckt_144_SPBlock_512W64B8W' + # Thoses ids are dependent on Yosys. They need to be adjusted whenever + # the design changes. + #tiId = 38695 + tiId = 38381 + #sramId = 3695 + sramId = 3300 + tiPath = 'subckt_{}_test_issuer.subckt_1_ti.'.format(tiId) + sramPaths = [ tiPath+'subckt_{}_sram4k_0.subckt_144_SPBlock_512W64B8W'.format(sramId) + , tiPath+'subckt_{}_sram4k_1.subckt_144_SPBlock_512W64B8W'.format(sramId+1) + , tiPath+'subckt_{}_sram4k_2.subckt_144_SPBlock_512W64B8W'.format(sramId+2) + , tiPath+'subckt_{}_sram4k_3.subckt_144_SPBlock_512W64B8W'.format(sramId+3) ] sram = DataBase.getDB().getCell( 'SPBlock_512W64B8W' ) if not sram: @@ -256,7 +263,7 @@ def scriptMain (**kw): ) ls180Conf.placeArea = Box( coreAb.getXMin() , coreAb.getYMin() - , coreAb.getXMax() + , coreAb.getXMax() - chipBuilder.conf.sliceStep , coreAb.getYMax() - sramAb.getHeight() - 2*sliceHeight ) Breakpoint.stop( 99, 'After core placement.' ) -- 2.30.2