From 5415b521befa5782cc41a733e313a707ee3b251f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 24 Sep 2018 22:49:30 +0200 Subject: [PATCH] targets/arty: use new clock abstraction module (compile, untested on board) --- litex/boards/targets/arty.py | 75 ++++++------------------------------ 1 file changed, 12 insertions(+), 63 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 021d2678..bdd8bfa0 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -3,10 +3,10 @@ import argparse from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import arty +from litex.soc.cores.clock import * from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -19,75 +19,24 @@ from liteeth.core.mac import LiteEthMAC class _CRG(Module): - def __init__(self, platform): + def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() - self.clock_domains.cd_clk50 = ClockDomain() - - clk100 = platform.request("clk100") - rst = ~platform.request("cpu_reset") - - pll_locked = Signal() - pll_fb = Signal() - pll_sys = Signal() - pll_sys4x = Signal() - pll_sys4x_dqs = Signal() - pll_clk200 = Signal() - pll_clk50 = Signal() - self.specials += [ - Instance("PLLE2_BASE", - p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - - # VCO @ 1600 MHz - p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0, - p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1, - i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, - - # 100 MHz - p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=pll_sys, - - # 400 MHz - p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=pll_sys4x, - - # 400 MHz dqs - p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=90.0, - o_CLKOUT2=pll_sys4x_dqs, - - # 200 MHz - p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0, - o_CLKOUT3=pll_clk200, - - # 50MHz - p_CLKOUT4_DIVIDE=32, p_CLKOUT4_PHASE=0.0, - o_CLKOUT4=pll_clk50 - ), - Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), - Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk), - Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), - Instance("BUFG", i_I=pll_clk50, o_O=self.cd_clk50.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst), - AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst), - AsyncResetSynchronizer(self.cd_clk50, ~pll_locked | rst), - ] - reset_counter = Signal(4, reset=15) - ic_reset = Signal(reset=1) - self.sync.clk200 += \ - If(reset_counter != 0, - reset_counter.eq(reset_counter - 1) - ).Else( - ic_reset.eq(0) - ) - self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) + self.submodules.pll = pll = S7PLL() + self.comb += pll.reset.eq(~platform.request("cpu_reset")) + pll.register_clkin(platform.request("clk100"), 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq, phase=90) + pll.create_clkout(self.cd_clk200, 200e6) + pll.add_idelayctrl(self.cd_clk200) eth_clk = Signal() self.specials += [ - Instance("BUFR", p_BUFR_DIVIDE="4", i_CE=1, i_CLR=0, i_I=clk100, o_O=eth_clk), + Instance("BUFR", p_BUFR_DIVIDE="4", i_CE=1, i_CLR=0, i_I=self.cd_sys.clk, o_O=eth_clk), Instance("BUFG", i_I=eth_clk, o_O=platform.request("eth_ref_clk")), ] @@ -105,7 +54,7 @@ class BaseSoC(SoCSDRAM): integrated_sram_size=0x8000, **kwargs) - self.submodules.crg = _CRG(platform) + self.submodules.crg = _CRG(platform, sys_clk_freq) # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) -- 2.30.2