From 5418637f0cfd15880e707d9b7d7254e8043ae7f5 Mon Sep 17 00:00:00 2001 From: Daniel Benusovich Date: Tue, 12 Mar 2019 22:47:47 -0700 Subject: [PATCH] Replace RegisterFile with Memory. --- TLB/src/TLB.py | 56 ++++++++++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 24 deletions(-) diff --git a/TLB/src/TLB.py b/TLB/src/TLB.py index 5299caec..58379586 100644 --- a/TLB/src/TLB.py +++ b/TLB/src/TLB.py @@ -3,7 +3,6 @@ from nmigen.cli import main from PermissionValidator import PermissionValidator from Cam import Cam -from RegisterFile import RegisterFile # The expected form of the data is # Item (Bits) @@ -26,9 +25,8 @@ class TLB(): self.state = 0 # L1 Cache Modules L1_size = 8 - bits_for_LRU = 8 # Just a placeholder for not. Arbitrary 8! self.cam_L1 = Cam(vma_size, cam_size) - self.reg_file = RegisterFile(pte_size + bits_for_LRU, cam_size) + self.mem_L1 = Memory(asid_size + pte_size, cam_size) # Permission Validator self.perm_validator = PermissionValidator(asid_size + pte_size) @@ -36,9 +34,10 @@ class TLB(): # Inputs self.super = Signal(1) # Supervisor Mode self.super_access = Signal(1) # Supervisor Access - self.command = Signal(2) # 00=None, 01=Search, 10=Write PTE, 11=None + self.command = Signal(2) # 00=None, 01=Search, 10=Write L1, 11=Write L2 self.xwr = Signal(3) # Execute, Write, Read self.mode = Signal(4) # 4 bits for access to Sv48 on Rv64 + self.address_L1 = Signal(max= am_size) self.asid = Signal(asid_size) # Address Space IDentifier (ASID) self.vma = Signal(vma_size) # Virtual Memory Address (VMA) self.pte_in = Signal(pte_size) # To be saved Page Table Entry (PTE) @@ -50,49 +49,60 @@ class TLB(): def elaborate(self, platform): m = Module() - # Add submodules - m.d.submodules.perm_valididator += self.perm_validator - m.d.submodules.cam_L1 += self.cam_L1 - m.d.sumbmodules.reg_file += self.reg_file + # Submodules for L1 Cache + m.d.submodules.cam_L1 = self.cam_L1 + m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port + m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.read_port + # Permission Validator Submodule + m.d.submodules.perm_valididator = self.perm_validator # When MODE specifies translation # TODO add in different bit length handling ie prefix 0s with m.If(self.mode != 0): m.d.comb += [ - self.cam_L1.enable.eq(1), - self.reg_file.enable.eq(1) + self.cam_L1.enable.eq(1) ] with m.Switch(self.command): # Search with m.Case("01"): m.d.comb += [ + write_L1.en.eq(0), self.cam_L1.write_enable.eq(0), self.cam_L1.data_in.eq(self.vma) ] - # Write + # Write L1 + # Expected that the miss will be handled in software with m.Case("10"): - # LRU logic should go in here - # Or take in address for writing? - # Add hardware option/software option - # SO MANY CHOICES + # Memory_L1 Logic + m.d.comb += [ + write_L1.en.eq(1), + write_L1.addr.eq(self.address_L1), + # The first argument is the LSB + write_L1.data.eq(Cat(self.pte, self.asid)) + ] + # CAM_L1 Logic m.d.comb += [ self.cam_L1.write_enable.eq(1), - self.cam_L1.data_in.eq(self.vma) + self.cam_L1.data_in.eq(self.vma), ] + # TODO + #with m.Case("11"): + # Match found in L1 CAM with m.If(self.cam_L1.single_match | self.cam_L1.multiple_match): - # Register file shortcut variables - reg_addrress = self.cam_L1.match_address - reg_data = self.reg_file.register_array[reg_addrress] - # Set all permission validator fields + # Memory shortcut variables + mem_addrress = self.cam_L1.match_address + # Memory Logic + m.d.comb += read_L1.addr(mem_address) + # Permission vVlidator Logic m.d.comb += [ self.hit.eq(1), # Set permission validator data to the correct # register file data according to CAM match # address - self.perm_validator.data.eq(reg_data), + self.perm_validator.data.eq(read_L1.data), # Execute, Read, Write self.perm_validator.xwr.eq(self.xwr), # Supervisor Mode @@ -113,6 +123,7 @@ class TLB(): m.d.comb += [ self.pte_out.eq(0) ] + # Miss Logic with m.Else(): m.d.comb += [ self.hit.eq(0), @@ -130,6 +141,3 @@ class TLB(): ] return m -thing = TLB() -print("Gottem") - -- 2.30.2