From 542fae699844beb4cb78aaec426fbf81ae632f8a Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 19 Dec 2020 21:22:04 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index e3434980f..ff535877a 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -235,14 +235,14 @@ that the spec is shifted up by one bit Mode is an augmentation of SV behaviour. Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first). - 0 1 2 3 4 description - ------------------ - 0 0 M sz CRM reduce mode (M=1). - 0 1 inv CR-bit Rc=1: ffirst CR sel - 0 1 inv sz dz Rc=0: ffirst z/nonz - 1 0 N sz dz sat mode: N=0/1 u/s - 1 1 inv CR-bit Rc=1: pred-result CR sel - 1 1 inv sz dz Rc=0: pred-result z/nonz +| 0-1 | 2 3 4 description | +| --- | ------------------ | +| 00 | M sz CRM reduce mode (M=1). | +| 01 | inv CR-bit Rc=1: ffirst CR sel | +| 01 | inv sz dz Rc=0: ffirst z/nonz | +| 10 | N sz dz sat mode: N=0/1 u/s | +| 11 | inv CR-bit Rc=1: pred-result CR sel | +| 11 | inv sz dz Rc=0: pred-result z/nonz | Mode types: -- 2.30.2