From 5447fb70ab9d4d74ac1445195e38a623fabc4def Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 23 Nov 2023 17:28:52 +0000 Subject: [PATCH] --- nlnet_2023_simplev_riscv.mdwn | 37 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/nlnet_2023_simplev_riscv.mdwn b/nlnet_2023_simplev_riscv.mdwn index 70092a820..f0f60e36a 100644 --- a/nlnet_2023_simplev_riscv.mdwn +++ b/nlnet_2023_simplev_riscv.mdwn @@ -54,27 +54,29 @@ EUR 100,000. Key phases of this project are: -* Assessment of the missing RISC-V instructions (RISC-V RV64GC is only 96 instructions whereas POWER ISA SFFS is 214) which are present in Power ISA 3.0 and required to enable comparable performance from RISC-V with Simple-V/SVP64 - +* Assessment of the missing RISC-V instructions (RISC-V RV64GC is only 96 instructions + whereas POWER ISA SFFS is 214) which are present in Power ISA 3.0 and required to + enable comparable performance from RISC-V with Simple-V * Implementation of the missing RISC-V instructions and instruction forms that makes is comparable with POWER ISA in the Scalar ISA space. - -* Assessment of application of Simple-V Vector Prefixing to SVP64, building on the work already done under NLnet Grant 2019-10-012 - +* Assessment of application of Simple-V Vector Prefixing, building on the work already + done under NLnet Grant 2019-10-012 * Implementation of Simple-V in the Libre-SOC Simulator, ISACaller. - -* Definition of assembler and disassembler for RISC-V instructions and also SVP64 in the Libre-SOC infrastructure. - -* Upgrading (with the newly created instructions and forms) sv-spike assembler development which was prototyped previously for Simple-V Specification: +* Definition of assembler and disassembler for RISC-V instructions and also Simple-V + in the Libre-SOC infrastructure. +* Upgrading (with the newly created instructions and forms) sv-spike assembler + development which was prototyped previously for Simple-V Specification: - -* Adding a comprehensive unit test base for the new instructions which can then be tested against sv-spike as well as ISACaller. Conversion of previously created instructions to the new format used in Libre-SOC, and adding the newly defined and created instructions. +* Adding a comprehensive unit test base for the new instructions which can then be + tested against sv-spike as well as ISACaller. Conversion of previously created + instructions to the new format used in Libre-SOC, and adding the newly defined + and created instructions. +* Documentation, demonstrations and Conference Papers. This will include porting + results of other completed projects (cryptoprimitives, video) from POWER ISA to + the RISC-V/Simple-V environment -* Documentation, demonstrations and Conference Papers. This will include porting results of other completed projects (cryptoprimitives, video) from POWER ISA to the RISC-V/Simple-V/SVP64 environment - -* Research and assessment of ARM7 and i486 (both on opencores.org)as to their feasibility for applying Simple-V Prefixing in future development projects - -By far the largest element of the budget is attributed to labour costs of the team involved from RED Semiconductor and LibreSOC - the project is entirely software-based and no additional hardware requirements are anticipated. A small budget of €5k is allocated to travel for presentation of the project results at industry conferences. +* Research and assessment of ARM7 and i486 (both on opencores.org) as well as ARC + as to their feasibility for applying Simple-V Prefixing in future development projects # Does the project have other funding sources, both past and present? @@ -85,7 +87,8 @@ for this development programme over the past five years, and for the project in ## What are significant technical challenges you expect to solve during the project, if any? -The key technical challenge in this project is the creation of special SVP64 instructions that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community. +The key technical challenge in this project is the creation of special Simple-V +instructions that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community. Based on the previous work of Vectorising RISC-V and POWER using Simple-V already, this project is well within the scope of the experienced teams at LibreSOC and RED Semiconductor, but is extremely detailed and comprehensive, requiring meticulous attention to detail and a very high standard of Project Management. This is a sustained standard and practices developed already over a five year period that will continue to be rigorously applied. -- 2.30.2