From 5478075df7de2c35821a5b2359b69e93e62d764f Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Mon, 25 Sep 2023 18:20:01 +0100 Subject: [PATCH] Added spaces and brackets for lbzux instruction --- openpower/isa/fixedload.mdwn | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index 3bedcb29..5e704587 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -102,11 +102,15 @@ Pseudo-code: RT <- ([0] * (XLEN-8)) || MEM(EA, 1) RA <- EA -Description:Let the effective address (EA) be the sum (RA)+ (RB). -The byte in storage addressed by EA is loaded into -RT56:63. RT0:55 are set to 0. -EA is placed into register RA. -If RA=0 or RA=RT, the instruction form is invalid. +Description: + + Let the effective address (EA) be the sum (RA)+ (RB). + The byte in storage addressed by EA is loaded into + RT[56:63]. RT[0:55] are set to 0. + + EA is placed into register RA. + + If RA=0 or RA=RT, the instruction form is invalid. Special Registers Altered: -- 2.30.2