From 548c42964efee6f9172b3a145afab26101a36f26 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 Jul 2020 00:23:56 +0100 Subject: [PATCH] whoops error in test of dynamic parameter --- src/soc/bus/test/test_minerva.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py index 93434d6e..2bb920a3 100644 --- a/src/soc/bus/test/test_minerva.py +++ b/src/soc/bus/test/test_minerva.py @@ -7,10 +7,6 @@ from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit): def __init__(self, pspec): super().__init__(pspec) - - def elaborate(self, platform): - m = super().elaborate(platform) - comb = m.d.comb # small 32-entry Memory if (hasattr(pspec, "dmem_test_depth") and isinstance(pspec.dmem_test_depth, int)): @@ -19,8 +15,12 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit): depth = 32 print ("TestSRAMBareLoadStoreUnit depth", depth) - self.mem = memory = Memory(width=self.data_wid, depth=depth) - m.submodules.sram = sram = SRAM(memory=memory, granularity=8, + self.mem = Memory(width=self.data_wid, depth=depth) + + def elaborate(self, platform): + m = super().elaborate(platform) + comb = m.d.comb + m.submodules.sram = sram = SRAM(memory=self.mem, granularity=8, features={'cti', 'bte', 'err'}) dbus = self.dbus -- 2.30.2