From 548e2884ec4f56d8a420d725d5f7d40740c690bc Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 7 Jul 2020 10:10:09 +0100 Subject: [PATCH] dev-arm: Move GICv2 intConfig for consistency Every other helper is placed below the respective array storage JIRA: https://gem5.atlassian.net/browse/GEM5-667 Change-Id: I398ac23eb68d84a8e0ed856550bfac8e403a86b3 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31054 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/dev/arm/gic_v2.cc | 2 +- src/dev/arm/gic_v2.hh | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc index 4ef15173d..321337937 100644 --- a/src/dev/arm/gic_v2.cc +++ b/src/dev/arm/gic_v2.cc @@ -72,7 +72,7 @@ GicV2::GicV2(const Params *p) enabled(false), haveGem5Extensions(p->gem5_extensions), itLines(p->it_lines), intEnabled {}, pendingInt {}, activeInt {}, - intPriority {}, cpuTarget {}, intConfig {}, + intPriority {}, intConfig {}, cpuTarget {}, cpuSgiPending {}, cpuSgiActive {}, cpuSgiPendingExt {}, cpuSgiActiveExt {}, cpuPpiPending {}, cpuPpiActive {}, diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh index 600f9afa8..40a95539c 100644 --- a/src/dev/arm/gic_v2.hh +++ b/src/dev/arm/gic_v2.hh @@ -281,6 +281,10 @@ class GicV2 : public BaseGic, public BaseGicRegisters } } + /** 2 bit per interrupt signaling if it's level or edge sensitive + * and if it is 1:N or N:N */ + uint32_t intConfig[INT_BITS_MAX*2]; + /** GICD_ICFGRn * get 2 bit config associated to an interrupt. */ @@ -319,10 +323,6 @@ class GicV2 : public BaseGic, public BaseGicRegisters } } - /** 2 bit per interrupt signaling if it's level or edge sensitive - * and if it is 1:N or N:N */ - uint32_t intConfig[INT_BITS_MAX*2]; - bool isLevelSensitive(ContextID ctx, uint32_t ix) { if (ix == SPURIOUS_INT) { return false; -- 2.30.2