From 5495ebd68d10e9472543dcd9c95e8b5a7a58a36b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:06 -0500 Subject: [PATCH] ARM: Decode the ssub instructions. --- src/arch/arm/isa/formats/data.isa | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index 28fb50194..648e04453 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -240,11 +240,11 @@ def format ArmParallelAddSubtract() {{ case 0x2: return new WarnUnimplemented("ssax", machInst); case 0x3: - return new WarnUnimplemented("ssub16", machInst); + return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); case 0x4: return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); case 0x7: - return new WarnUnimplemented("ssub8", machInst); + return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL); } break; case 0x2: @@ -557,12 +557,14 @@ def format Thumb32DataProcReg() {{ case 0x6: return new WarnUnimplemented("ssax", machInst); case 0x5: - return new WarnUnimplemented("ssub16", machInst); + return new Ssub16RegCc(machInst, rd, + rn, rm, 0, LSL); case 0x0: return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); case 0x4: - return new WarnUnimplemented("ssub8", machInst); + return new Ssub8RegCc(machInst, rd, + rn, rm, 0, LSL); } break; case 0x1: -- 2.30.2