From 5498d5298577c07189ff3f7026eba5c1ee09cc1b Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 3 Mar 2007 17:19:52 +0000
Subject: [PATCH] Filled in with basic x86 stuff. Some things are missing,
 wrong, or nonsensical for x86.

--HG--
extra : convert_revision : 2f7845db6d65b353985b474f7012cfbbaece6a39
---
 src/arch/x86/types.hh | 33 +++++++++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 747d173e4..82fe0eb8a 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -58,10 +58,39 @@
 #ifndef __ARCH_X86_TYPES_HH__
 #define __ARCH_X86_TYPES_HH__
 
-#error X86 is not yet supported!
-
 namespace X86ISA
 {
+    //XXX This won't work
+    typedef uint32_t MachInst;
+    //XXX This won't work either
+    typedef uint64_t ExtMachInst;
+
+    typedef uint64_t IntReg;
+    typedef uint64_t MiscReg;
+
+    //These floating point types are correct for mmx, but not
+    //technically for x87 (80 bits) or at all for xmm (128 bits)
+    typedef double FloatReg;
+    typedef uint64_t FloatRegBits;
+    typedef union
+    {
+        IntReg intReg;
+        FloatReg fpReg;
+        MiscReg ctrlReg;
+    } AnyReg;
+
+    //XXX This is very hypothetical. X87 instructions would need to
+    //change their "context" constantly. It's also not clear how
+    //this would be handled as far as out of order execution.
+    //Maybe x87 instructions are in order?
+    enum RegContextParam
+    {
+        CONTEXT_X87_TOP
+    };
+
+    typedef int RegContextVal;
+
+    typedef uint8_t RegIndex;
 };
 
 #endif // __ARCH_X86_TYPES_HH__
-- 
2.30.2