From 54adb0ac5de40a9154cc115302b9ae9d27e6446c Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 13 Jan 2021 13:53:17 +0000 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 30930641c..a606e2497 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -324,7 +324,9 @@ Here is a table showing progression from 0 to VL-1 when VL=18, where an Integer ... .. CRn.15 15 -This gives an opportunity to minimise modifications to gcc and llvm for any Vectorisation up to a reasonable length of `MVL=16`. The register file is viewed as comprising 16 32-bit Condition Registers. +This gives an opportunity to minimise modifications to gcc and llvm for any Vectorisation up to a reasonable length of `MVL=16`. The register file is viewed as comprising 16 32-bit Condition Registers. + +*There is a downside to this approach*: some of the CRs are not directly accessible even through Scalar EXTRA marking and will require predicated (VINDEXed) cr move operations. ## CR EXTRA mapping table and algorithm -- 2.30.2