From 54af23e258576ba0d8300c17ff444724a534f1c8 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 14 May 2019 10:35:41 +0100
Subject: [PATCH] experimenting with cscore, overlapping instructions

---
 src/experiment/cscore.py | 24 +++++++++++++++++++-----
 src/regfile/regfile.py   |  2 +-
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 0d1fc4d5..9a729be3 100644
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -168,8 +168,8 @@ class Scoreboard(Elaboratable):
 
         # Connect INT Fn Unit global wr/rd pending
         for fu in if_l:
-            m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
-            m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
+            m.d.sync += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
+            m.d.sync += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
 
         # Connect Picker
         #---------
@@ -305,7 +305,7 @@ def scoreboard_sim(dut, alusim):
 
         yield from alusim.check(dut)
 
-    for i in range(20):
+    for i in range(2):
         src1 = randint(1, dut.n_regs-1)
         src2 = randint(1, dut.n_regs-1)
         while True:
@@ -313,12 +313,20 @@ def scoreboard_sim(dut, alusim):
             break
             if dest not in [src1, src2]:
                 break
+        if i == 0:
+            src1 = 6
+            src2 = 6
+            dest = 1
+        else:
+            src1 = 1
+            src2 = 7
+            dest = 1
         #src1 = 2
         #src2 = 3
         #dest = 2 
 
         op = randint(0, 1)
-        #op = 1
+        op = i
         print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
         yield from int_instr(dut, alusim, op, src1, src2, dest)
         yield from print_reg(dut, [3,4,5])
@@ -327,7 +335,11 @@ def scoreboard_sim(dut, alusim):
         for i in range(len(dut.int_insn_i)):
             yield dut.int_insn_i[i].eq(0)
         yield
-        yield
+        while True:
+            issue_o = yield dut.issue_o
+            if issue_o:
+                break
+            yield
 
 
     yield
@@ -338,6 +350,8 @@ def scoreboard_sim(dut, alusim):
     yield
     yield
     yield
+    yield
+    yield
     yield from alusim.check(dut)
 
 
diff --git a/src/regfile/regfile.py b/src/regfile/regfile.py
index 29fbda65..1d732ba8 100644
--- a/src/regfile/regfile.py
+++ b/src/regfile/regfile.py
@@ -10,7 +10,7 @@ import operator
 
 
 class Register(Elaboratable):
-    def __init__(self, width, writethru=False):
+    def __init__(self, width, writethru=True):
         self.width = width
         self.writethru = writethru
         self._rdports = []
-- 
2.30.2