From 54bc87469a4747ea626d1d680f39eb3d282ede5d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 3 Dec 2018 14:58:08 -0500 Subject: [PATCH] radeonsi: make si_cp_wait_mem more configurable MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Tested-by: Dieter Nützel --- src/gallium/drivers/radeonsi/si_fence.c | 6 ++---- src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.h | 2 +- src/gallium/drivers/radeonsi/si_query.c | 3 ++- src/gallium/drivers/radeonsi/si_state_draw.c | 3 ++- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c index d385f445774..b6920c95e34 100644 --- a/src/gallium/drivers/radeonsi/si_fence.c +++ b/src/gallium/drivers/radeonsi/si_fence.c @@ -160,13 +160,11 @@ unsigned si_cp_write_fence_dwords(struct si_screen *screen) return dwords; } -void si_cp_wait_mem(struct si_context *ctx, +void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref, uint32_t mask, unsigned flags) { - struct radeon_cmdbuf *cs = ctx->gfx_cs; - radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); - radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1) | flags); + radeon_emit(cs, WAIT_REG_MEM_MEM_SPACE(1) | flags); radeon_emit(cs, va); radeon_emit(cs, va >> 32); radeon_emit(cs, ref); /* reference value */ diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c index fc2c58854bc..f15f310dd11 100644 --- a/src/gallium/drivers/radeonsi/si_perfcounter.c +++ b/src/gallium/drivers/radeonsi/si_perfcounter.c @@ -701,7 +701,7 @@ static void si_pc_emit_stop(struct si_context *sctx, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE, EOP_DATA_SEL_VALUE_32BIT, buffer, va, 0, SI_NOT_QUERY); - si_cp_wait_mem(sctx, va, 0, 0xffffffff, 0); + si_cp_wait_mem(sctx, cs, va, 0, 0xffffffff, WAIT_REG_MEM_EQUAL); radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0)); diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 4512d2529af..957629e4633 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1213,7 +1213,7 @@ void si_cp_release_mem(struct si_context *ctx, struct r600_resource *buf, uint64_t va, uint32_t new_fence, unsigned query_type); unsigned si_cp_write_fence_dwords(struct si_screen *screen); -void si_cp_wait_mem(struct si_context *ctx, +void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref, uint32_t mask, unsigned flags); void si_init_fence_functions(struct si_context *ctx); void si_init_screen_fence_functions(struct si_screen *screen); diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c index 093643bf684..a1563de6970 100644 --- a/src/gallium/drivers/radeonsi/si_query.c +++ b/src/gallium/drivers/radeonsi/si_query.c @@ -1576,7 +1576,8 @@ static void si_query_hw_get_result_resource(struct si_context *sctx, va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size; va += params.fence_offset; - si_cp_wait_mem(sctx, va, 0x80000000, 0x80000000, 0); + si_cp_wait_mem(sctx, sctx->gfx_cs, va, 0x80000000, + 0x80000000, WAIT_REG_MEM_EQUAL); } sctx->b.launch_grid(&sctx->b, &grid); diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index cfd904e621c..6454491457b 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1056,7 +1056,8 @@ void si_emit_cache_flush(struct si_context *sctx) EOP_DATA_SEL_VALUE_32BIT, sctx->wait_mem_scratch, va, sctx->wait_mem_number, SI_NOT_QUERY); - si_cp_wait_mem(sctx, va, sctx->wait_mem_number, 0xffffffff, 0); + si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff, + WAIT_REG_MEM_EQUAL); } /* Make sure ME is idle (it executes most packets) before continuing. -- 2.30.2