From 54c63275e02c0c57eea24e1d4099e585f04cff6a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 9 Aug 2014 10:56:59 +0800 Subject: [PATCH] platforms/kc705: remove DDR3 multirank pins --- mibuild/platforms/kc705.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py index 8dc4f7f6..7be5635c 100644 --- a/mibuild/platforms/kc705.py +++ b/mibuild/platforms/kc705.py @@ -88,12 +88,10 @@ _io = [ "AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"), IOStandard("SSTL15")), Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")), - Subsignal("cke", Pins("AF10 AE10"), IOStandard("SSTL15")), Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")), Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")), Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("AC12 AE8"), IOStandard("SSTL15")), - Subsignal("odt", Pins("AD8 AC10"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")), Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"), IOStandard("SSTL15")), Subsignal("dq", Pins( @@ -112,7 +110,9 @@ _io = [ IOStandard("DIFF_SSTL15")), Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")), Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")), - Subsignal("rst_n", Pins("AK3"), IOStandard("LVCMOS15")), + Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")), + Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")), Misc("SLEW=FAST"), Misc("VCCAUX_IO=HIGH") ), -- 2.30.2