From 54dad0c2605f905a0e78b4e88a03e7c262ef5c2f Mon Sep 17 00:00:00 2001 From: Richard Kenner Date: Wed, 21 Dec 1994 14:39:36 -0500 Subject: [PATCH] (adddi3, subdi3): New patterns. From-SVN: r8684 --- gcc/config/m68k/m68k.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index f71e9edf708..196df8b678e 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -1854,6 +1854,18 @@ ;; add instructions +(define_insn "adddi3" + [(set (match_operand:DI 0 "register_operand" "=d") + (plus:DI (match_operand:DI 1 "register_operand" "%0") + (match_operand:DI 2 "register_operand" "d")))] + "" + "* +{ + operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1); + return \"add%.l %3,%1\;addx%.l %2,%0\"; +} ") + ;; Note that the middle two alternatives are near-duplicates ;; in order to handle insns generated by reload. ;; This is needed since they are not themselves reloaded, @@ -2274,6 +2286,18 @@ ;; subtract instructions +(define_insn "subdi3" + [(set (match_operand:DI 0 "register_operand" "=d") + (minus:DI (match_operand:DI 1 "register_operand" "0") + (match_operand:DI 2 "register_operand" "d")))] + "" + "* +{ + operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1); + return \"sub%.l %3,%1\;subx%.l %2,%0\"; +} ") + (define_insn "subsi3" [(set (match_operand:SI 0 "general_operand" "=m,r") (minus:SI (match_operand:SI 1 "general_operand" "0,0") -- 2.30.2