From 5500c419159a7e702e76c8abd4008e5a176965ec Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Feb 2015 10:05:04 +0100 Subject: [PATCH] move lm32/mor1kx submodules to extcores --- .gitmodules | 8 ++++---- {verilog => extcores}/lm32/lm32_config.v | 0 extcores/lm32/submodule | 1 + extcores/mor1kx/submodule | 1 + misoclib/gensoc/__init__.py | 6 +++--- verilog/lm32/submodule | 1 - verilog/mor1kx/submodule | 1 - 7 files changed, 9 insertions(+), 9 deletions(-) rename {verilog => extcores}/lm32/lm32_config.v (100%) create mode 160000 extcores/lm32/submodule create mode 160000 extcores/mor1kx/submodule delete mode 160000 verilog/lm32/submodule delete mode 160000 verilog/mor1kx/submodule diff --git a/.gitmodules b/.gitmodules index a952646d..aa337e22 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,8 +1,8 @@ -[submodule "verilog/lm32/submodule"] - path = verilog/lm32/submodule +[submodule "extcores/lm32/submodule"] + path = extcores/lm32/submodule url = https://github.com/m-labs/lm32.git -[submodule "verilog/mor1kx/submodule"] - path = verilog/mor1kx/submodule +[submodule "extcores/mor1kx/submodule"] + path = extcores/mor1kx/submodule url = https://github.com/openrisc/mor1kx.git [submodule "software/compiler-rt"] path = software/compiler-rt diff --git a/verilog/lm32/lm32_config.v b/extcores/lm32/lm32_config.v similarity index 100% rename from verilog/lm32/lm32_config.v rename to extcores/lm32/lm32_config.v diff --git a/extcores/lm32/submodule b/extcores/lm32/submodule new file mode 160000 index 00000000..84b3e3ca --- /dev/null +++ b/extcores/lm32/submodule @@ -0,0 +1 @@ +Subproject commit 84b3e3ca0ad9535acaef201c1482342871358b08 diff --git a/extcores/mor1kx/submodule b/extcores/mor1kx/submodule new file mode 160000 index 00000000..95fc8e43 --- /dev/null +++ b/extcores/mor1kx/submodule @@ -0,0 +1 @@ +Subproject commit 95fc8e432d762e48b42991663cf9d0cdb918e27e diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index e07d9587..9d490ccf 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -75,15 +75,15 @@ class GenSoC(Module): # add CPU Verilog sources if cpu_type == "lm32": - platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), + platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"), "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v", "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v", "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v", "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v", "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") - platform.add_verilog_include_path(os.path.join("verilog", "lm32")) + platform.add_verilog_include_path(os.path.join("extcores", "lm32")) if cpu_type == "or1k": - platform.add_source_dir(os.path.join("verilog", "mor1kx", "submodule", "rtl", "verilog")) + platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog")) def register_rom(self, rom_wb_if, bios_size=0xa000): if self._rom_registered: diff --git a/verilog/lm32/submodule b/verilog/lm32/submodule deleted file mode 160000 index dfd6ca7b..00000000 --- a/verilog/lm32/submodule +++ /dev/null @@ -1 +0,0 @@ -Subproject commit dfd6ca7bfc1cf0a6ff306cb95bcae62915091301 diff --git a/verilog/mor1kx/submodule b/verilog/mor1kx/submodule deleted file mode 160000 index 64651c8a..00000000 --- a/verilog/mor1kx/submodule +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 64651c8af488a498f059c54fcd9580b1d16ac6c4 -- 2.30.2