From 550c31849024a2184887df87aae39617ebfe0d6a Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Wed, 11 Feb 2015 10:23:27 -0500 Subject: [PATCH] sim: Move the BaseTLB to src/arch/generic/ The TLB-related code is generally architecture dependent and should live in the arch directory to signify that. --HG-- rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py rename : src/sim/tlb.cc => src/arch/generic/tlb.cc rename : src/sim/tlb.hh => src/arch/generic/tlb.hh --- src/arch/alpha/tlb.hh | 2 +- src/arch/arm/stage2_lookup.hh | 1 - src/arch/arm/tlb.hh | 2 +- src/{sim => arch/generic}/BaseTLB.py | 2 +- src/arch/generic/SConscript | 5 +++++ src/{sim => arch/generic}/tlb.cc | 3 ++- src/{sim => arch/generic}/tlb.hh | 6 +++--- src/arch/mips/tlb.hh | 2 +- src/arch/power/tlb.hh | 2 +- src/arch/sparc/tlb.hh | 2 +- src/arch/x86/faults.hh | 2 +- src/arch/x86/tlb.hh | 2 +- src/cpu/base_dyn_inst.hh | 2 +- src/cpu/checker/cpu.cc | 2 +- src/cpu/translation.hh | 2 +- src/sim/SConscript | 3 --- 16 files changed, 21 insertions(+), 19 deletions(-) rename src/{sim => arch/generic}/BaseTLB.py (97%) rename src/{sim => arch/generic}/tlb.cc (98%) rename src/{sim => arch/generic}/tlb.hh (98%) diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index ee59041f3..ccd4362d3 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -39,10 +39,10 @@ #include "arch/alpha/pagetable.hh" #include "arch/alpha/utility.hh" #include "arch/alpha/vtophys.hh" +#include "arch/generic/tlb.hh" #include "base/statistics.hh" #include "mem/request.hh" #include "params/AlphaTLB.hh" -#include "sim/tlb.hh" class ThreadContext; diff --git a/src/arch/arm/stage2_lookup.hh b/src/arch/arm/stage2_lookup.hh index 6706b4724..870276b0a 100755 --- a/src/arch/arm/stage2_lookup.hh +++ b/src/arch/arm/stage2_lookup.hh @@ -47,7 +47,6 @@ #include "arch/arm/table_walker.hh" #include "arch/arm/tlb.hh" #include "mem/request.hh" -#include "sim/tlb.hh" class ThreadContext; diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index f996f2d53..0be569fec 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -48,12 +48,12 @@ #include "arch/arm/pagetable.hh" #include "arch/arm/utility.hh" #include "arch/arm/vtophys.hh" +#include "arch/generic/tlb.hh" #include "base/statistics.hh" #include "dev/dma_device.hh" #include "mem/request.hh" #include "params/ArmTLB.hh" #include "sim/probe/pmu.hh" -#include "sim/tlb.hh" class ThreadContext; diff --git a/src/sim/BaseTLB.py b/src/arch/generic/BaseTLB.py similarity index 97% rename from src/sim/BaseTLB.py rename to src/arch/generic/BaseTLB.py index 8a03413a9..6a8a9727f 100644 --- a/src/sim/BaseTLB.py +++ b/src/arch/generic/BaseTLB.py @@ -31,4 +31,4 @@ from m5.SimObject import SimObject class BaseTLB(SimObject): type = 'BaseTLB' abstract = True - cxx_header = "sim/tlb.hh" + cxx_header = "arch/generic/tlb.hh" diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript index 9d59fa269..c87ad671f 100644 --- a/src/arch/generic/SConscript +++ b/src/arch/generic/SConscript @@ -33,4 +33,9 @@ if env['TARGET_ISA'] == 'null': Source('decode_cache.cc') Source('mmapped_ipr.cc') +Source('tlb.cc') + +SimObject('BaseTLB.py') + +DebugFlag('TLB') Source('pseudo_inst.cc') diff --git a/src/sim/tlb.cc b/src/arch/generic/tlb.cc similarity index 98% rename from src/sim/tlb.cc rename to src/arch/generic/tlb.cc index 00a51dbe3..39ea09b0d 100644 --- a/src/sim/tlb.cc +++ b/src/arch/generic/tlb.cc @@ -28,12 +28,13 @@ * Authors: Gabe Black */ +#include "arch/generic/tlb.hh" + #include "cpu/thread_context.hh" #include "mem/page_table.hh" #include "sim/faults.hh" #include "sim/full_system.hh" #include "sim/process.hh" -#include "sim/tlb.hh" Fault GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode) diff --git a/src/sim/tlb.hh b/src/arch/generic/tlb.hh similarity index 98% rename from src/sim/tlb.hh rename to src/arch/generic/tlb.hh index 9557fa3b1..0a7e78151 100644 --- a/src/sim/tlb.hh +++ b/src/arch/generic/tlb.hh @@ -40,8 +40,8 @@ * Authors: Gabe Black */ -#ifndef __SIM_TLB_HH__ -#define __SIM_TLB_HH__ +#ifndef __ARCH_GENERIC_TLB_HH__ +#define __ARCH_GENERIC_TLB_HH__ #include "base/misc.hh" #include "mem/request.hh" @@ -147,4 +147,4 @@ class GenericTLB : public BaseTLB Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; }; -#endif // __ARCH_SPARC_TLB_HH__ +#endif // __ARCH_GENERIC_TLB_HH__ diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index 225e207dc..c7cd5e631 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -37,6 +37,7 @@ #include +#include "arch/generic/tlb.hh" #include "arch/mips/isa_traits.hh" #include "arch/mips/pagetable.hh" #include "arch/mips/utility.hh" @@ -45,7 +46,6 @@ #include "mem/request.hh" #include "params/MipsTLB.hh" #include "sim/sim_object.hh" -#include "sim/tlb.hh" class ThreadContext; diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh index 0abafc777..9818774d8 100644 --- a/src/arch/power/tlb.hh +++ b/src/arch/power/tlb.hh @@ -39,6 +39,7 @@ #include +#include "arch/generic/tlb.hh" #include "arch/power/isa_traits.hh" #include "arch/power/pagetable.hh" #include "arch/power/utility.hh" @@ -46,7 +47,6 @@ #include "base/statistics.hh" #include "mem/request.hh" #include "params/PowerTLB.hh" -#include "sim/tlb.hh" class ThreadContext; diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 9c027cbbd..1d229fba7 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -31,12 +31,12 @@ #ifndef __ARCH_SPARC_TLB_HH__ #define __ARCH_SPARC_TLB_HH__ +#include "arch/generic/tlb.hh" #include "arch/sparc/asi.hh" #include "arch/sparc/tlb_map.hh" #include "base/misc.hh" #include "mem/request.hh" #include "params/SparcTLB.hh" -#include "sim/tlb.hh" class ThreadContext; class Packet; diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh index b43cda36a..b9eb85e21 100644 --- a/src/arch/x86/faults.hh +++ b/src/arch/x86/faults.hh @@ -42,10 +42,10 @@ #include +#include "arch/generic/tlb.hh" #include "base/bitunion.hh" #include "base/misc.hh" #include "sim/faults.hh" -#include "sim/tlb.hh" namespace X86ISA { diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index e1089f90c..77f9fc49d 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -44,6 +44,7 @@ #include #include +#include "arch/generic/tlb.hh" #include "arch/x86/regs/segment.hh" #include "arch/x86/pagetable.hh" #include "base/trie.hh" @@ -51,7 +52,6 @@ #include "mem/request.hh" #include "params/X86TLB.hh" #include "sim/sim_object.hh" -#include "sim/tlb.hh" class ThreadContext; class Packet; diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 108b799e1..ab275369f 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -51,6 +51,7 @@ #include #include +#include "arch/generic/tlb.hh" #include "arch/utility.hh" #include "base/trace.hh" #include "config/the_isa.hh" @@ -65,7 +66,6 @@ #include "mem/packet.hh" #include "sim/byteswap.hh" #include "sim/system.hh" -#include "sim/tlb.hh" /** * @file diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index d6a8bd032..229066fcc 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -44,6 +44,7 @@ #include #include +#include "arch/generic/tlb.hh" #include "arch/kernel_stats.hh" #include "arch/vtophys.hh" #include "cpu/checker/cpu.hh" @@ -53,7 +54,6 @@ #include "cpu/thread_context.hh" #include "params/CheckerCPU.hh" #include "sim/full_system.hh" -#include "sim/tlb.hh" using namespace std; using namespace TheISA; diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh index f870a9c11..4ff75546a 100644 --- a/src/cpu/translation.hh +++ b/src/cpu/translation.hh @@ -45,8 +45,8 @@ #ifndef __CPU_TRANSLATION_HH__ #define __CPU_TRANSLATION_HH__ +#include "arch/generic/tlb.hh" #include "sim/faults.hh" -#include "sim/tlb.hh" /** * This class captures the state of an address translation. A translation diff --git a/src/sim/SConscript b/src/sim/SConscript index 7583b53cb..400d595e3 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -30,7 +30,6 @@ Import('*') -SimObject('BaseTLB.py') SimObject('ClockedObject.py') SimObject('TickedObject.py') SimObject('Root.py') @@ -75,7 +74,6 @@ if env['TARGET_ISA'] != 'null': Source('process.cc') Source('pseudo_inst.cc') Source('syscall_emul.cc') - Source('tlb.cc') DebugFlag('Checkpoint') DebugFlag('Config') @@ -92,7 +90,6 @@ DebugFlag('PseudoInst') DebugFlag('Stack') DebugFlag('SyscallVerbose') DebugFlag('TimeSync') -DebugFlag('TLB') DebugFlag('Thread') DebugFlag('Timer') DebugFlag('VtoPhys') -- 2.30.2