From 553262bcc14cf112f50eb473cb592f7d0f6958f8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 4 May 2015 12:28:49 +0200 Subject: [PATCH] soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment... --- misoclib/soc/sdram.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 1d96d280..44ad29bc 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -59,8 +59,8 @@ class SDRAMSoC(SoC): l2_size = self.sdram_controller_settings.l2_size if l2_size: - # XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache. - # Issue is reported to Xilinx and should be fixed in next releases (2015.1?). + # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache. + # Issue is reported to Xilinx and should be fixed in next releases (2015.2?). # Remove this workaround when fixed by Xilinx. from mibuild.xilinx.vivado import XilinxVivadoToolchain if isinstance(self.platform.toolchain, XilinxVivadoToolchain): -- 2.30.2