From 5538d058b6ae6c0124036d56ecb94a32907f42be Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 24 Jul 2020 14:42:04 +0100 Subject: [PATCH] too much debug info going past, so add the test registers to the failed log message --- src/soc/fu/div/test/runner.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/fu/div/test/runner.py b/src/soc/fu/div/test/runner.py index e822e41c..5404c773 100644 --- a/src/soc/fu/div/test/runner.py +++ b/src/soc/fu/div/test/runner.py @@ -190,6 +190,7 @@ class DivRunner(unittest.TestCase): # XXX print("time:", sim._state.timeline.now) msg = "%s: %s" % (self.div_pipe_kind.name, code) msg += " %s" % (repr(prog.assembly)) + msg += " %s" % (repr(test.regs)) yield from self.check_alu_outputs(alu, pdecode2, isa_sim, msg) -- 2.30.2