From 553c2cf16b7612d4a70bd96230dad63777ec867e Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 11 May 2020 15:07:25 -0400 Subject: [PATCH] pan/mdg: Set RA bounds for fp16 Signed-off-by: Alyssa Rosenzweig Part-of: --- src/panfrost/midgard/midgard_ra.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index faaa41f2839..e4901eed638 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -525,13 +525,25 @@ allocate_registers(compiler_context *ctx, bool *spilled) (size == 64) ? 3 : /* (1 << 3) = 8-byte */ 3; /* 8-bit todo */ + /* We can't cross xy/zw boundaries. TODO: vec8 can */ + if (size == 16) + min_bound[dest] = 8; + /* We don't have a swizzle for the conditional and we don't * want to muck with the conditional itself, so just force * alignment for now */ - if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->alu.op)) + if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->alu.op)) { min_alignment[dest] = 4; /* 1 << 4= 16-byte = vec4 */ + /* LCRA assumes bound >= alignment */ + min_bound[dest] = 16; + } + + /* Since ld/st swizzles and masks are 32-bit only, we need them + * aligned to enable final packing */ + if (ins->type == TAG_LOAD_STORE_4) + min_alignment[dest] = MAX2(min_alignment[dest], 2); } for (unsigned i = 0; i < ctx->temp_count; ++i) { -- 2.30.2