From 554006bd1a4ac1a43bb386198b69682691c7496f Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Thu, 4 May 2006 11:03:41 +0000 Subject: [PATCH] predicates.md (const01_rtx): Tell generator programs that this only matches CONST_INTs. * config/bfin/predicates.md (const01_rtx): Tell generator programs that this only matches CONST_INTs. All users changed to VOIDmode operands. From-SVN: r113520 --- gcc/ChangeLog | 6 +++++ gcc/config/bfin/bfin.md | 48 +++++++++++++++++------------------ gcc/config/bfin/predicates.md | 3 ++- 3 files changed, 32 insertions(+), 25 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d3195ac0306..14eb262c729 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2006-05-04 Bernd Schmidt + + * config/bfin/predicates.md (const01_rtx): Tell generator programs + that this only matches CONST_INTs. All users changed to VOIDmode + operands. + 2006-05-04 Leehod Baruch * see.c: New file. diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index e8659922107..6992de3ac08 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -459,7 +459,7 @@ { HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16; intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF; - + operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode)); } @@ -2318,7 +2318,7 @@ (define_insn "movv2hi_hi" [(set (match_operand:HI 0 "register_operand" "=d,d,d") (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d") - (parallel [(match_operand:SI 2 "const01_operand" "P0,P0,P1")])))] + (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))] "" "@ /* optimized out */ @@ -2578,10 +2578,10 @@ [(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(vec_select:HI (match_operand:V2HI 1 "register_operand" "d") - (parallel [(match_operand:SI 3 "const01_operand" "P0P1")])) + (parallel [(match_operand 3 "const01_operand" "P0P1")])) (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") - (parallel [(match_operand:SI 4 "const01_operand" "P0P1")])) + (parallel [(match_operand 4 "const01_operand" "P0P1")])) (match_operand 5 "const_int_operand" "n")] UNSPEC_MUL_WITH_FLAG))] "" @@ -2670,15 +2670,15 @@ (unspec:V2HI [(vec_concat:V2HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") - (parallel [(match_operand:SI 3 "const01_operand" "P0P1")])) + (parallel [(match_operand 3 "const01_operand" "P0P1")])) (vec_select:HI (match_dup 1) - (parallel [(match_operand:SI 4 "const01_operand" "P0P1")]))) + (parallel [(match_operand 4 "const01_operand" "P0P1")]))) (vec_concat:V2HI (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") - (parallel [(match_operand:SI 5 "const01_operand" "P0P1")])) + (parallel [(match_operand 5 "const01_operand" "P0P1")])) (vec_select:HI (match_dup 2) - (parallel [(match_operand:SI 6 "const01_operand" "P0P1")]))) + (parallel [(match_operand 6 "const01_operand" "P0P1")]))) (match_operand 7 "const_int_operand" "n")] UNSPEC_MUL_WITH_FLAG))] "" @@ -2718,15 +2718,15 @@ (unspec:V2HI [(vec_concat:V2HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") - (parallel [(match_operand:SI 3 "const01_operand" "P0P1")])) + (parallel [(match_operand 3 "const01_operand" "P0P1")])) (vec_select:HI (match_dup 1) - (parallel [(match_operand:SI 4 "const01_operand" "P0P1")]))) + (parallel [(match_operand 4 "const01_operand" "P0P1")]))) (vec_concat:V2HI (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") - (parallel [(match_operand:SI 5 "const01_operand" "P0P1")])) + (parallel [(match_operand 5 "const01_operand" "P0P1")])) (vec_select:HI (match_dup 2) - (parallel [(match_operand:SI 6 "const01_operand" "P0P1")]))) + (parallel [(match_operand 6 "const01_operand" "P0P1")]))) (match_operand:V2PDI 7 "register_operand" "e") (match_operand 8 "const01_operand" "P0P1") (match_operand 9 "const01_operand" "P0P1") @@ -2771,15 +2771,15 @@ (unspec:V2PDI [(vec_concat:V2HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") - (parallel [(match_operand:SI 3 "const01_operand" "P0P1")])) + (parallel [(match_operand 3 "const01_operand" "P0P1")])) (vec_select:HI (match_dup 1) - (parallel [(match_operand:SI 4 "const01_operand" "P0P1")]))) + (parallel [(match_operand 4 "const01_operand" "P0P1")]))) (vec_concat:V2HI (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") - (parallel [(match_operand:SI 5 "const01_operand" "P0P1")])) + (parallel [(match_operand 5 "const01_operand" "P0P1")])) (vec_select:HI (match_dup 2) - (parallel [(match_operand:SI 6 "const01_operand" "P0P1")]))) + (parallel [(match_operand 6 "const01_operand" "P0P1")]))) (match_operand:V2PDI 7 "register_operand" "e") (match_operand 8 "const01_operand" "P0P1") (match_operand 9 "const01_operand" "P0P1") @@ -2817,15 +2817,15 @@ (unspec:V2HI [(vec_concat:V2HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") - (parallel [(match_operand:SI 3 "const01_operand" "P0P1")])) + (parallel [(match_operand 3 "const01_operand" "P0P1")])) (vec_select:HI (match_dup 1) - (parallel [(match_operand:SI 4 "const01_operand" "P0P1")]))) + (parallel [(match_operand 4 "const01_operand" "P0P1")]))) (vec_concat:V2HI (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") - (parallel [(match_operand:SI 5 "const01_operand" "P0P1")])) + (parallel [(match_operand 5 "const01_operand" "P0P1")])) (vec_select:HI (match_dup 2) - (parallel [(match_operand:SI 6 "const01_operand" "P0P1")]))) + (parallel [(match_operand 6 "const01_operand" "P0P1")]))) (match_operand 7 "const_int_operand" "n")] UNSPEC_MAC_WITH_FLAG)) (set (match_operand:V2PDI 8 "register_operand" "=e") @@ -2867,15 +2867,15 @@ (unspec:V2PDI [(vec_concat:V2HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d") - (parallel [(match_operand:SI 3 "const01_operand" "P0P1")])) + (parallel [(match_operand 3 "const01_operand" "P0P1")])) (vec_select:HI (match_dup 1) - (parallel [(match_operand:SI 4 "const01_operand" "P0P1")]))) + (parallel [(match_operand 4 "const01_operand" "P0P1")]))) (vec_concat:V2HI (vec_select:HI (match_operand:V2HI 2 "register_operand" "d") - (parallel [(match_operand:SI 5 "const01_operand" "P0P1")])) + (parallel [(match_operand 5 "const01_operand" "P0P1")])) (vec_select:HI (match_dup 2) - (parallel [(match_operand:SI 6 "const01_operand" "P0P1")]))) + (parallel [(match_operand 6 "const01_operand" "P0P1")]))) (match_operand 7 "const_int_operand" "n")] UNSPEC_MAC_WITH_FLAG))] "" diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md index ee7de7af315..eccee2be4d2 100644 --- a/gcc/config/bfin/predicates.md +++ b/gcc/config/bfin/predicates.md @@ -57,7 +57,8 @@ (match_code "const_int"))) (define_predicate "const01_operand" - (match_test "op == const0_rtx || op == const1_rtx")) + (and (match_code "const_int") + (match_test "op == const0_rtx || op == const1_rtx"))) (define_predicate "vec_shift_operand" (ior (and (match_code "const_int") -- 2.30.2