From 5540cabc00a5cb6dd3f37ef2b99986cf6243eb09 Mon Sep 17 00:00:00 2001 From: Kajol Jain Date: Wed, 12 Jun 2019 12:32:59 +0530 Subject: [PATCH] arch-power: Added function to modify MSR and SRR1 register * Added general function to modify MSR and SRR1 register. * Added macros to get mask for * Set particular bit. * Unset Bit. Change-Id: I17b82f6ef7f7d8915f9c1320f99fc6f3f9ecaf74 Signed-off-by: Kajol Jain --- src/arch/power/faults.hh | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh index bfb4dd00f..e328922a9 100644 --- a/src/arch/power/faults.hh +++ b/src/arch/power/faults.hh @@ -36,6 +36,11 @@ #include "cpu/thread_context.hh" #include "sim/faults.hh" +#define setbit(shift, mask) ( (uint64_t)1 << shift | mask) +#define unsetbit(shift,mask) ( ~((uint64_t)1 << shift) & mask) +#define setBitMask(shift) ( (uint64_t)1 << shift) +#define unsetMask(start ,end)(~((setBitMask(start))-1) | ((setBitMask(end))-1)) + namespace PowerISA { @@ -94,6 +99,35 @@ class PowerInterrupt : public PowerFaultBase : PowerFaultBase("Interrupt") { } + virtual void updateMsr(ThreadContext * tc) + { + Msr msr = tc->readIntReg(INTREG_MSR); + msr.tm = 0; + msr.vec = 0; + msr.vsx = 0; + msr.fp = 0; + msr.pr = 0; + msr.pmm = 0; + msr.ir = 0; + msr.dr = 0; + msr.fe1 = 0; + msr.fe0 = 0; + msr.ee = 0; + msr.ri = 0; + msr.te = 0; + msr.sf = 1; + msr = unsetbit(5, msr); + tc->setIntReg(INTREG_MSR, msr); + } + + virtual void updateSRR1(ThreadContext *tc, uint64_t BitMask=0x0000000) + { + Msr msr = tc->readIntReg(INTREG_MSR); + uint64_t srr1 = ((msr & unsetMask(31, 27)) & unsetMask(22,16)) | BitMask; + tc->setIntReg(INTREG_SRR1, srr1); + } +}; + }; -- 2.30.2