From 5558865cbf1ee4b8764777279d60798cb9f9dc5d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 11 Feb 2020 18:21:41 +0100 Subject: [PATCH] soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region --- litex/soc/integration/soc_core.py | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 8338da15..ce4a2edd 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -135,6 +135,8 @@ class SoCCore(LiteXSoC): self.with_wishbone = with_wishbone self.wishbone_timeout_cycles = wishbone_timeout_cycles + self.wb_slaves = {} + # Modules instances ------------------------------------------------------------------------ # Add SoCController @@ -195,7 +197,10 @@ class SoCCore(LiteXSoC): if address == region.origin: wb_name = name break - self.bus.add_slave(name=wb_name, slave=interface) + if wb_name is None: + self.wb_slaves[address] = interface + else: + self.bus.add_slave(name=wb_name, slave=interface) def add_memory_region(self, name, origin, length, type="cached"): self.bus.add_region(name, SoCRegion(origin=origin, size=length, @@ -214,6 +219,15 @@ class SoCCore(LiteXSoC): # Finalization --------------------------------------------------------------------------------- def do_finalize(self): + # Retro-compatibility + for address, interface in self.wb_slaves.items(): + wb_name = None + for name, region in self.bus.regions.items(): + if address == region.origin: + wb_name = name + break + self.bus.add_slave(name=wb_name, slave=interface) + SoC.do_finalize(self) # Retro-compatibility for region in self.bus.regions.values(): -- 2.30.2