From 555bab5c6431951aab359cc31ba31ede9c12f64f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 25 May 2020 01:11:49 +0100 Subject: [PATCH] mention zeroing --- src/soc/experiment/compldst_multi.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index 4749f4a3..048e5b4c 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -259,6 +259,8 @@ class LDSTCompUnit(Elaboratable): alu_o = Signal(self.rwid, reset_less=True) ldd_o = Signal(self.rwid, reset_less=True) + # XXX TODO ZEROing just lije in ComUnit + # select immediate or src2 reg to add src2_or_imm = Signal(self.rwid, reset_less=True) src_sel = Signal(reset_less=True) -- 2.30.2