From 556b2fbd240bff5d20c5137827757e053c00c3a8 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Tue, 14 Apr 2015 22:06:47 -0700 Subject: [PATCH] i965: Make a helper function intel_miptree_set_total_width_height() and some more code refactoring. No functional changes in this patch. Signed-off-by: Anuj Phogat Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 93 ++++++++++++---------- 1 file changed, 50 insertions(+), 43 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 9a2a331fcb7..312a8873afe 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -710,50 +710,10 @@ brw_miptree_choose_tiling(struct brw_context *brw, return I915_TILING_Y | I915_TILING_X; } - -void -brw_miptree_layout(struct brw_context *brw, - bool for_bo, - enum intel_miptree_tiling_mode requested, - struct intel_mipmap_tree *mt) +static void +intel_miptree_set_total_width_height(struct brw_context *brw, + struct intel_mipmap_tree *mt) { - bool gen6_hiz_or_stencil = false; - - mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE; - - if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) { - const GLenum base_format = _mesa_get_format_base_format(mt->format); - gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format); - } - - if (gen6_hiz_or_stencil) { - /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the - * hardware doesn't support multiple mip levels on stencil/hiz. - * - * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer: - * "The hierarchical depth buffer does not support the LOD field" - * - * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer: - * "The stencil depth buffer does not support the LOD field" - */ - if (mt->format == MESA_FORMAT_S_UINT8) { - /* Stencil uses W tiling, so we force W tiling alignment for the - * ALL_SLICES_AT_EACH_LOD miptree layout. - */ - mt->align_w = 64; - mt->align_h = 64; - } else { - /* Depth uses Y tiling, so we force need Y tiling alignment for the - * ALL_SLICES_AT_EACH_LOD miptree layout. - */ - mt->align_w = 128 / mt->cpp; - mt->align_h = 32; - } - } else { - mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt); - mt->align_h = intel_vertical_texture_alignment_unit(brw, mt); - } - switch (mt->target) { case GL_TEXTURE_CUBE_MAP: if (brw->gen == 4) { @@ -796,8 +756,55 @@ brw_miptree_layout(struct brw_context *brw, } break; } + DBG("%s: %dx%dx%d\n", __func__, mt->total_width, mt->total_height, mt->cpp); +} + +void +brw_miptree_layout(struct brw_context *brw, + bool for_bo, + enum intel_miptree_tiling_mode requested, + struct intel_mipmap_tree *mt) +{ + bool gen6_hiz_or_stencil = false; + + mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE; + + if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) { + const GLenum base_format = _mesa_get_format_base_format(mt->format); + gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format); + } + + if (gen6_hiz_or_stencil) { + /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the + * hardware doesn't support multiple mip levels on stencil/hiz. + * + * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer: + * "The hierarchical depth buffer does not support the LOD field" + * + * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer: + * "The stencil depth buffer does not support the LOD field" + */ + if (mt->format == MESA_FORMAT_S_UINT8) { + /* Stencil uses W tiling, so we force W tiling alignment for the + * ALL_SLICES_AT_EACH_LOD miptree layout. + */ + mt->align_w = 64; + mt->align_h = 64; + } else { + /* Depth uses Y tiling, so we force need Y tiling alignment for the + * ALL_SLICES_AT_EACH_LOD miptree layout. + */ + mt->align_w = 128 / mt->cpp; + mt->align_h = 32; + } + } else { + mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt); + mt->align_h = intel_vertical_texture_alignment_unit(brw, mt); + } + + intel_miptree_set_total_width_height(brw, mt); if (!mt->total_width || !mt->total_height) { intel_miptree_release(&mt); -- 2.30.2