From 557351e7da53e4f09b16fe9b729ddd425ff04a15 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 20 Feb 2021 16:40:41 +0000 Subject: [PATCH] increment CRs based on srcstep, see what happens --- src/soc/decoder/power_decoder2.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index a5fde3b3..8a3591fe 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -1168,7 +1168,10 @@ class PowerDecode2(PowerDecodeSubset): comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA) - comb += to_reg.data.eq(svdec.cr_out) # 7-bit output + with m.If(svdec.isvec): + comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit output + with m.Else(): + comb += to_reg.data.eq(svdec.cr_out) # 7-bit output comb += to_reg.ok.eq(fromreg.ok) # sigh this is exactly the sort of thing for which the -- 2.30.2