From 55a265d967de97dc1284ddb6f464d3eecb0b3696 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 17 Feb 2012 23:52:06 +0100 Subject: [PATCH] bank: add RE signal for registers made of fields --- migen/bank/csrgen.py | 1 + migen/bank/description.py | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py index c8765089..fed5058d 100644 --- a/migen/bank/csrgen.py +++ b/migen/bank/csrgen.py @@ -34,6 +34,7 @@ class Bank: bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size])) offset += field.size if len(bwra) > 1: + bwra.append(reg.re.eq(1)) bwcases.append(bwra) else: raise TypeError diff --git a/migen/bank/description.py b/migen/bank/description.py index 415ed809..4c9b5b6d 100644 --- a/migen/bank/description.py +++ b/migen/bank/description.py @@ -27,9 +27,13 @@ class Field: self.we = Signal() class RegisterFields: - def __init__(self, name, fields): + def __init__(self, name, fields, re=None): self.name = name self.fields = fields + if re is None: + self.re = Signal() + else: + self.re = re class RegisterField(RegisterFields): def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0): @@ -71,7 +75,7 @@ def expand_description(description, busword): else: f.append(field) if f: - d.append(RegisterFields(reg.name, f)) + d.append(RegisterFields(reg.name, f, reg.re)) else: raise TypeError return d -- 2.30.2