From 55ab38d9c0f5468273c3926788ef53c5c8e44d12 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 10 Sep 2020 17:13:13 +0100 Subject: [PATCH] correct some errors introduced in dcache.py --- src/soc/experiment/dcache.py | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 32f7602d..b4411729 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -452,7 +452,7 @@ class DCache(Elaboratable): comb = m.d.comb sync = m.d.sync - index = Signal(log2_int(TLB_SET_BITS), False) + index = Signal(TLB_SET_BITS) addrbits = Signal(TLB_SET_BITS) amin = TLB_LG_PGSZ @@ -481,6 +481,7 @@ class DCache(Elaboratable): for i in range(TLB_SET_SIZE): # TLB PLRU interface tlb_plru = PLRU(TLB_WAY_BITS) + setattr(m.submodules, "maybe_plru_%d" % i, tlb_plru) tlb_plru_acc = Signal(TLB_WAY_BITS) tlb_plru_acc_en = Signal() tlb_plru_out = Signal(TLB_WAY_BITS) @@ -506,7 +507,7 @@ class DCache(Elaboratable): hitway = Signal(TLB_WAY_BITS) hit = Signal() - eatag = Signal(log2_int(TLB_EA_TAG_BITS, False)) + eatag = Signal(TLB_EA_TAG_BITS) TLB_LG_END = TLB_LG_PGSZ + TLB_SET_BITS comb += tlb_req_index.eq(r0.req.addr[TLB_LG_PGSZ : TLB_LG_END]) @@ -549,15 +550,6 @@ class DCache(Elaboratable): comb = m.d.comb sync = m.d.sync - # variable tlbie : std_ulogic; - # variable tlbwe : std_ulogic; - # variable repl_way : tlb_way_t; - # variable eatag : tlb_tag_t; - # variable tagset : tlb_way_tags_t; - # variable pteset : tlb_way_ptes_t; - #type tlb_tags_t is array(tlb_index_t) of tlb_way_tags_t; - # --> Array([Signal(log(way_tags length)) for i in range(number of tlbs)]) - tlbie = Signal() tlbwe = Signal() repl_way = Signal(TLB_WAY_BITS) @@ -600,9 +592,9 @@ class DCache(Elaboratable): # PLRU interface plru = PLRU(TLB_WAY_BITS) setattr(m.submodules, "plru%d" % i, plru) - plru_acc = Signal(TLB_WAY_BITS) + plru_acc = Signal(WAY_BITS) plru_acc_en = Signal() - plru_out = Signal(TLB_WAY_BITS) + plru_out = Signal(WAY_BITS) comb += plru.acc.eq(plru_acc) comb += plru.acc_en.eq(plru_acc_en) @@ -833,7 +825,6 @@ class DCache(Elaboratable): data_out = Signal(64) data_fwd = Signal(64) - j = Signal() # Use the bypass if are reading the row that was # written 1 or 2 cycles ago, including for the @@ -989,7 +980,7 @@ class DCache(Elaboratable): # Cache hit synchronous machine for the easy case. # This handles load hits. # It also handles error cases (TLB miss, cache paradox) - def dcache_fast_hit(self, m, req_op, r0_valid, r1, ): + def dcache_fast_hit(self, m, req_op, r0_valid, r1): comb = m.d.comb sync = m.d.sync -- 2.30.2